1 /*
2 * PPC-AG BG0900 board
3 *
4 * Copyright (C) 2013 Marek Vasut <marex@denx.de>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9 #include <common.h>
10 #include <asm/gpio.h>
11 #include <asm/io.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/iomux-mx28.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/sys_proto.h>
16 #include <linux/mii.h>
17 #include <miiphy.h>
18 #include <netdev.h>
19 #include <errno.h>
20
21 DECLARE_GLOBAL_DATA_PTR;
22
23 /*
24 * Functions
25 */
board_early_init_f(void)26 int board_early_init_f(void)
27 {
28 /* IO0 clock at 480MHz */
29 mxs_set_ioclk(MXC_IOCLK0, 480000);
30 /* IO1 clock at 480MHz */
31 mxs_set_ioclk(MXC_IOCLK1, 480000);
32
33 /* SSP2 clock at 160MHz */
34 mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
35
36 return 0;
37 }
38
dram_init(void)39 int dram_init(void)
40 {
41 return mxs_dram_init();
42 }
43
board_init(void)44 int board_init(void)
45 {
46 /* Adress of boot parameters */
47 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
48
49 return 0;
50 }
51
52 #ifdef CONFIG_CMD_NET
board_eth_init(bd_t * bis)53 int board_eth_init(bd_t *bis)
54 {
55 struct mxs_clkctrl_regs *clkctrl_regs =
56 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
57 struct eth_device *dev;
58 int ret;
59
60 ret = cpu_eth_init(bis);
61
62 /* BG0900 uses ENET_CLK PAD to drive FEC clock */
63 writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN,
64 &clkctrl_regs->hw_clkctrl_enet);
65
66 /* Reset FEC PHYs */
67 gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
68 udelay(200);
69 gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
70
71 ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
72 if (ret) {
73 puts("FEC MXS: Unable to init FEC0\n");
74 return ret;
75 }
76
77 dev = eth_get_dev_by_name("FEC0");
78 if (!dev) {
79 puts("FEC MXS: Unable to get FEC0 device entry\n");
80 return -EINVAL;
81 }
82
83 return ret;
84 }
85
86 #endif
87