1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2017 Logic PD, Inc. 3*4882a593Smuzhiyun * Adam Ford <aford173@gmail.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Refer doc/README.imximage for more details about how-to configure 8*4882a593Smuzhiyun * and create imximage boot image 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * The syntax is taken as close as possible with the kwbimage 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun#include <asm/mach-imx/imximage.cfg> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun/* image version */ 16*4882a593SmuzhiyunIMAGE_VERSION 2 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunBOOT_OFFSET FLASH_OFFSET_STANDARD 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun/* 21*4882a593Smuzhiyun * Device Configuration Data (DCD) 22*4882a593Smuzhiyun * 23*4882a593Smuzhiyun * Each entry must have the format: 24*4882a593Smuzhiyun * Addr-type Address Value 25*4882a593Smuzhiyun * 26*4882a593Smuzhiyun * where: 27*4882a593Smuzhiyun * Addr-type register length (1,2 or 4 bytes) 28*4882a593Smuzhiyun * Address absolute address of the register 29*4882a593Smuzhiyun * value value to be stored in the register 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun#define __ASSEMBLY__ 33*4882a593Smuzhiyun#include <config.h> 34*4882a593Smuzhiyun#include "asm/arch-mx6/mx6-ddr.h" 35*4882a593Smuzhiyun#include "asm/arch-mx6/iomux.h" 36*4882a593Smuzhiyun#include "asm/arch-mx6/crm_regs.h" 37*4882a593Smuzhiyun 38*4882a593SmuzhiyunDATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 39*4882a593SmuzhiyunDATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 40*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030 41*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030 42*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_CAS, 0x00000030 43*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_RAS, 0x00000030 44*4882a593SmuzhiyunDATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 45*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_RESET, 0x00000030 46*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 47*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDODT0, 0x00000030 48*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDODT1, 0x00000030 49*4882a593SmuzhiyunDATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 50*4882a593SmuzhiyunDATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 51*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 52*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 53*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 54*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 55*4882a593SmuzhiyunDATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 56*4882a593SmuzhiyunDATA 4, MX6_IOM_GRP_B0DS, 0x00000030 57*4882a593SmuzhiyunDATA 4, MX6_IOM_GRP_B1DS, 0x00000030 58*4882a593SmuzhiyunDATA 4, MX6_IOM_GRP_B2DS, 0x00000030 59*4882a593SmuzhiyunDATA 4, MX6_IOM_GRP_B3DS, 0x00000030 60*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 61*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 62*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 63*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 64*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 65*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 66*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A 67*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B 68*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x03340338 69*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0334032C 70*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4036383C 71*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x2E384038 72*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 73*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 74*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 75*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 76*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 77*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 78*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 79*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDCFG0, 0xB8BE7955 80*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64 81*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB 82*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDMISC, 0x00011740 83*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 84*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 85*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDOR, 0x00BE1023 86*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDASP, 0x00000047 87*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDCTL, 0x85190000 88*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x00888032 89*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 90*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x00008031 91*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x19408030 92*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 93*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDREF, 0x00007800 94*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007 95*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 96*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 97*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun/* set the default clock gate to save power */ 100*4882a593SmuzhiyunDATA 4, CCM_CCGR0, 0x00C03F3F 101*4882a593SmuzhiyunDATA 4, CCM_CCGR1, 0x0030FC03 102*4882a593SmuzhiyunDATA 4, CCM_CCGR2, 0x0FFFC000 103*4882a593SmuzhiyunDATA 4, CCM_CCGR3, 0x3FF00000 104*4882a593SmuzhiyunDATA 4, CCM_CCGR4, 0xFFFFF300 105*4882a593SmuzhiyunDATA 4, CCM_CCGR5, 0x0F0000F3 106*4882a593SmuzhiyunDATA 4, CCM_CCGR6, 0x00000FFF 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun/* enable AXI cache for VDOA/VPU/IPU */ 109*4882a593SmuzhiyunDATA 4 MX6_IOMUXC_GPR4 0xF00000CF 110*4882a593Smuzhiyun/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ 111*4882a593SmuzhiyunDATA 4 MX6_IOMUXC_GPR6 0x007F007F 112*4882a593SmuzhiyunDATA 4 MX6_IOMUXC_GPR7 0x007F007F 113