1/* 2 * Copyright (C) 2017 Logic PD, Inc. 3 * Adam Ford <aford173@gmail.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 * 7 * Refer doc/README.imximage for more details about how-to configure 8 * and create imximage boot image 9 * 10 * The syntax is taken as close as possible with the kwbimage 11 */ 12 13#include <asm/mach-imx/imximage.cfg> 14 15/* image version */ 16IMAGE_VERSION 2 17 18BOOT_OFFSET FLASH_OFFSET_STANDARD 19 20/* 21 * Device Configuration Data (DCD) 22 * 23 * Each entry must have the format: 24 * Addr-type Address Value 25 * 26 * where: 27 * Addr-type register length (1,2 or 4 bytes) 28 * Address absolute address of the register 29 * value value to be stored in the register 30 */ 31 32#define __ASSEMBLY__ 33#include <config.h> 34#include "asm/arch-mx6/mx6-ddr.h" 35#include "asm/arch-mx6/iomux.h" 36#include "asm/arch-mx6/crm_regs.h" 37 38DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 39DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 40DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030 41DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030 42DATA 4, MX6_IOM_DRAM_CAS, 0x00000030 43DATA 4, MX6_IOM_DRAM_RAS, 0x00000030 44DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 45DATA 4, MX6_IOM_DRAM_RESET, 0x00000030 46DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 47DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000030 48DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000030 49DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 50DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 51DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 52DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 53DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 54DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 55DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 56DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 57DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 58DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 59DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 60DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 61DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 62DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 63DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 64DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 65DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 66DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A 67DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B 68DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x03340338 69DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0334032C 70DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4036383C 71DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x2E384038 72DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 73DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 74DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 75DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 76DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 77DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 78DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 79DATA 4, MX6_MMDC_P0_MDCFG0, 0xB8BE7955 80DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64 81DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB 82DATA 4, MX6_MMDC_P0_MDMISC, 0x00011740 83DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 84DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 85DATA 4, MX6_MMDC_P0_MDOR, 0x00BE1023 86DATA 4, MX6_MMDC_P0_MDASP, 0x00000047 87DATA 4, MX6_MMDC_P0_MDCTL, 0x85190000 88DATA 4, MX6_MMDC_P0_MDSCR, 0x00888032 89DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 90DATA 4, MX6_MMDC_P0_MDSCR, 0x00008031 91DATA 4, MX6_MMDC_P0_MDSCR, 0x19408030 92DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 93DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 94DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007 95DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 96DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 97DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 98 99/* set the default clock gate to save power */ 100DATA 4, CCM_CCGR0, 0x00C03F3F 101DATA 4, CCM_CCGR1, 0x0030FC03 102DATA 4, CCM_CCGR2, 0x0FFFC000 103DATA 4, CCM_CCGR3, 0x3FF00000 104DATA 4, CCM_CCGR4, 0xFFFFF300 105DATA 4, CCM_CCGR5, 0x0F0000F3 106DATA 4, CCM_CCGR6, 0x00000FFF 107 108/* enable AXI cache for VDOA/VPU/IPU */ 109DATA 4 MX6_IOMUXC_GPR4 0xF00000CF 110/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ 111DATA 4 MX6_IOMUXC_GPR6 0x007F007F 112DATA 4 MX6_IOMUXC_GPR7 0x007F007F 113