1 /*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * Authors: Roy Zang <tie-fei.zang@freescale.com>
5 * Chunhe Lan <Chunhe.Lan@freescale.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10 #include <common.h>
11 #include <command.h>
12 #include <pci.h>
13 #include <asm/io.h>
14 #include <asm/cache.h>
15 #include <asm/processor.h>
16 #include <asm/mmu.h>
17 #include <asm/immap_85xx.h>
18 #include <asm/fsl_pci.h>
19 #include <fsl_ddr_sdram.h>
20 #include <asm/fsl_portals.h>
21 #include <fsl_qbman.h>
22 #include <linux/libfdt.h>
23 #include <fdt_support.h>
24 #include <netdev.h>
25 #include <malloc.h>
26 #include <fm_eth.h>
27 #include <fsl_mdio.h>
28 #include <miiphy.h>
29 #include <phy.h>
30 #include <fsl_dtsec.h>
31
32 DECLARE_GLOBAL_DATA_PTR;
33
board_early_init_f(void)34 int board_early_init_f(void)
35 {
36 fsl_lbc_t *lbc = LBC_BASE_ADDR;
37
38 /* Set ABSWP to implement conversion of addresses in the LBC */
39 setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
40
41 return 0;
42 }
43
checkboard(void)44 int checkboard(void)
45 {
46 printf("Board: P1023 RDB\n");
47
48 return 0;
49 }
50
51 #ifdef CONFIG_PCI
pci_init_board(void)52 void pci_init_board(void)
53 {
54 fsl_pcie_init_board(0);
55 }
56 #endif
57
board_early_init_r(void)58 int board_early_init_r(void)
59 {
60 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
61 int flash_esel = find_tlb_idx((void *)flashbase, 1);
62
63 /*
64 * Remap Boot flash + PROMJET region to caching-inhibited
65 * so that flash can be erased properly.
66 */
67
68 /* Flush d-cache and invalidate i-cache of any FLASH data */
69 flush_dcache();
70 invalidate_icache();
71
72 if (flash_esel == -1) {
73 /* very unlikely unless something is messed up */
74 puts("Error: Could not find TLB for FLASH BASE\n");
75 flash_esel = 2; /* give our best effort to continue */
76 } else {
77 /* invalidate existing TLB entry for flash + promjet */
78 disable_tlb(flash_esel);
79 }
80
81 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
82 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
83 0, flash_esel, BOOKE_PAGESZ_256M, 1);
84
85 setup_portals();
86
87 return 0;
88 }
89
get_board_sys_clk(ulong dummy)90 unsigned long get_board_sys_clk(ulong dummy)
91 {
92 return gd->bus_clk;
93 }
94
get_board_ddr_clk(ulong dummy)95 unsigned long get_board_ddr_clk(ulong dummy)
96 {
97 return gd->mem_clk;
98 }
99
board_eth_init(bd_t * bis)100 int board_eth_init(bd_t *bis)
101 {
102 ccsr_gur_t *gur = (ccsr_gur_t *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
103 struct fsl_pq_mdio_info dtsec_mdio_info;
104
105 /*
106 * Need to set dTSEC 1 pin multiplexing to TSEC. The default setting
107 * is not correct.
108 */
109 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TSEC1_1);
110
111 dtsec_mdio_info.regs =
112 (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
113 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
114
115 /* Register the 1G MDIO bus */
116 fsl_pq_mdio_init(bis, &dtsec_mdio_info);
117
118 fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
119 fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
120
121 fm_info_set_mdio(FM1_DTSEC1,
122 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
123 fm_info_set_mdio(FM1_DTSEC2,
124 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
125
126 #ifdef CONFIG_FMAN_ENET
127 cpu_eth_init(bis);
128 #endif
129
130 return pci_eth_init(bis);
131 }
132
133 #if defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,bd_t * bd)134 int ft_board_setup(void *blob, bd_t *bd)
135 {
136 phys_addr_t base;
137 phys_size_t size;
138
139 ft_cpu_setup(blob, bd);
140
141 base = env_get_bootm_low();
142 size = env_get_bootm_size();
143
144 fdt_fixup_memory(blob, (u64)base, (u64)size);
145
146 #ifdef CONFIG_HAS_FSL_DR_USB
147 fsl_fdt_fixup_dr_usb(blob, bd);
148 #endif
149
150 fdt_fixup_fman_ethernet(blob);
151
152 return 0;
153 }
154 #endif
155