1 /*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <common.h>
8 #include <fsl_ddr_sdram.h>
9 #include <fsl_ddr_dimm_params.h>
10 #ifdef CONFIG_FSL_DEEP_SLEEP
11 #include <fsl_sleep.h>
12 #endif
13 #include <asm/arch/clock.h>
14 #include "ddr.h"
15
16 DECLARE_GLOBAL_DATA_PTR;
17
fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)18 void fsl_ddr_board_options(memctl_options_t *popts,
19 dimm_params_t *pdimm,
20 unsigned int ctrl_num)
21 {
22 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
23 ulong ddr_freq;
24
25 if (ctrl_num > 3) {
26 printf("Not supported controller number %d\n", ctrl_num);
27 return;
28 }
29 if (!pdimm->n_ranks)
30 return;
31
32 pbsp = udimms[0];
33
34 /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
35 * freqency and n_banks specified in board_specific_parameters table.
36 */
37 ddr_freq = get_ddr_freq(0) / 1000000;
38 while (pbsp->datarate_mhz_high) {
39 if (pbsp->n_ranks == pdimm->n_ranks) {
40 if (ddr_freq <= pbsp->datarate_mhz_high) {
41 popts->clk_adjust = pbsp->clk_adjust;
42 popts->wrlvl_start = pbsp->wrlvl_start;
43 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
44 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
45 popts->cpo_override = pbsp->cpo_override;
46 popts->write_data_delay =
47 pbsp->write_data_delay;
48 goto found;
49 }
50 pbsp_highest = pbsp;
51 }
52 pbsp++;
53 }
54
55 if (pbsp_highest) {
56 printf("Error: board specific timing not found for %lu MT/s\n",
57 ddr_freq);
58 printf("Trying to use the highest speed (%u) parameters\n",
59 pbsp_highest->datarate_mhz_high);
60 popts->clk_adjust = pbsp_highest->clk_adjust;
61 popts->wrlvl_start = pbsp_highest->wrlvl_start;
62 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
63 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
64 } else {
65 panic("DIMM is not supported by this board");
66 }
67 found:
68 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
69 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
70
71 /* force DDR bus width to 32 bits */
72 popts->data_bus_width = 1;
73 popts->otf_burst_chop_en = 0;
74 popts->burst_length = DDR_BL8;
75 popts->bstopre = 0; /* enable auto precharge */
76
77 /*
78 * Factors to consider for half-strength driver enable:
79 * - number of DIMMs installed
80 */
81 popts->half_strength_driver_enable = 1;
82 /*
83 * Write leveling override
84 */
85 popts->wrlvl_override = 1;
86 popts->wrlvl_sample = 0xf;
87
88 /*
89 * Rtt and Rtt_WR override
90 */
91 popts->rtt_override = 0;
92
93 /* Enable ZQ calibration */
94 popts->zq_en = 1;
95
96 #ifdef CONFIG_SYS_FSL_DDR4
97 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
98 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
99 DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
100
101 /* optimize cpo for erratum A-009942 */
102 popts->cpo_sample = 0x59;
103 #else
104 popts->cswl_override = DDR_CSWL_CS0;
105
106 /* DHC_EN =1, ODT = 75 Ohm */
107 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
108 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
109 #endif
110 }
111
fsl_initdram(void)112 int fsl_initdram(void)
113 {
114 phys_size_t dram_size;
115
116 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
117 gd->ram_size = fsl_ddr_sdram_size();
118
119 return 0;
120 #else
121 puts("Initializing DDR....using SPD\n");
122
123 dram_size = fsl_ddr_sdram();
124 #endif
125 erratum_a008850_post();
126
127 #ifdef CONFIG_FSL_DEEP_SLEEP
128 fsl_dp_ddr_restore();
129 #endif
130
131 gd->ram_size = dram_size;
132
133 return 0;
134 }
135