1 /*
2 * (C) Copyright 2011
3 * egnite GmbH <info@egnite.de>
4 *
5 * (C) Copyright 2010
6 * Ole Reinhardt <ole.reinhardt@thermotemp.de>
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11 /*
12 * Ethernut 5 general board support
13 *
14 * Ethernut is an open source hardware and software project for
15 * embedded Ethernet devices. Hardware layouts and CAD files are
16 * freely available under BSD-like license.
17 *
18 * Ethernut 5 is the first member of the Ethernut board family
19 * with U-Boot and Linux support. This implementation is based
20 * on the original work done by Ole Reinhardt, but heavily modified
21 * to support additional features and the latest board revision 5.0F.
22 *
23 * Main board components are by default:
24 *
25 * Atmel AT91SAM9XE512 CPU with 512 kBytes NOR Flash
26 * 2 x 64 MBytes Micron MT48LC32M16A2P SDRAM
27 * 512 MBytes Micron MT29F4G08ABADA NAND Flash
28 * 4 MBytes Atmel AT45DB321D DataFlash
29 * SMSC LAN8710 Ethernet PHY
30 * Atmel ATmega168 MCU used for power management
31 * Linear Technology LTC4411 PoE controller
32 *
33 * U-Boot relevant board interfaces are:
34 *
35 * 100 Mbit Ethernet with IEEE 802.3af PoE
36 * RS-232 serial port
37 * USB host and device
38 * MMC/SD-Card slot
39 * Expansion port with I2C, SPI and more...
40 *
41 * Typically the U-Boot image is loaded from serial DataFlash into
42 * SDRAM by the samboot boot loader, which is located in internal
43 * NOR Flash and provides all essential initializations like CPU
44 * and peripheral clocks and, of course, the SDRAM configuration.
45 *
46 * For testing purposes it is also possibly to directly transfer
47 * the image into SDRAM via JTAG. A tested configuration exists
48 * for the Turtelizer 2 hardware dongle and the OpenOCD software.
49 * In this case the latter will do the basic hardware configuration
50 * via its reset-init script.
51 *
52 * For additional information visit the project home page at
53 * http://www.ethernut.de/
54 */
55
56 #include <common.h>
57 #include <net.h>
58 #include <netdev.h>
59 #include <miiphy.h>
60 #include <i2c.h>
61 #include <mmc.h>
62 #include <atmel_mci.h>
63
64 #include <asm/arch/at91sam9260.h>
65 #include <asm/arch/at91sam9260_matrix.h>
66 #include <asm/arch/at91sam9_smc.h>
67 #include <asm/arch/at91_common.h>
68 #include <asm/arch/clk.h>
69 #include <asm/arch/gpio.h>
70 #include <asm/io.h>
71 #include <asm/gpio.h>
72
73 #include "ethernut5_pwrman.h"
74
75 DECLARE_GLOBAL_DATA_PTR;
76
77 /*
78 * This is called last during early initialization. Most of the basic
79 * hardware interfaces are up and running.
80 *
81 * The SDRAM hardware has been configured by the first stage boot loader.
82 * We only need to announce its size, using u-boot's memory check.
83 */
dram_init(void)84 int dram_init(void)
85 {
86 gd->ram_size = get_ram_size(
87 (void *)CONFIG_SYS_SDRAM_BASE,
88 CONFIG_SYS_SDRAM_SIZE);
89 return 0;
90 }
91
92 #ifdef CONFIG_CMD_NAND
ethernut5_nand_hw_init(void)93 static void ethernut5_nand_hw_init(void)
94 {
95 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
96 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
97 unsigned long csa;
98
99 /* Assign CS3 to NAND/SmartMedia Interface */
100 csa = readl(&matrix->ebicsa);
101 csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
102 writel(csa, &matrix->ebicsa);
103
104 /* Configure SMC CS3 for NAND/SmartMedia */
105 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
106 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
107 &smc->cs[3].setup);
108 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
109 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
110 &smc->cs[3].pulse);
111 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
112 &smc->cs[3].cycle);
113 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
114 AT91_SMC_MODE_EXNW_DISABLE |
115 AT91_SMC_MODE_DBW_8 |
116 AT91_SMC_MODE_TDF_CYCLE(2),
117 &smc->cs[3].mode);
118
119 #ifdef CONFIG_SYS_NAND_READY_PIN
120 /* Ready pin is optional. */
121 at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
122 #endif
123 gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
124 }
125 #endif
126
127 /*
128 * This is called first during late initialization.
129 */
board_init(void)130 int board_init(void)
131 {
132 at91_periph_clk_enable(ATMEL_ID_PIOA);
133 at91_periph_clk_enable(ATMEL_ID_PIOB);
134 at91_periph_clk_enable(ATMEL_ID_PIOC);
135
136 /* Set adress of boot parameters. */
137 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
138 /* Initialize UARTs and power management. */
139 ethernut5_power_init();
140 #ifdef CONFIG_CMD_NAND
141 ethernut5_nand_hw_init();
142 #endif
143 return 0;
144 }
145
146 #ifdef CONFIG_MACB
147 /*
148 * This is optionally called last during late initialization.
149 */
board_eth_init(bd_t * bis)150 int board_eth_init(bd_t *bis)
151 {
152 const char *devname;
153 unsigned short mode;
154
155 at91_periph_clk_enable(ATMEL_ID_EMAC0);
156
157 /* Need to reset PHY via power management. */
158 ethernut5_phy_reset();
159 /* Set peripheral pins. */
160 at91_macb_hw_init();
161 /* Basic EMAC initialization. */
162 if (macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, CONFIG_PHY_ID))
163 return -1;
164 /*
165 * Early board revisions have a pull-down at the PHY's MODE0
166 * strap pin, which forces the PHY into power down. Here we
167 * switch to all-capable mode.
168 */
169 devname = miiphy_get_current_dev();
170 if (miiphy_read(devname, 0, 18, &mode) == 0) {
171 /* Set mode[2:0] to 0b111. */
172 mode |= 0x00E0;
173 miiphy_write(devname, 0, 18, mode);
174 /* Soft reset overrides strap pins. */
175 miiphy_write(devname, 0, MII_BMCR, BMCR_RESET);
176 }
177 /* Sync environment with network devices, needed for nfsroot. */
178 return eth_init();
179 }
180 #endif
181
182 #ifdef CONFIG_GENERIC_ATMEL_MCI
board_mmc_init(bd_t * bd)183 int board_mmc_init(bd_t *bd)
184 {
185 at91_periph_clk_enable(ATMEL_ID_MCI);
186
187 /* Initialize MCI hardware. */
188 at91_mci_hw_init();
189 /* Register the device. */
190 return atmel_mci_init((void *)ATMEL_BASE_MCI);
191 }
192
board_mmc_getcd(struct mmc * mmc)193 int board_mmc_getcd(struct mmc *mmc)
194 {
195 return !at91_get_pio_value(CONFIG_SYS_MMC_CD_PIN);
196 }
197 #endif
198