1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2003
3*4882a593Smuzhiyun * Thomas.Lange@corelatus.se
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <command.h>
10*4882a593Smuzhiyun #include <mach/au1x00.h>
11*4882a593Smuzhiyun #include <asm/mipsregs.h>
12*4882a593Smuzhiyun #include <asm/io.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
15*4882a593Smuzhiyun
dram_init(void)16*4882a593Smuzhiyun int dram_init(void)
17*4882a593Smuzhiyun {
18*4882a593Smuzhiyun /* Sdram is setup by assembler code */
19*4882a593Smuzhiyun /* If memory could be changed, we should return the true value here */
20*4882a593Smuzhiyun gd->ram_size = MEM_SIZE * 1024 * 1024;
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun return 0;
23*4882a593Smuzhiyun }
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define BCSR_PCMCIA_PC0DRVEN 0x0010
26*4882a593Smuzhiyun #define BCSR_PCMCIA_PC0RST 0x0080
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* In arch/mips/cpu/cpu.c */
29*4882a593Smuzhiyun void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
30*4882a593Smuzhiyun
checkboard(void)31*4882a593Smuzhiyun int checkboard (void)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun #ifdef CONFIG_IDE_PCMCIA
34*4882a593Smuzhiyun u16 status;
35*4882a593Smuzhiyun volatile u32 *pcmcia_bcsr = (u32*)(DB1XX0_BCSR_ADDR+0x10);
36*4882a593Smuzhiyun #endif /* CONFIG_IDE_PCMCIA */
37*4882a593Smuzhiyun volatile u32 *phy = (u32*)(DB1XX0_BCSR_ADDR+0xC);
38*4882a593Smuzhiyun volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
39*4882a593Smuzhiyun u32 proc_id;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun proc_id = read_c0_prid();
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun switch (proc_id >> 24) {
46*4882a593Smuzhiyun case 0:
47*4882a593Smuzhiyun puts ("Board: Merlot (DbAu1000)\n");
48*4882a593Smuzhiyun printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n",
49*4882a593Smuzhiyun (proc_id >> 8) & 0xFF, proc_id & 0xFF);
50*4882a593Smuzhiyun break;
51*4882a593Smuzhiyun case 1:
52*4882a593Smuzhiyun puts ("Board: DbAu1500\n");
53*4882a593Smuzhiyun printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x\n",
54*4882a593Smuzhiyun (proc_id >> 8) & 0xFF, proc_id & 0xFF);
55*4882a593Smuzhiyun break;
56*4882a593Smuzhiyun case 2:
57*4882a593Smuzhiyun puts ("Board: DbAu1100\n");
58*4882a593Smuzhiyun printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n",
59*4882a593Smuzhiyun (proc_id >> 8) & 0xFF, proc_id & 0xFF);
60*4882a593Smuzhiyun break;
61*4882a593Smuzhiyun case 3:
62*4882a593Smuzhiyun puts ("Board: DbAu1550\n");
63*4882a593Smuzhiyun printf ("CPU: Au1550, id: 0x%02x, rev: 0x%02x\n",
64*4882a593Smuzhiyun (proc_id >> 8) & 0xFF, proc_id & 0xFF);
65*4882a593Smuzhiyun break;
66*4882a593Smuzhiyun default:
67*4882a593Smuzhiyun printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun set_io_port_base(0);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun #ifdef CONFIG_IDE_PCMCIA
73*4882a593Smuzhiyun /* Enable 3.3 V on slot 0 ( VCC )
74*4882a593Smuzhiyun No 5V */
75*4882a593Smuzhiyun status = 4;
76*4882a593Smuzhiyun *pcmcia_bcsr = status;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun status |= BCSR_PCMCIA_PC0DRVEN;
79*4882a593Smuzhiyun *pcmcia_bcsr = status;
80*4882a593Smuzhiyun au_sync();
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun udelay(300*1000);
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun status |= BCSR_PCMCIA_PC0RST;
85*4882a593Smuzhiyun *pcmcia_bcsr = status;
86*4882a593Smuzhiyun au_sync();
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun udelay(100*1000);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun /* PCMCIA is on a 36 bit physical address.
91*4882a593Smuzhiyun We need to map it into a 32 bit addresses */
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun #if 0
94*4882a593Smuzhiyun /* We dont need theese unless we run whole pcmcia package */
95*4882a593Smuzhiyun write_one_tlb(20, /* index */
96*4882a593Smuzhiyun 0x01ffe000, /* Pagemask, 16 MB pages */
97*4882a593Smuzhiyun CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */
98*4882a593Smuzhiyun 0x3C000017, /* Lo0 */
99*4882a593Smuzhiyun 0x3C200017); /* Lo1 */
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun write_one_tlb(21, /* index */
102*4882a593Smuzhiyun 0x01ffe000, /* Pagemask, 16 MB pages */
103*4882a593Smuzhiyun CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */
104*4882a593Smuzhiyun 0x3D000017, /* Lo0 */
105*4882a593Smuzhiyun 0x3D200017); /* Lo1 */
106*4882a593Smuzhiyun #endif /* 0 */
107*4882a593Smuzhiyun write_one_tlb(22, /* index */
108*4882a593Smuzhiyun 0x01ffe000, /* Pagemask, 16 MB pages */
109*4882a593Smuzhiyun CONFIG_SYS_PCMCIA_MEM_ADDR, /* Hi */
110*4882a593Smuzhiyun 0x3E000017, /* Lo0 */
111*4882a593Smuzhiyun 0x3E200017); /* Lo1 */
112*4882a593Smuzhiyun #endif /* CONFIG_IDE_PCMCIA */
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /* Release reset of ethernet PHY chips */
115*4882a593Smuzhiyun /* Always do this, because linux does not know about it */
116*4882a593Smuzhiyun *phy = 3;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun return 0;
119*4882a593Smuzhiyun }
120