1 /*
2 * (C) Copyright 2003
3 * Thomas.Lange@corelatus.se
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9 #include <command.h>
10 #include <mach/au1x00.h>
11 #include <asm/mipsregs.h>
12 #include <asm/io.h>
13
14 DECLARE_GLOBAL_DATA_PTR;
15
dram_init(void)16 int dram_init(void)
17 {
18 /* Sdram is setup by assembler code */
19 /* If memory could be changed, we should return the true value here */
20 gd->ram_size = MEM_SIZE * 1024 * 1024;
21
22 return 0;
23 }
24
25 #define BCSR_PCMCIA_PC0DRVEN 0x0010
26 #define BCSR_PCMCIA_PC0RST 0x0080
27
28 /* In arch/mips/cpu/cpu.c */
29 void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
30
checkboard(void)31 int checkboard (void)
32 {
33 #ifdef CONFIG_IDE_PCMCIA
34 u16 status;
35 volatile u32 *pcmcia_bcsr = (u32*)(DB1XX0_BCSR_ADDR+0x10);
36 #endif /* CONFIG_IDE_PCMCIA */
37 volatile u32 *phy = (u32*)(DB1XX0_BCSR_ADDR+0xC);
38 volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
39 u32 proc_id;
40
41 *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
42
43 proc_id = read_c0_prid();
44
45 switch (proc_id >> 24) {
46 case 0:
47 puts ("Board: Merlot (DbAu1000)\n");
48 printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n",
49 (proc_id >> 8) & 0xFF, proc_id & 0xFF);
50 break;
51 case 1:
52 puts ("Board: DbAu1500\n");
53 printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x\n",
54 (proc_id >> 8) & 0xFF, proc_id & 0xFF);
55 break;
56 case 2:
57 puts ("Board: DbAu1100\n");
58 printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n",
59 (proc_id >> 8) & 0xFF, proc_id & 0xFF);
60 break;
61 case 3:
62 puts ("Board: DbAu1550\n");
63 printf ("CPU: Au1550, id: 0x%02x, rev: 0x%02x\n",
64 (proc_id >> 8) & 0xFF, proc_id & 0xFF);
65 break;
66 default:
67 printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
68 }
69
70 set_io_port_base(0);
71
72 #ifdef CONFIG_IDE_PCMCIA
73 /* Enable 3.3 V on slot 0 ( VCC )
74 No 5V */
75 status = 4;
76 *pcmcia_bcsr = status;
77
78 status |= BCSR_PCMCIA_PC0DRVEN;
79 *pcmcia_bcsr = status;
80 au_sync();
81
82 udelay(300*1000);
83
84 status |= BCSR_PCMCIA_PC0RST;
85 *pcmcia_bcsr = status;
86 au_sync();
87
88 udelay(100*1000);
89
90 /* PCMCIA is on a 36 bit physical address.
91 We need to map it into a 32 bit addresses */
92
93 #if 0
94 /* We dont need theese unless we run whole pcmcia package */
95 write_one_tlb(20, /* index */
96 0x01ffe000, /* Pagemask, 16 MB pages */
97 CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */
98 0x3C000017, /* Lo0 */
99 0x3C200017); /* Lo1 */
100
101 write_one_tlb(21, /* index */
102 0x01ffe000, /* Pagemask, 16 MB pages */
103 CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */
104 0x3D000017, /* Lo0 */
105 0x3D200017); /* Lo1 */
106 #endif /* 0 */
107 write_one_tlb(22, /* index */
108 0x01ffe000, /* Pagemask, 16 MB pages */
109 CONFIG_SYS_PCMCIA_MEM_ADDR, /* Hi */
110 0x3E000017, /* Lo0 */
111 0x3E200017); /* Lo1 */
112 #endif /* CONFIG_IDE_PCMCIA */
113
114 /* Release reset of ethernet PHY chips */
115 /* Always do this, because linux does not know about it */
116 *phy = 3;
117
118 return 0;
119 }
120