1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * SPL specific code for Compulab CM-T54 board
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <asm/emif.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun const struct emif_regs emif_regs_ddr3_532_mhz_cm_t54 = {
14*4882a593Smuzhiyun #if defined(CONFIG_DRAM_1G) || defined(CONFIG_DRAM_512M)
15*4882a593Smuzhiyun .sdram_config_init = 0x618522B2,
16*4882a593Smuzhiyun .sdram_config = 0x618522B2,
17*4882a593Smuzhiyun #elif defined(CONFIG_DRAM_2G)
18*4882a593Smuzhiyun .sdram_config_init = 0x618522BA,
19*4882a593Smuzhiyun .sdram_config = 0x618522BA,
20*4882a593Smuzhiyun #endif
21*4882a593Smuzhiyun .sdram_config2 = 0x0,
22*4882a593Smuzhiyun .ref_ctrl = 0x00001040,
23*4882a593Smuzhiyun .sdram_tim1 = 0xEEEF36F3,
24*4882a593Smuzhiyun .sdram_tim2 = 0x348F7FDA,
25*4882a593Smuzhiyun .sdram_tim3 = 0x027F88A8,
26*4882a593Smuzhiyun .read_idle_ctrl = 0x00050000,
27*4882a593Smuzhiyun .zq_config = 0x1007190B,
28*4882a593Smuzhiyun .temp_alert_config = 0x00000000,
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun .emif_ddr_phy_ctlr_1_init = 0x0030400B,
31*4882a593Smuzhiyun .emif_ddr_phy_ctlr_1 = 0x0034400B,
32*4882a593Smuzhiyun .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
33*4882a593Smuzhiyun .emif_ddr_ext_phy_ctrl_2 = 0x00000000,
34*4882a593Smuzhiyun .emif_ddr_ext_phy_ctrl_3 = 0x00000000,
35*4882a593Smuzhiyun .emif_ddr_ext_phy_ctrl_4 = 0x00000000,
36*4882a593Smuzhiyun .emif_ddr_ext_phy_ctrl_5 = 0x4350D435,
37*4882a593Smuzhiyun .emif_rd_wr_lvl_rmp_win = 0x00000000,
38*4882a593Smuzhiyun .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
39*4882a593Smuzhiyun .emif_rd_wr_lvl_ctl = 0x00000000,
40*4882a593Smuzhiyun .emif_rd_wr_exec_thresh = 0x40000305,
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun const struct dmm_lisa_map_regs lisa_map_cm_t54 = {
44*4882a593Smuzhiyun .dmm_lisa_map_0 = 0x0,
45*4882a593Smuzhiyun .dmm_lisa_map_1 = 0x0,
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #ifdef CONFIG_DRAM_2G
48*4882a593Smuzhiyun .dmm_lisa_map_2 = 0x80740300,
49*4882a593Smuzhiyun #elif defined(CONFIG_DRAM_1G)
50*4882a593Smuzhiyun .dmm_lisa_map_2 = 0x80640300,
51*4882a593Smuzhiyun #elif defined(CONFIG_DRAM_512M)
52*4882a593Smuzhiyun .dmm_lisa_map_2 = 0x80500100,
53*4882a593Smuzhiyun #endif
54*4882a593Smuzhiyun .dmm_lisa_map_3 = 0x00000000,
55*4882a593Smuzhiyun .is_ma_present = 0x1,
56*4882a593Smuzhiyun };
57*4882a593Smuzhiyun
emif_get_reg_dump(u32 emif_nr,const struct emif_regs ** regs)58*4882a593Smuzhiyun void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun *regs = &emif_regs_ddr3_532_mhz_cm_t54;
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
emif_get_dmm_regs(const struct dmm_lisa_map_regs ** dmm_lisa_regs)63*4882a593Smuzhiyun void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun *dmm_lisa_regs = &lisa_map_cm_t54;
66*4882a593Smuzhiyun }
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