1 /*
2 * SPL specific code for Compulab CM-T54 board
3 *
4 * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
5 *
6 * Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11 #include <asm/emif.h>
12
13 const struct emif_regs emif_regs_ddr3_532_mhz_cm_t54 = {
14 #if defined(CONFIG_DRAM_1G) || defined(CONFIG_DRAM_512M)
15 .sdram_config_init = 0x618522B2,
16 .sdram_config = 0x618522B2,
17 #elif defined(CONFIG_DRAM_2G)
18 .sdram_config_init = 0x618522BA,
19 .sdram_config = 0x618522BA,
20 #endif
21 .sdram_config2 = 0x0,
22 .ref_ctrl = 0x00001040,
23 .sdram_tim1 = 0xEEEF36F3,
24 .sdram_tim2 = 0x348F7FDA,
25 .sdram_tim3 = 0x027F88A8,
26 .read_idle_ctrl = 0x00050000,
27 .zq_config = 0x1007190B,
28 .temp_alert_config = 0x00000000,
29
30 .emif_ddr_phy_ctlr_1_init = 0x0030400B,
31 .emif_ddr_phy_ctlr_1 = 0x0034400B,
32 .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
33 .emif_ddr_ext_phy_ctrl_2 = 0x00000000,
34 .emif_ddr_ext_phy_ctrl_3 = 0x00000000,
35 .emif_ddr_ext_phy_ctrl_4 = 0x00000000,
36 .emif_ddr_ext_phy_ctrl_5 = 0x4350D435,
37 .emif_rd_wr_lvl_rmp_win = 0x00000000,
38 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
39 .emif_rd_wr_lvl_ctl = 0x00000000,
40 .emif_rd_wr_exec_thresh = 0x40000305,
41 };
42
43 const struct dmm_lisa_map_regs lisa_map_cm_t54 = {
44 .dmm_lisa_map_0 = 0x0,
45 .dmm_lisa_map_1 = 0x0,
46
47 #ifdef CONFIG_DRAM_2G
48 .dmm_lisa_map_2 = 0x80740300,
49 #elif defined(CONFIG_DRAM_1G)
50 .dmm_lisa_map_2 = 0x80640300,
51 #elif defined(CONFIG_DRAM_512M)
52 .dmm_lisa_map_2 = 0x80500100,
53 #endif
54 .dmm_lisa_map_3 = 0x00000000,
55 .is_ma_present = 0x1,
56 };
57
emif_get_reg_dump(u32 emif_nr,const struct emif_regs ** regs)58 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
59 {
60 *regs = &emif_regs_ddr3_532_mhz_cm_t54;
61 }
62
emif_get_dmm_regs(const struct dmm_lisa_map_regs ** dmm_lisa_regs)63 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
64 {
65 *dmm_lisa_regs = &lisa_map_cm_t54;
66 }
67