1 /*
2 * URB OHCI HCD (Host Controller Driver) for USB on the AU1x00.
3 *
4 * (C) Copyright 2003
5 * Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 * Note: Part of this code has been derived from linux
9 *
10 */
11 /*
12 * IMPORTANT NOTES
13 * 1 - this driver is intended for use with USB Mass Storage Devices
14 * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
15 */
16
17 #include <config.h>
18
19 #ifdef CONFIG_USB_OHCI
20
21 /* #include <pci.h> no PCI on the AU1x00 */
22
23 #include <common.h>
24 #include <malloc.h>
25 #include <asm/io.h>
26 #include <mach/au1x00.h>
27 #include <usb.h>
28 #include "au1x00_usb_ohci.h"
29
30 #define OHCI_USE_NPS /* force NoPowerSwitching mode */
31 #define OHCI_VERBOSE_DEBUG /* not always helpful */
32 #define OHCI_FILL_TRACE
33
34 #define USBH_ENABLE_BE (1<<0)
35 #define USBH_ENABLE_C (1<<1)
36 #define USBH_ENABLE_E (1<<2)
37 #define USBH_ENABLE_CE (1<<3)
38 #define USBH_ENABLE_RD (1<<4)
39
40 #ifdef __LITTLE_ENDIAN
41 #define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C)
42 #else
43 #define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C | USBH_ENABLE_BE)
44 #endif
45
46
47 /* For initializing controller (mask in an HCFS mode too) */
48 #define OHCI_CONTROL_INIT \
49 (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
50
51 #undef readl
52 #undef writel
53
54 #define readl(a) au_readl((long)(a))
55 #define writel(v,a) au_writel((v),(int)(a))
56
57 #define DEBUG
58 #ifdef DEBUG
59 #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
60 #else
61 #define dbg(format, arg...) do {} while(0)
62 #endif /* DEBUG */
63 #define err(format, arg...) printf("ERROR: " format "\n", ## arg)
64 #define SHOW_INFO
65 #ifdef SHOW_INFO
66 #define info(format, arg...) printf("INFO: " format "\n", ## arg)
67 #else
68 #define info(format, arg...) do {} while(0)
69 #endif
70
71 #define m16_swap(x) swap_16(x)
72 #define m32_swap(x) swap_32(x)
73
74 /* global ohci_t */
75 static ohci_t gohci;
76 /* this must be aligned to a 256 byte boundary */
77 struct ohci_hcca ghcca[1];
78 /* a pointer to the aligned storage */
79 struct ohci_hcca *phcca;
80 /* this allocates EDs for all possible endpoints */
81 struct ohci_device ohci_dev;
82 /* urb_priv */
83 urb_priv_t urb_priv;
84 /* RHSC flag */
85 int got_rhsc;
86 /* device which was disconnected */
87 struct usb_device *devgone;
88
89 /*-------------------------------------------------------------------------*/
90
91 /* AMD-756 (D2 rev) reports corrupt register contents in some cases.
92 * The erratum (#4) description is incorrect. AMD's workaround waits
93 * till some bits (mostly reserved) are clear; ok for all revs.
94 */
95 #define OHCI_QUIRK_AMD756 0xabcd
96 #define read_roothub(hc, register, mask) ({ \
97 u32 temp = readl (&hc->regs->roothub.register); \
98 if (hc->flags & OHCI_QUIRK_AMD756) \
99 while (temp & mask) \
100 temp = readl (&hc->regs->roothub.register); \
101 temp; })
102
roothub_a(struct ohci * hc)103 static u32 roothub_a (struct ohci *hc)
104 { return read_roothub (hc, a, 0xfc0fe000); }
roothub_b(struct ohci * hc)105 static inline u32 roothub_b (struct ohci *hc)
106 { return readl (&hc->regs->roothub.b); }
roothub_status(struct ohci * hc)107 static inline u32 roothub_status (struct ohci *hc)
108 { return readl (&hc->regs->roothub.status); }
roothub_portstatus(struct ohci * hc,int i)109 static u32 roothub_portstatus (struct ohci *hc, int i)
110 { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
111
112
113 /* forward declaration */
114 static int hc_interrupt (void);
115 static void
116 td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
117 int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
118
119 /*-------------------------------------------------------------------------*
120 * URB support functions
121 *-------------------------------------------------------------------------*/
122
123 /* free HCD-private data associated with this URB */
124
urb_free_priv(urb_priv_t * urb)125 static void urb_free_priv (urb_priv_t * urb)
126 {
127 int i;
128 int last;
129 struct td * td;
130
131 last = urb->length - 1;
132 if (last >= 0) {
133 for (i = 0; i <= last; i++) {
134 td = urb->td[i];
135 if (td) {
136 td->usb_dev = NULL;
137 urb->td[i] = NULL;
138 }
139 }
140 }
141 }
142
143 /*-------------------------------------------------------------------------*/
144
145 #ifdef DEBUG
146 static int sohci_get_current_frame_number (struct usb_device * dev);
147
148 /* debug| print the main components of an URB
149 * small: 0) header + data packets 1) just header */
150
pkt_print(struct usb_device * dev,unsigned long pipe,void * buffer,int transfer_len,struct devrequest * setup,char * str,int small)151 static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
152 int transfer_len, struct devrequest * setup, char * str, int small)
153 {
154 urb_priv_t * purb = &urb_priv;
155
156 dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
157 str,
158 sohci_get_current_frame_number (dev),
159 usb_pipedevice (pipe),
160 usb_pipeendpoint (pipe),
161 usb_pipeout (pipe)? 'O': 'I',
162 usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
163 (usb_pipecontrol (pipe)? "CTRL": "BULK"),
164 purb->actual_length,
165 transfer_len, dev->status);
166 #ifdef OHCI_VERBOSE_DEBUG
167 if (!small) {
168 int i, len;
169
170 if (usb_pipecontrol (pipe)) {
171 printf (__FILE__ ": cmd(8):");
172 for (i = 0; i < 8 ; i++)
173 printf (" %02x", ((__u8 *) setup) [i]);
174 printf ("\n");
175 }
176 if (transfer_len > 0 && buffer) {
177 printf (__FILE__ ": data(%d/%d):",
178 purb->actual_length,
179 transfer_len);
180 len = usb_pipeout (pipe)?
181 transfer_len: purb->actual_length;
182 for (i = 0; i < 16 && i < len; i++)
183 printf (" %02x", ((__u8 *) buffer) [i]);
184 printf ("%s\n", i < len? "...": "");
185 }
186 }
187 #endif
188 }
189
190 /* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
ep_print_int_eds(ohci_t * ohci,char * str)191 void ep_print_int_eds (ohci_t *ohci, char * str) {
192 int i, j;
193 __u32 * ed_p;
194 for (i= 0; i < 32; i++) {
195 j = 5;
196 ed_p = &(ohci->hcca->int_table [i]);
197 if (*ed_p == 0)
198 continue;
199 printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
200 while (*ed_p != 0 && j--) {
201 ed_t *ed = (ed_t *)m32_swap(ed_p);
202 printf (" ed: %4x;", ed->hwINFO);
203 ed_p = &ed->hwNextED;
204 }
205 printf ("\n");
206 }
207 }
208
ohci_dump_intr_mask(char * label,__u32 mask)209 static void ohci_dump_intr_mask (char *label, __u32 mask)
210 {
211 dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
212 label,
213 mask,
214 (mask & OHCI_INTR_MIE) ? " MIE" : "",
215 (mask & OHCI_INTR_OC) ? " OC" : "",
216 (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
217 (mask & OHCI_INTR_FNO) ? " FNO" : "",
218 (mask & OHCI_INTR_UE) ? " UE" : "",
219 (mask & OHCI_INTR_RD) ? " RD" : "",
220 (mask & OHCI_INTR_SF) ? " SF" : "",
221 (mask & OHCI_INTR_WDH) ? " WDH" : "",
222 (mask & OHCI_INTR_SO) ? " SO" : ""
223 );
224 }
225
maybe_print_eds(char * label,__u32 value)226 static void maybe_print_eds (char *label, __u32 value)
227 {
228 ed_t *edp = (ed_t *)value;
229
230 if (value) {
231 dbg ("%s %08x", label, value);
232 dbg ("%08x", edp->hwINFO);
233 dbg ("%08x", edp->hwTailP);
234 dbg ("%08x", edp->hwHeadP);
235 dbg ("%08x", edp->hwNextED);
236 }
237 }
238
hcfs2string(int state)239 static char * hcfs2string (int state)
240 {
241 switch (state) {
242 case OHCI_USB_RESET: return "reset";
243 case OHCI_USB_RESUME: return "resume";
244 case OHCI_USB_OPER: return "operational";
245 case OHCI_USB_SUSPEND: return "suspend";
246 }
247 return "?";
248 }
249
250 /* dump control and status registers */
ohci_dump_status(ohci_t * controller)251 static void ohci_dump_status (ohci_t *controller)
252 {
253 struct ohci_regs *regs = controller->regs;
254 __u32 temp;
255
256 temp = readl (®s->revision) & 0xff;
257 if (temp != 0x10)
258 dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
259
260 temp = readl (®s->control);
261 dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
262 (temp & OHCI_CTRL_RWE) ? " RWE" : "",
263 (temp & OHCI_CTRL_RWC) ? " RWC" : "",
264 (temp & OHCI_CTRL_IR) ? " IR" : "",
265 hcfs2string (temp & OHCI_CTRL_HCFS),
266 (temp & OHCI_CTRL_BLE) ? " BLE" : "",
267 (temp & OHCI_CTRL_CLE) ? " CLE" : "",
268 (temp & OHCI_CTRL_IE) ? " IE" : "",
269 (temp & OHCI_CTRL_PLE) ? " PLE" : "",
270 temp & OHCI_CTRL_CBSR
271 );
272
273 temp = readl (®s->cmdstatus);
274 dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
275 (temp & OHCI_SOC) >> 16,
276 (temp & OHCI_OCR) ? " OCR" : "",
277 (temp & OHCI_BLF) ? " BLF" : "",
278 (temp & OHCI_CLF) ? " CLF" : "",
279 (temp & OHCI_HCR) ? " HCR" : ""
280 );
281
282 ohci_dump_intr_mask ("intrstatus", readl (®s->intrstatus));
283 ohci_dump_intr_mask ("intrenable", readl (®s->intrenable));
284
285 maybe_print_eds ("ed_periodcurrent", readl (®s->ed_periodcurrent));
286
287 maybe_print_eds ("ed_controlhead", readl (®s->ed_controlhead));
288 maybe_print_eds ("ed_controlcurrent", readl (®s->ed_controlcurrent));
289
290 maybe_print_eds ("ed_bulkhead", readl (®s->ed_bulkhead));
291 maybe_print_eds ("ed_bulkcurrent", readl (®s->ed_bulkcurrent));
292
293 maybe_print_eds ("donehead", readl (®s->donehead));
294 }
295
ohci_dump_roothub(ohci_t * controller,int verbose)296 static void ohci_dump_roothub (ohci_t *controller, int verbose)
297 {
298 __u32 temp, ndp, i;
299
300 temp = roothub_a (controller);
301 ndp = (temp & RH_A_NDP);
302
303 if (verbose) {
304 dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
305 ((temp & RH_A_POTPGT) >> 24) & 0xff,
306 (temp & RH_A_NOCP) ? " NOCP" : "",
307 (temp & RH_A_OCPM) ? " OCPM" : "",
308 (temp & RH_A_DT) ? " DT" : "",
309 (temp & RH_A_NPS) ? " NPS" : "",
310 (temp & RH_A_PSM) ? " PSM" : "",
311 ndp
312 );
313 temp = roothub_b (controller);
314 dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
315 temp,
316 (temp & RH_B_PPCM) >> 16,
317 (temp & RH_B_DR)
318 );
319 temp = roothub_status (controller);
320 dbg ("roothub.status: %08x%s%s%s%s%s%s",
321 temp,
322 (temp & RH_HS_CRWE) ? " CRWE" : "",
323 (temp & RH_HS_OCIC) ? " OCIC" : "",
324 (temp & RH_HS_LPSC) ? " LPSC" : "",
325 (temp & RH_HS_DRWE) ? " DRWE" : "",
326 (temp & RH_HS_OCI) ? " OCI" : "",
327 (temp & RH_HS_LPS) ? " LPS" : ""
328 );
329 }
330
331 for (i = 0; i < ndp; i++) {
332 temp = roothub_portstatus (controller, i);
333 dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
334 i,
335 temp,
336 (temp & RH_PS_PRSC) ? " PRSC" : "",
337 (temp & RH_PS_OCIC) ? " OCIC" : "",
338 (temp & RH_PS_PSSC) ? " PSSC" : "",
339 (temp & RH_PS_PESC) ? " PESC" : "",
340 (temp & RH_PS_CSC) ? " CSC" : "",
341
342 (temp & RH_PS_LSDA) ? " LSDA" : "",
343 (temp & RH_PS_PPS) ? " PPS" : "",
344 (temp & RH_PS_PRS) ? " PRS" : "",
345 (temp & RH_PS_POCI) ? " POCI" : "",
346 (temp & RH_PS_PSS) ? " PSS" : "",
347
348 (temp & RH_PS_PES) ? " PES" : "",
349 (temp & RH_PS_CCS) ? " CCS" : ""
350 );
351 }
352 }
353
ohci_dump(ohci_t * controller,int verbose)354 static void ohci_dump (ohci_t *controller, int verbose)
355 {
356 dbg ("OHCI controller usb-%s state", controller->slot_name);
357
358 /* dumps some of the state we know about */
359 ohci_dump_status (controller);
360 if (verbose)
361 ep_print_int_eds (controller, "hcca");
362 dbg ("hcca frame #%04x", controller->hcca->frame_no);
363 ohci_dump_roothub (controller, 1);
364 }
365
366
367 #endif /* DEBUG */
368
369 /*-------------------------------------------------------------------------*
370 * Interface functions (URB)
371 *-------------------------------------------------------------------------*/
372
373 /* get a transfer request */
374
sohci_submit_job(struct usb_device * dev,unsigned long pipe,void * buffer,int transfer_len,struct devrequest * setup,int interval)375 int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
376 int transfer_len, struct devrequest *setup, int interval)
377 {
378 ohci_t *ohci;
379 ed_t * ed;
380 urb_priv_t *purb_priv;
381 int i, size = 0;
382
383 ohci = &gohci;
384
385 /* when controller's hung, permit only roothub cleanup attempts
386 * such as powering down ports */
387 if (ohci->disabled) {
388 err("sohci_submit_job: EPIPE");
389 return -1;
390 }
391
392 /* every endpoint has a ed, locate and fill it */
393 if (!(ed = ep_add_ed (dev, pipe))) {
394 err("sohci_submit_job: ENOMEM");
395 return -1;
396 }
397
398 /* for the private part of the URB we need the number of TDs (size) */
399 switch (usb_pipetype (pipe)) {
400 case PIPE_BULK: /* one TD for every 4096 Byte */
401 size = (transfer_len - 1) / 4096 + 1;
402 break;
403 case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
404 size = (transfer_len == 0)? 2:
405 (transfer_len - 1) / 4096 + 3;
406 break;
407 }
408
409 if (size >= (N_URB_TD - 1)) {
410 err("need %d TDs, only have %d", size, N_URB_TD);
411 return -1;
412 }
413 purb_priv = &urb_priv;
414 purb_priv->pipe = pipe;
415
416 /* fill the private part of the URB */
417 purb_priv->length = size;
418 purb_priv->ed = ed;
419 purb_priv->actual_length = 0;
420
421 /* allocate the TDs */
422 /* note that td[0] was allocated in ep_add_ed */
423 for (i = 0; i < size; i++) {
424 purb_priv->td[i] = td_alloc (dev);
425 if (!purb_priv->td[i]) {
426 purb_priv->length = i;
427 urb_free_priv (purb_priv);
428 err("sohci_submit_job: ENOMEM");
429 return -1;
430 }
431 }
432
433 if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
434 urb_free_priv (purb_priv);
435 err("sohci_submit_job: EINVAL");
436 return -1;
437 }
438
439 /* link the ed into a chain if is not already */
440 if (ed->state != ED_OPER)
441 ep_link (ohci, ed);
442
443 /* fill the TDs and link it to the ed */
444 td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
445
446 return 0;
447 }
448
449 /*-------------------------------------------------------------------------*/
450
451 #ifdef DEBUG
452 /* tell us the current USB frame number */
453
sohci_get_current_frame_number(struct usb_device * usb_dev)454 static int sohci_get_current_frame_number (struct usb_device *usb_dev)
455 {
456 ohci_t *ohci = &gohci;
457
458 return m16_swap (ohci->hcca->frame_no);
459 }
460 #endif
461
462 /*-------------------------------------------------------------------------*
463 * ED handling functions
464 *-------------------------------------------------------------------------*/
465
466 /* link an ed into one of the HC chains */
467
ep_link(ohci_t * ohci,ed_t * edi)468 static int ep_link (ohci_t *ohci, ed_t *edi)
469 {
470 volatile ed_t *ed = edi;
471
472 ed->state = ED_OPER;
473
474 switch (ed->type) {
475 case PIPE_CONTROL:
476 ed->hwNextED = 0;
477 if (ohci->ed_controltail == NULL) {
478 writel ((long)ed, &ohci->regs->ed_controlhead);
479 } else {
480 ohci->ed_controltail->hwNextED = m32_swap (ed);
481 }
482 ed->ed_prev = ohci->ed_controltail;
483 if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
484 !ohci->ed_rm_list[1] && !ohci->sleeping) {
485 ohci->hc_control |= OHCI_CTRL_CLE;
486 writel (ohci->hc_control, &ohci->regs->control);
487 }
488 ohci->ed_controltail = edi;
489 break;
490
491 case PIPE_BULK:
492 ed->hwNextED = 0;
493 if (ohci->ed_bulktail == NULL) {
494 writel ((long)ed, &ohci->regs->ed_bulkhead);
495 } else {
496 ohci->ed_bulktail->hwNextED = m32_swap (ed);
497 }
498 ed->ed_prev = ohci->ed_bulktail;
499 if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
500 !ohci->ed_rm_list[1] && !ohci->sleeping) {
501 ohci->hc_control |= OHCI_CTRL_BLE;
502 writel (ohci->hc_control, &ohci->regs->control);
503 }
504 ohci->ed_bulktail = edi;
505 break;
506 }
507 return 0;
508 }
509
510 /*-------------------------------------------------------------------------*/
511
512 /* unlink an ed from one of the HC chains.
513 * just the link to the ed is unlinked.
514 * the link from the ed still points to another operational ed or 0
515 * so the HC can eventually finish the processing of the unlinked ed */
516
ep_unlink(ohci_t * ohci,ed_t * ed)517 static int ep_unlink (ohci_t *ohci, ed_t *ed)
518 {
519 ed->hwINFO |= m32_swap (OHCI_ED_SKIP);
520
521 switch (ed->type) {
522 case PIPE_CONTROL:
523 if (ed->ed_prev == NULL) {
524 if (!ed->hwNextED) {
525 ohci->hc_control &= ~OHCI_CTRL_CLE;
526 writel (ohci->hc_control, &ohci->regs->control);
527 }
528 writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
529 } else {
530 ed->ed_prev->hwNextED = ed->hwNextED;
531 }
532 if (ohci->ed_controltail == ed) {
533 ohci->ed_controltail = ed->ed_prev;
534 } else {
535 ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
536 }
537 break;
538
539 case PIPE_BULK:
540 if (ed->ed_prev == NULL) {
541 if (!ed->hwNextED) {
542 ohci->hc_control &= ~OHCI_CTRL_BLE;
543 writel (ohci->hc_control, &ohci->regs->control);
544 }
545 writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
546 } else {
547 ed->ed_prev->hwNextED = ed->hwNextED;
548 }
549 if (ohci->ed_bulktail == ed) {
550 ohci->ed_bulktail = ed->ed_prev;
551 } else {
552 ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
553 }
554 break;
555 }
556 ed->state = ED_UNLINK;
557 return 0;
558 }
559
560
561 /*-------------------------------------------------------------------------*/
562
563 /* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
564 * but the USB stack is a little bit stateless so we do it at every transaction
565 * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
566 * in all other cases the state is left unchanged
567 * the ed info fields are setted anyway even though most of them should not change */
568
ep_add_ed(struct usb_device * usb_dev,unsigned long pipe)569 static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
570 {
571 td_t *td;
572 ed_t *ed_ret;
573 volatile ed_t *ed;
574
575 ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
576 (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
577
578 if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
579 err("ep_add_ed: pending delete");
580 /* pending delete request */
581 return NULL;
582 }
583
584 if (ed->state == ED_NEW) {
585 ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
586 /* dummy td; end of td list for ed */
587 td = td_alloc (usb_dev);
588 ed->hwTailP = m32_swap (td);
589 ed->hwHeadP = ed->hwTailP;
590 ed->state = ED_UNLINK;
591 ed->type = usb_pipetype (pipe);
592 ohci_dev.ed_cnt++;
593 }
594
595 ed->hwINFO = m32_swap (usb_pipedevice (pipe)
596 | usb_pipeendpoint (pipe) << 7
597 | (usb_pipeisoc (pipe)? 0x8000: 0)
598 | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
599 | (usb_dev->speed == USB_SPEED_LOW) << 13
600 | usb_maxpacket (usb_dev, pipe) << 16);
601
602 return ed_ret;
603 }
604
605 /*-------------------------------------------------------------------------*
606 * TD handling functions
607 *-------------------------------------------------------------------------*/
608
609 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
610
td_fill(ohci_t * ohci,unsigned int info,void * data,int len,struct usb_device * dev,int index,urb_priv_t * urb_priv)611 static void td_fill (ohci_t *ohci, unsigned int info,
612 void *data, int len,
613 struct usb_device *dev, int index, urb_priv_t *urb_priv)
614 {
615 volatile td_t *td, *td_pt;
616 #ifdef OHCI_FILL_TRACE
617 int i;
618 #endif
619
620 if (index > urb_priv->length) {
621 err("index > length");
622 return;
623 }
624 /* use this td as the next dummy */
625 td_pt = urb_priv->td [index];
626 td_pt->hwNextTD = 0;
627
628 /* fill the old dummy TD */
629 td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);
630
631 td->ed = urb_priv->ed;
632 td->next_dl_td = NULL;
633 td->index = index;
634 td->data = (__u32)data;
635 #ifdef OHCI_FILL_TRACE
636 if (1 || (usb_pipebulk(urb_priv->pipe) &&
637 usb_pipeout(urb_priv->pipe))) {
638 for (i = 0; i < len; i++)
639 printf("td->data[%d] %#2x\n",i, ((unsigned char *)(td->data+0x80000000))[i]);
640 }
641 #endif
642 if (!len)
643 data = 0;
644
645 td->hwINFO = m32_swap (info);
646 td->hwCBP = m32_swap (data);
647 if (data)
648 td->hwBE = m32_swap (data + len - 1);
649 else
650 td->hwBE = 0;
651 td->hwNextTD = m32_swap (td_pt);
652 td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000);
653
654 /* append to queue */
655 td->ed->hwTailP = td->hwNextTD;
656 }
657
658 /*-------------------------------------------------------------------------*/
659
660 /* prepare all TDs of a transfer */
661
662 #define kseg_to_phys(x) ((void *)((__u32)(x) - 0x80000000))
663
td_submit_job(struct usb_device * dev,unsigned long pipe,void * buffer,int transfer_len,struct devrequest * setup,urb_priv_t * urb,int interval)664 static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
665 int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
666 {
667 ohci_t *ohci = &gohci;
668 int data_len = transfer_len;
669 void *data;
670 int cnt = 0;
671 __u32 info = 0;
672 unsigned int toggle = 0;
673
674 /* OHCI handles the DATA-toggles itself, we just use the
675 USB-toggle bits for resetting */
676 if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
677 toggle = TD_T_TOGGLE;
678 } else {
679 toggle = TD_T_DATA0;
680 usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
681 }
682 urb->td_cnt = 0;
683 if (data_len)
684 data = kseg_to_phys(buffer);
685 else
686 data = 0;
687
688 switch (usb_pipetype (pipe)) {
689 case PIPE_BULK:
690 info = usb_pipeout (pipe)?
691 TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
692 while(data_len > 4096) {
693 td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
694 data += 4096; data_len -= 4096; cnt++;
695 }
696 info = usb_pipeout (pipe)?
697 TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
698 td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
699 cnt++;
700
701 if (!ohci->sleeping)
702 writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
703 break;
704
705 case PIPE_CONTROL:
706 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
707 td_fill (ohci, info, kseg_to_phys(setup), 8, dev, cnt++, urb);
708 if (data_len > 0) {
709 info = usb_pipeout (pipe)?
710 TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
711 /* NOTE: mishandles transfers >8K, some >4K */
712 td_fill (ohci, info, data, data_len, dev, cnt++, urb);
713 }
714 info = usb_pipeout (pipe)?
715 TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
716 td_fill (ohci, info, data, 0, dev, cnt++, urb);
717 if (!ohci->sleeping)
718 writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
719 break;
720 }
721 if (urb->length != cnt)
722 dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
723 }
724
725 /*-------------------------------------------------------------------------*
726 * Done List handling functions
727 *-------------------------------------------------------------------------*/
728
729
730 /* calculate the transfer length and update the urb */
731
dl_transfer_length(td_t * td)732 static void dl_transfer_length(td_t * td)
733 {
734 __u32 tdINFO, tdBE, tdCBP;
735 urb_priv_t *lurb_priv = &urb_priv;
736
737 tdINFO = m32_swap (td->hwINFO);
738 tdBE = m32_swap (td->hwBE);
739 tdCBP = m32_swap (td->hwCBP);
740
741
742 if (!(usb_pipecontrol(lurb_priv->pipe) &&
743 ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
744 if (tdBE != 0) {
745 if (td->hwCBP == 0)
746 lurb_priv->actual_length += tdBE - td->data + 1;
747 else
748 lurb_priv->actual_length += tdCBP - td->data;
749 }
750 }
751 }
752
753 /*-------------------------------------------------------------------------*/
754
755 /* replies to the request have to be on a FIFO basis so
756 * we reverse the reversed done-list */
757
dl_reverse_done_list(ohci_t * ohci)758 static td_t * dl_reverse_done_list (ohci_t *ohci)
759 {
760 __u32 td_list_hc;
761 td_t *td_rev = NULL;
762 td_t *td_list = NULL;
763 urb_priv_t *lurb_priv = NULL;
764
765 td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
766 ohci->hcca->done_head = 0;
767
768 while (td_list_hc) {
769 td_list = (td_t *)td_list_hc;
770
771 if (TD_CC_GET (m32_swap (td_list->hwINFO))) {
772 lurb_priv = &urb_priv;
773 dbg(" USB-error/status: %x : %p",
774 TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);
775 if (td_list->ed->hwHeadP & m32_swap (0x1)) {
776 if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
777 td_list->ed->hwHeadP =
778 (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) |
779 (td_list->ed->hwHeadP & m32_swap (0x2));
780 lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
781 } else
782 td_list->ed->hwHeadP &= m32_swap (0xfffffff2);
783 }
784 }
785
786 td_list->next_dl_td = td_rev;
787 td_rev = td_list;
788 td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;
789 }
790 return td_list;
791 }
792
793 /*-------------------------------------------------------------------------*/
794
795 /* td done list */
dl_done_list(ohci_t * ohci,td_t * td_list)796 static int dl_done_list (ohci_t *ohci, td_t *td_list)
797 {
798 td_t *td_list_next = NULL;
799 ed_t *ed;
800 int cc = 0;
801 int stat = 0;
802 /* urb_t *urb; */
803 urb_priv_t *lurb_priv;
804 __u32 tdINFO, edHeadP, edTailP;
805
806 while (td_list) {
807 td_list_next = td_list->next_dl_td;
808
809 lurb_priv = &urb_priv;
810 tdINFO = m32_swap (td_list->hwINFO);
811
812 ed = td_list->ed;
813
814 dl_transfer_length(td_list);
815
816 /* error code of transfer */
817 cc = TD_CC_GET (tdINFO);
818 if (cc != 0) {
819 dbg("ConditionCode %#x", cc);
820 stat = cc_to_error[cc];
821 }
822
823 if (ed->state != ED_NEW) {
824 edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
825 edTailP = m32_swap (ed->hwTailP);
826
827 /* unlink eds if they are not busy */
828 if ((edHeadP == edTailP) && (ed->state == ED_OPER))
829 ep_unlink (ohci, ed);
830 }
831
832 td_list = td_list_next;
833 }
834 return stat;
835 }
836
837 /*-------------------------------------------------------------------------*
838 * Virtual Root Hub
839 *-------------------------------------------------------------------------*/
840
841 #include <usbroothubdes.h>
842
843 /* Hub class-specific descriptor is constructed dynamically */
844
845
846 /*-------------------------------------------------------------------------*/
847
848 #define OK(x) len = (x); break
849 #ifdef DEBUG
850 #define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
851 #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
852 #else
853 #define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
854 #define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
855 #endif
856 #define RD_RH_STAT roothub_status(&gohci)
857 #define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
858
859 /* request to virtual root hub */
860
rh_check_port_status(ohci_t * controller)861 int rh_check_port_status(ohci_t *controller)
862 {
863 __u32 temp, ndp, i;
864 int res;
865
866 res = -1;
867 temp = roothub_a (controller);
868 ndp = (temp & RH_A_NDP);
869 for (i = 0; i < ndp; i++) {
870 temp = roothub_portstatus (controller, i);
871 /* check for a device disconnect */
872 if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
873 (RH_PS_PESC | RH_PS_CSC)) &&
874 ((temp & RH_PS_CCS) == 0)) {
875 res = i;
876 break;
877 }
878 }
879 return res;
880 }
881
ohci_submit_rh_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int transfer_len,struct devrequest * cmd)882 static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
883 void *buffer, int transfer_len, struct devrequest *cmd)
884 {
885 void * data = buffer;
886 int leni = transfer_len;
887 int len = 0;
888 int stat = 0;
889 __u32 datab[4];
890 __u8 *data_buf = (__u8 *)datab;
891 __u16 bmRType_bReq;
892 __u16 wValue;
893 __u16 wIndex;
894 __u16 wLength;
895
896 #ifdef DEBUG
897 urb_priv.actual_length = 0;
898 pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
899 #else
900 mdelay(1);
901 #endif
902 if (usb_pipeint(pipe)) {
903 info("Root-Hub submit IRQ: NOT implemented");
904 return 0;
905 }
906
907 bmRType_bReq = cmd->requesttype | (cmd->request << 8);
908 wValue = m16_swap (cmd->value);
909 wIndex = m16_swap (cmd->index);
910 wLength = m16_swap (cmd->length);
911
912 info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
913 dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
914
915 switch (bmRType_bReq) {
916 /* Request Destination:
917 without flags: Device,
918 RH_INTERFACE: interface,
919 RH_ENDPOINT: endpoint,
920 RH_CLASS means HUB here,
921 RH_OTHER | RH_CLASS almost ever means HUB_PORT here
922 */
923
924 case RH_GET_STATUS:
925 *(__u16 *) data_buf = m16_swap (1); OK (2);
926 case RH_GET_STATUS | RH_INTERFACE:
927 *(__u16 *) data_buf = m16_swap (0); OK (2);
928 case RH_GET_STATUS | RH_ENDPOINT:
929 *(__u16 *) data_buf = m16_swap (0); OK (2);
930 case RH_GET_STATUS | RH_CLASS:
931 *(__u32 *) data_buf = m32_swap (
932 RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
933 OK (4);
934 case RH_GET_STATUS | RH_OTHER | RH_CLASS:
935 *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
936
937 case RH_CLEAR_FEATURE | RH_ENDPOINT:
938 switch (wValue) {
939 case (RH_ENDPOINT_STALL): OK (0);
940 }
941 break;
942
943 case RH_CLEAR_FEATURE | RH_CLASS:
944 switch (wValue) {
945 case RH_C_HUB_LOCAL_POWER:
946 OK(0);
947 case (RH_C_HUB_OVER_CURRENT):
948 WR_RH_STAT(RH_HS_OCIC); OK (0);
949 }
950 break;
951
952 case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
953 switch (wValue) {
954 case (RH_PORT_ENABLE):
955 WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
956 case (RH_PORT_SUSPEND):
957 WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
958 case (RH_PORT_POWER):
959 WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
960 case (RH_C_PORT_CONNECTION):
961 WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
962 case (RH_C_PORT_ENABLE):
963 WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
964 case (RH_C_PORT_SUSPEND):
965 WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
966 case (RH_C_PORT_OVER_CURRENT):
967 WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
968 case (RH_C_PORT_RESET):
969 WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
970 }
971 break;
972
973 case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
974 switch (wValue) {
975 case (RH_PORT_SUSPEND):
976 WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
977 case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
978 if (RD_RH_PORTSTAT & RH_PS_CCS)
979 WR_RH_PORTSTAT (RH_PS_PRS);
980 OK (0);
981 case (RH_PORT_POWER):
982 WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
983 case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
984 if (RD_RH_PORTSTAT & RH_PS_CCS)
985 WR_RH_PORTSTAT (RH_PS_PES );
986 OK (0);
987 }
988 break;
989
990 case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
991
992 case RH_GET_DESCRIPTOR:
993 switch ((wValue & 0xff00) >> 8) {
994 case (0x01): /* device descriptor */
995 len = min_t(unsigned int,
996 leni,
997 min_t(unsigned int,
998 sizeof (root_hub_dev_des),
999 wLength));
1000 data_buf = root_hub_dev_des; OK(len);
1001 case (0x02): /* configuration descriptor */
1002 len = min_t(unsigned int,
1003 leni,
1004 min_t(unsigned int,
1005 sizeof (root_hub_config_des),
1006 wLength));
1007 data_buf = root_hub_config_des; OK(len);
1008 case (0x03): /* string descriptors */
1009 if(wValue==0x0300) {
1010 len = min_t(unsigned int,
1011 leni,
1012 min_t(unsigned int,
1013 sizeof (root_hub_str_index0),
1014 wLength));
1015 data_buf = root_hub_str_index0;
1016 OK(len);
1017 }
1018 if(wValue==0x0301) {
1019 len = min_t(unsigned int,
1020 leni,
1021 min_t(unsigned int,
1022 sizeof (root_hub_str_index1),
1023 wLength));
1024 data_buf = root_hub_str_index1;
1025 OK(len);
1026 }
1027 default:
1028 stat = USB_ST_STALLED;
1029 }
1030 break;
1031
1032 case RH_GET_DESCRIPTOR | RH_CLASS:
1033 {
1034 __u32 temp = roothub_a (&gohci);
1035
1036 data_buf [0] = 9; /* min length; */
1037 data_buf [1] = 0x29;
1038 data_buf [2] = temp & RH_A_NDP;
1039 data_buf [3] = 0;
1040 if (temp & RH_A_PSM) /* per-port power switching? */
1041 data_buf [3] |= 0x1;
1042 if (temp & RH_A_NOCP) /* no overcurrent reporting? */
1043 data_buf [3] |= 0x10;
1044 else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
1045 data_buf [3] |= 0x8;
1046
1047 /* corresponds to data_buf[4-7] */
1048 datab [1] = 0;
1049 data_buf [5] = (temp & RH_A_POTPGT) >> 24;
1050 temp = roothub_b (&gohci);
1051 data_buf [7] = temp & RH_B_DR;
1052 if (data_buf [2] < 7) {
1053 data_buf [8] = 0xff;
1054 } else {
1055 data_buf [0] += 2;
1056 data_buf [8] = (temp & RH_B_DR) >> 8;
1057 data_buf [10] = data_buf [9] = 0xff;
1058 }
1059
1060 len = min_t(unsigned int, leni,
1061 min_t(unsigned int, data_buf [0], wLength));
1062 OK (len);
1063 }
1064
1065 case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1);
1066
1067 case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
1068
1069 default:
1070 dbg ("unsupported root hub command");
1071 stat = USB_ST_STALLED;
1072 }
1073
1074 #ifdef DEBUG
1075 ohci_dump_roothub (&gohci, 1);
1076 #else
1077 mdelay(1);
1078 #endif
1079
1080 len = min_t(int, len, leni);
1081 if (data != data_buf)
1082 memcpy (data, data_buf, len);
1083 dev->act_len = len;
1084 dev->status = stat;
1085
1086 #ifdef DEBUG
1087 if (transfer_len)
1088 urb_priv.actual_length = transfer_len;
1089 pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
1090 #else
1091 mdelay(1);
1092 #endif
1093
1094 return stat;
1095 }
1096
1097 /*-------------------------------------------------------------------------*/
1098
1099 /* common code for handling submit messages - used for all but root hub */
1100 /* accesses. */
submit_common_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int transfer_len,struct devrequest * setup,int interval)1101 int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1102 int transfer_len, struct devrequest *setup, int interval)
1103 {
1104 int stat = 0;
1105 int maxsize = usb_maxpacket(dev, pipe);
1106 int timeout;
1107
1108 /* device pulled? Shortcut the action. */
1109 if (devgone == dev) {
1110 dev->status = USB_ST_CRC_ERR;
1111 return 0;
1112 }
1113
1114 #ifdef DEBUG
1115 urb_priv.actual_length = 0;
1116 pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
1117 #else
1118 mdelay(1);
1119 #endif
1120 if (!maxsize) {
1121 err("submit_common_message: pipesize for pipe %lx is zero",
1122 pipe);
1123 return -1;
1124 }
1125
1126 if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
1127 err("sohci_submit_job failed");
1128 return -1;
1129 }
1130
1131 mdelay(10);
1132 /* ohci_dump_status(&gohci); */
1133
1134 /* allow more time for a BULK device to react - some are slow */
1135 #define BULK_TO 5000 /* timeout in milliseconds */
1136 if (usb_pipebulk(pipe))
1137 timeout = BULK_TO;
1138 else
1139 timeout = 100;
1140
1141 timeout *= 4;
1142 /* wait for it to complete */
1143 for (;;) {
1144 /* check whether the controller is done */
1145 stat = hc_interrupt();
1146 if (stat < 0) {
1147 stat = USB_ST_CRC_ERR;
1148 break;
1149 }
1150 if (stat >= 0 && stat != 0xff) {
1151 /* 0xff is returned for an SF-interrupt */
1152 break;
1153 }
1154 if (--timeout) {
1155 udelay(250); /* mdelay(1); */
1156 } else {
1157 err("CTL:TIMEOUT ");
1158 stat = USB_ST_CRC_ERR;
1159 break;
1160 }
1161 }
1162 /* we got an Root Hub Status Change interrupt */
1163 if (got_rhsc) {
1164 #ifdef DEBUG
1165 ohci_dump_roothub (&gohci, 1);
1166 #endif
1167 got_rhsc = 0;
1168 /* abuse timeout */
1169 timeout = rh_check_port_status(&gohci);
1170 if (timeout >= 0) {
1171 #if 0 /* this does nothing useful, but leave it here in case that changes */
1172 /* the called routine adds 1 to the passed value */
1173 usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
1174 #endif
1175 /*
1176 * XXX
1177 * This is potentially dangerous because it assumes
1178 * that only one device is ever plugged in!
1179 */
1180 devgone = dev;
1181 }
1182 }
1183
1184 dev->status = stat;
1185 dev->act_len = transfer_len;
1186
1187 #ifdef DEBUG
1188 pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
1189 #else
1190 mdelay(1);
1191 #endif
1192
1193 /* free TDs in urb_priv */
1194 urb_free_priv (&urb_priv);
1195 return 0;
1196 }
1197
1198 /* submit routines called from usb.c */
submit_bulk_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int transfer_len)1199 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1200 int transfer_len)
1201 {
1202 info("submit_bulk_msg");
1203 return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
1204 }
1205
submit_control_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int transfer_len,struct devrequest * setup)1206 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1207 int transfer_len, struct devrequest *setup)
1208 {
1209 int maxsize = usb_maxpacket(dev, pipe);
1210
1211 info("submit_control_msg");
1212 #ifdef DEBUG
1213 urb_priv.actual_length = 0;
1214 pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
1215 #else
1216 mdelay(1);
1217 #endif
1218 if (!maxsize) {
1219 err("submit_control_message: pipesize for pipe %lx is zero",
1220 pipe);
1221 return -1;
1222 }
1223 if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
1224 gohci.rh.dev = dev;
1225 /* root hub - redirect */
1226 return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
1227 setup);
1228 }
1229
1230 return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
1231 }
1232
submit_int_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int transfer_len,int interval)1233 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1234 int transfer_len, int interval)
1235 {
1236 info("submit_int_msg");
1237 return -1;
1238 }
1239
1240 /*-------------------------------------------------------------------------*
1241 * HC functions
1242 *-------------------------------------------------------------------------*/
1243
1244 /* reset the HC and BUS */
1245
hc_reset(ohci_t * ohci)1246 static int hc_reset (ohci_t *ohci)
1247 {
1248 int timeout = 30;
1249 int smm_timeout = 50; /* 0,5 sec */
1250
1251 if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
1252 writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
1253 info("USB HC TakeOver from SMM");
1254 while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
1255 mdelay (10);
1256 if (--smm_timeout == 0) {
1257 err("USB HC TakeOver failed!");
1258 return -1;
1259 }
1260 }
1261 }
1262
1263 /* Disable HC interrupts */
1264 writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
1265
1266 dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
1267 ohci->slot_name,
1268 readl (&ohci->regs->control));
1269
1270 /* Reset USB (needed by some controllers) */
1271 writel (0, &ohci->regs->control);
1272
1273 /* HC Reset requires max 10 us delay */
1274 writel (OHCI_HCR, &ohci->regs->cmdstatus);
1275 while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
1276 if (--timeout == 0) {
1277 err("USB HC reset timed out!");
1278 return -1;
1279 }
1280 udelay (1);
1281 }
1282 return 0;
1283 }
1284
1285 /*-------------------------------------------------------------------------*/
1286
1287 /* Start an OHCI controller, set the BUS operational
1288 * enable interrupts
1289 * connect the virtual root hub */
1290
hc_start(ohci_t * ohci)1291 static int hc_start (ohci_t * ohci)
1292 {
1293 __u32 mask;
1294 unsigned int fminterval;
1295
1296 ohci->disabled = 1;
1297
1298 /* Tell the controller where the control and bulk lists are
1299 * The lists are empty now. */
1300
1301 writel (0, &ohci->regs->ed_controlhead);
1302 writel (0, &ohci->regs->ed_bulkhead);
1303
1304 writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
1305
1306 fminterval = 0x2edf;
1307 writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
1308 fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
1309 writel (fminterval, &ohci->regs->fminterval);
1310 writel (0x628, &ohci->regs->lsthresh);
1311
1312 /* start controller operations */
1313 ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
1314 ohci->disabled = 0;
1315 writel (ohci->hc_control, &ohci->regs->control);
1316
1317 /* disable all interrupts */
1318 mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
1319 OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
1320 OHCI_INTR_OC | OHCI_INTR_MIE);
1321 writel (mask, &ohci->regs->intrdisable);
1322 /* clear all interrupts */
1323 mask &= ~OHCI_INTR_MIE;
1324 writel (mask, &ohci->regs->intrstatus);
1325 /* Choose the interrupts we care about now - but w/o MIE */
1326 mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
1327 writel (mask, &ohci->regs->intrenable);
1328
1329 #ifdef OHCI_USE_NPS
1330 /* required for AMD-756 and some Mac platforms */
1331 writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
1332 &ohci->regs->roothub.a);
1333 writel (RH_HS_LPSC, &ohci->regs->roothub.status);
1334 #endif /* OHCI_USE_NPS */
1335
1336 /* POTPGT delay is bits 24-31, in 2 ms units. */
1337 mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
1338
1339 /* connect the virtual root hub */
1340 ohci->rh.devnum = 0;
1341
1342 return 0;
1343 }
1344
1345 /*-------------------------------------------------------------------------*/
1346
1347 /* an interrupt happens */
1348
1349 static int
hc_interrupt(void)1350 hc_interrupt (void)
1351 {
1352 ohci_t *ohci = &gohci;
1353 struct ohci_regs *regs = ohci->regs;
1354 int ints;
1355 int stat = -1;
1356
1357 if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) {
1358 ints = OHCI_INTR_WDH;
1359 } else {
1360 ints = readl (®s->intrstatus);
1361 }
1362
1363 /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
1364
1365 if (ints & OHCI_INTR_RHSC) {
1366 got_rhsc = 1;
1367 }
1368
1369 if (ints & OHCI_INTR_UE) {
1370 ohci->disabled++;
1371 err ("OHCI Unrecoverable Error, controller usb-%s disabled",
1372 ohci->slot_name);
1373 /* e.g. due to PCI Master/Target Abort */
1374
1375 #ifdef DEBUG
1376 ohci_dump (ohci, 1);
1377 #else
1378 mdelay(1);
1379 #endif
1380 /* FIXME: be optimistic, hope that bug won't repeat often. */
1381 /* Make some non-interrupt context restart the controller. */
1382 /* Count and limit the retries though; either hardware or */
1383 /* software errors can go forever... */
1384 hc_reset (ohci);
1385 return -1;
1386 }
1387
1388 if (ints & OHCI_INTR_WDH) {
1389 mdelay(1);
1390 writel (OHCI_INTR_WDH, ®s->intrdisable);
1391 stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
1392 writel (OHCI_INTR_WDH, ®s->intrenable);
1393 }
1394
1395 if (ints & OHCI_INTR_SO) {
1396 dbg("USB Schedule overrun\n");
1397 writel (OHCI_INTR_SO, ®s->intrenable);
1398 stat = -1;
1399 }
1400
1401 /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
1402 if (ints & OHCI_INTR_SF) {
1403 unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;
1404 mdelay(1);
1405 writel (OHCI_INTR_SF, ®s->intrdisable);
1406 if (ohci->ed_rm_list[frame] != NULL)
1407 writel (OHCI_INTR_SF, ®s->intrenable);
1408 stat = 0xff;
1409 }
1410
1411 writel (ints, ®s->intrstatus);
1412 return stat;
1413 }
1414
1415 /*-------------------------------------------------------------------------*/
1416
1417 /*-------------------------------------------------------------------------*/
1418
1419 /* De-allocate all resources.. */
1420
hc_release_ohci(ohci_t * ohci)1421 static void hc_release_ohci (ohci_t *ohci)
1422 {
1423 dbg ("USB HC release ohci usb-%s", ohci->slot_name);
1424
1425 if (!ohci->disabled)
1426 hc_reset (ohci);
1427 }
1428
1429 /*-------------------------------------------------------------------------*/
1430
1431 #define __read_32bit_c0_register(source, sel) \
1432 ({ int __res; \
1433 if (sel == 0) \
1434 __asm__ __volatile__( \
1435 "mfc0\t%0, " #source "\n\t" \
1436 : "=r" (__res)); \
1437 else \
1438 __asm__ __volatile__( \
1439 ".set\tmips32\n\t" \
1440 "mfc0\t%0, " #source ", " #sel "\n\t" \
1441 ".set\tmips0\n\t" \
1442 : "=r" (__res)); \
1443 __res; \
1444 })
1445
1446 #define read_c0_prid() __read_32bit_c0_register($15, 0)
1447
1448 /*
1449 * low level initalisation routine, called from usb.c
1450 */
1451 static char ohci_inited = 0;
1452
usb_lowlevel_init(int index,enum usb_init_type init,void ** controller)1453 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1454 {
1455 u32 pin_func;
1456 u32 sys_freqctrl, sys_clksrc;
1457 u32 prid = read_c0_prid();
1458
1459 dbg("in usb_lowlevel_init\n");
1460
1461 /* zero and disable FREQ2 */
1462 sys_freqctrl = au_readl(SYS_FREQCTRL0);
1463 sys_freqctrl &= ~0xFFF00000;
1464 au_writel(sys_freqctrl, SYS_FREQCTRL0);
1465
1466 /* zero and disable USBH/USBD clocks */
1467 sys_clksrc = au_readl(SYS_CLKSRC);
1468 sys_clksrc &= ~0x00007FE0;
1469 au_writel(sys_clksrc, SYS_CLKSRC);
1470
1471 sys_freqctrl = au_readl(SYS_FREQCTRL0);
1472 sys_freqctrl &= ~0xFFF00000;
1473
1474 sys_clksrc = au_readl(SYS_CLKSRC);
1475 sys_clksrc &= ~0x00007FE0;
1476
1477 switch (prid & 0x000000FF) {
1478 case 0x00: /* DA */
1479 case 0x01: /* HA */
1480 case 0x02: /* HB */
1481 /* CPU core freq to 48MHz to slow it way down... */
1482 au_writel(4, SYS_CPUPLL);
1483
1484 /*
1485 * Setup 48MHz FREQ2 from CPUPLL for USB Host
1486 */
1487 /* FRDIV2=3 -> div by 8 of 384MHz -> 48MHz */
1488 sys_freqctrl |= ((3<<22) | (1<<21) | (0<<20));
1489 au_writel(sys_freqctrl, SYS_FREQCTRL0);
1490
1491 /* CPU core freq to 384MHz */
1492 au_writel(0x20, SYS_CPUPLL);
1493
1494 printf("Au1000: 48MHz OHCI workaround enabled\n");
1495 break;
1496
1497 default: /* HC and newer */
1498 /* FREQ2 = aux/2 = 48 MHz */
1499 sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20));
1500 au_writel(sys_freqctrl, SYS_FREQCTRL0);
1501 break;
1502 }
1503
1504 /*
1505 * Route 48MHz FREQ2 into USB Host and/or Device
1506 */
1507 sys_clksrc |= ((4<<12) | (0<<11) | (0<<10));
1508 au_writel(sys_clksrc, SYS_CLKSRC);
1509
1510 /* configure pins GPIO[14:9] as GPIO */
1511 pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8080);
1512
1513 au_writel(pin_func, SYS_PINFUNC);
1514 au_writel(0x2800, SYS_TRIOUTCLR);
1515 au_writel(0x0030, SYS_OUTPUTCLR);
1516
1517 dbg("OHCI board setup complete\n");
1518
1519 /* enable host controller */
1520 au_writel(USBH_ENABLE_CE, USB_HOST_CONFIG);
1521 udelay(1000);
1522 au_writel(USBH_ENABLE_INIT, USB_HOST_CONFIG);
1523 udelay(1000);
1524
1525 /* wait for reset complete (read register twice; see au1500 errata) */
1526 while (au_readl(USB_HOST_CONFIG),
1527 !(au_readl(USB_HOST_CONFIG) & USBH_ENABLE_RD))
1528 udelay(1000);
1529
1530 dbg("OHCI clock running\n");
1531
1532 memset (&gohci, 0, sizeof (ohci_t));
1533 memset (&urb_priv, 0, sizeof (urb_priv_t));
1534
1535 /* align the storage */
1536 if ((__u32)&ghcca[0] & 0xff) {
1537 err("HCCA not aligned!!");
1538 return -1;
1539 }
1540 phcca = &ghcca[0];
1541 info("aligned ghcca %p", phcca);
1542 memset(&ohci_dev, 0, sizeof(struct ohci_device));
1543 if ((__u32)&ohci_dev.ed[0] & 0x7) {
1544 err("EDs not aligned!!");
1545 return -1;
1546 }
1547 memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
1548 if ((__u32)gtd & 0x7) {
1549 err("TDs not aligned!!");
1550 return -1;
1551 }
1552 ptd = gtd;
1553 gohci.hcca = phcca;
1554 memset (phcca, 0, sizeof (struct ohci_hcca));
1555
1556 gohci.disabled = 1;
1557 gohci.sleeping = 0;
1558 gohci.irq = -1;
1559 gohci.regs = (struct ohci_regs *)(USB_OHCI_BASE | 0xA0000000);
1560
1561 gohci.flags = 0;
1562 gohci.slot_name = "au1x00";
1563
1564 dbg("OHCI revision: 0x%08x\n"
1565 " RH: a: 0x%08x b: 0x%08x\n",
1566 readl(&gohci.regs->revision),
1567 readl(&gohci.regs->roothub.a), readl(&gohci.regs->roothub.b));
1568
1569 if (hc_reset (&gohci) < 0)
1570 goto errout;
1571
1572 /* FIXME this is a second HC reset; why?? */
1573 writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
1574 mdelay (10);
1575
1576 if (hc_start (&gohci) < 0)
1577 goto errout;
1578
1579 #ifdef DEBUG
1580 ohci_dump (&gohci, 1);
1581 #else
1582 mdelay(1);
1583 #endif
1584 ohci_inited = 1;
1585 return 0;
1586
1587 errout:
1588 err("OHCI initialization error\n");
1589 hc_release_ohci (&gohci);
1590 /* Initialization failed */
1591 au_writel(readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG);
1592 return -1;
1593 }
1594
usb_lowlevel_stop(int index)1595 int usb_lowlevel_stop(int index)
1596 {
1597 /* this gets called really early - before the controller has */
1598 /* even been initialized! */
1599 if (!ohci_inited)
1600 return 0;
1601 /* TODO release any interrupts, etc. */
1602 /* call hc_release_ohci() here ? */
1603 hc_reset (&gohci);
1604 /* may not want to do this */
1605 /* Disable clock */
1606 au_writel(readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG);
1607 return 0;
1608 }
1609
1610 #endif /* CONFIG_USB_OHCI */
1611