1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 /* 3 * Copyright (c) 2022 Rockchip Electronics Co. Ltd. 4 * Author: Finley Xiao <finley.xiao@rock-chips.com> 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3562_H 8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3562_H 9 10 /* cru-clocks indices */ 11 12 /* cru plls */ 13 #define PLL_APLL 1 14 #define PLL_GPLL 2 15 #define PLL_VPLL 3 16 #define PLL_HPLL 4 17 #define PLL_CPLL 5 18 #define PLL_DPLL 6 19 20 /* cru clocks */ 21 #define ARMCLK 8 22 #define CLK_GPU 9 23 #define ACLK_RKNN 10 24 #define CLK_DDR 11 25 #define CLK_MATRIX_50M_SRC 12 26 #define CLK_MATRIX_100M_SRC 13 27 #define CLK_MATRIX_125M_SRC 14 28 #define CLK_MATRIX_200M_SRC 15 29 #define CLK_MATRIX_300M_SRC 16 30 #define ACLK_TOP 17 31 #define ACLK_TOP_VIO 18 32 #define CLK_CAM0_OUT2IO 19 33 #define CLK_CAM1_OUT2IO 20 34 #define CLK_CAM2_OUT2IO 21 35 #define CLK_CAM3_OUT2IO 22 36 #define ACLK_BUS 23 37 #define HCLK_BUS 24 38 #define PCLK_BUS 25 39 #define PCLK_I2C1 26 40 #define PCLK_I2C2 27 41 #define PCLK_I2C3 28 42 #define PCLK_I2C4 29 43 #define PCLK_I2C5 30 44 #define CLK_I2C 31 45 #define CLK_I2C1 32 46 #define CLK_I2C2 33 47 #define CLK_I2C3 34 48 #define CLK_I2C4 35 49 #define CLK_I2C5 36 50 #define DCLK_BUS_GPIO 37 51 #define DCLK_BUS_GPIO3 38 52 #define DCLK_BUS_GPIO4 39 53 #define PCLK_TIMER 40 54 #define CLK_TIMER0 41 55 #define CLK_TIMER1 42 56 #define CLK_TIMER2 43 57 #define CLK_TIMER3 44 58 #define CLK_TIMER4 45 59 #define CLK_TIMER5 46 60 #define PCLK_STIMER 47 61 #define CLK_STIMER0 48 62 #define CLK_STIMER1 49 63 #define PCLK_WDTNS 50 64 #define CLK_WDTNS 51 65 #define PCLK_GRF 52 66 #define PCLK_SGRF 53 67 #define PCLK_MAILBOX 54 68 #define PCLK_INTC 55 69 #define ACLK_BUS_GIC400 56 70 #define ACLK_BUS_SPINLOCK 57 71 #define ACLK_DCF 58 72 #define PCLK_DCF 59 73 #define FCLK_BUS_CM0_CORE 60 74 #define CLK_BUS_CM0_RTC 61 75 #define HCLK_ICACHE 62 76 #define HCLK_DCACHE 63 77 #define PCLK_TSADC 64 78 #define CLK_TSADC 65 79 #define CLK_TSADC_TSEN 66 80 #define PCLK_DFT2APB 67 81 #define CLK_SARADC_VCCIO156 68 82 #define PCLK_GMAC 69 83 #define ACLK_GMAC 70 84 #define CLK_GMAC_125M_CRU_I 71 85 #define CLK_GMAC_50M_CRU_I 72 86 #define CLK_GMAC_50M_O 73 87 #define CLK_GMAC_ETH_OUT2IO 74 88 #define PCLK_APB2ASB_VCCIO156 75 89 #define PCLK_TO_VCCIO156 76 90 #define PCLK_DSIPHY 77 91 #define PCLK_DSITX 78 92 #define PCLK_CPU_EMA_DET 79 93 #define PCLK_HASH 80 94 #define PCLK_TOPCRU 81 95 #define PCLK_ASB2APB_VCCIO156 82 96 #define PCLK_IOC_VCCIO156 83 97 #define PCLK_GPIO3_VCCIO156 84 98 #define PCLK_GPIO4_VCCIO156 85 99 #define PCLK_SARADC_VCCIO156 86 100 #define PCLK_MAC100 87 101 #define ACLK_MAC100 89 102 #define CLK_MAC100_50M_MATRIX 90 103 #define HCLK_CORE 91 104 #define PCLK_DDR 92 105 #define CLK_MSCH_BRG_BIU 93 106 #define PCLK_DDR_HWLP 94 107 #define PCLK_DDR_UPCTL 95 108 #define PCLK_DDR_PHY 96 109 #define PCLK_DDR_DFICTL 97 110 #define PCLK_DDR_DMA2DDR 98 111 #define PCLK_DDR_MON 99 112 #define TMCLK_DDR_MON 100 113 #define PCLK_DDR_GRF 101 114 #define PCLK_DDR_CRU 102 115 #define PCLK_SUBDDR_CRU 103 116 #define CLK_GPU_PRE 104 117 #define ACLK_GPU_PRE 105 118 #define CLK_GPU_BRG 107 119 #define CLK_NPU_PRE 108 120 #define HCLK_NPU_PRE 109 121 #define HCLK_RKNN 111 122 #define ACLK_PERI 112 123 #define HCLK_PERI 113 124 #define PCLK_PERI 114 125 #define PCLK_PERICRU 115 126 #define HCLK_SAI0 116 127 #define CLK_SAI0_SRC 117 128 #define CLK_SAI0_FRAC 118 129 #define CLK_SAI0 119 130 #define MCLK_SAI0 120 131 #define MCLK_SAI0_OUT2IO 121 132 #define HCLK_SAI1 122 133 #define CLK_SAI1_SRC 123 134 #define CLK_SAI1_FRAC 124 135 #define CLK_SAI1 125 136 #define MCLK_SAI1 126 137 #define MCLK_SAI1_OUT2IO 127 138 #define HCLK_SAI2 128 139 #define CLK_SAI2_SRC 129 140 #define CLK_SAI2_FRAC 130 141 #define CLK_SAI2 131 142 #define MCLK_SAI2 132 143 #define MCLK_SAI2_OUT2IO 133 144 #define HCLK_DSM 134 145 #define CLK_DSM 135 146 #define HCLK_PDM 136 147 #define MCLK_PDM 137 148 #define HCLK_SPDIF 138 149 #define CLK_SPDIF_SRC 139 150 #define CLK_SPDIF_FRAC 140 151 #define CLK_SPDIF 141 152 #define MCLK_SPDIF 142 153 #define HCLK_SDMMC0 143 154 #define CCLK_SDMMC0 144 155 #define HCLK_SDMMC1 145 156 #define CCLK_SDMMC1 146 157 #define SCLK_SDMMC0_DRV 147 158 #define SCLK_SDMMC0_SAMPLE 148 159 #define SCLK_SDMMC1_DRV 149 160 #define SCLK_SDMMC1_SAMPLE 150 161 #define HCLK_EMMC 151 162 #define ACLK_EMMC 152 163 #define CCLK_EMMC 153 164 #define BCLK_EMMC 154 165 #define TMCLK_EMMC 155 166 #define SCLK_SFC 156 167 #define HCLK_SFC 157 168 #define HCLK_USB2HOST 158 169 #define HCLK_USB2HOST_ARB 159 170 #define PCLK_SPI1 160 171 #define CLK_SPI1 161 172 #define SCLK_IN_SPI1 162 173 #define PCLK_SPI2 163 174 #define CLK_SPI2 164 175 #define SCLK_IN_SPI2 165 176 #define PCLK_UART1 166 177 #define PCLK_UART2 167 178 #define PCLK_UART3 168 179 #define PCLK_UART4 169 180 #define PCLK_UART5 170 181 #define PCLK_UART6 171 182 #define PCLK_UART7 172 183 #define PCLK_UART8 173 184 #define PCLK_UART9 174 185 #define CLK_UART1_SRC 175 186 #define CLK_UART1_FRAC 176 187 #define CLK_UART1 177 188 #define SCLK_UART1 178 189 #define CLK_UART2_SRC 179 190 #define CLK_UART2_FRAC 180 191 #define CLK_UART2 181 192 #define SCLK_UART2 182 193 #define CLK_UART3_SRC 183 194 #define CLK_UART3_FRAC 184 195 #define CLK_UART3 185 196 #define SCLK_UART3 186 197 #define CLK_UART4_SRC 187 198 #define CLK_UART4_FRAC 188 199 #define CLK_UART4 189 200 #define SCLK_UART4 190 201 #define CLK_UART5_SRC 191 202 #define CLK_UART5_FRAC 192 203 #define CLK_UART5 193 204 #define SCLK_UART5 194 205 #define CLK_UART6_SRC 195 206 #define CLK_UART6_FRAC 196 207 #define CLK_UART6 197 208 #define SCLK_UART6 198 209 #define CLK_UART7_SRC 199 210 #define CLK_UART7_FRAC 200 211 #define CLK_UART7 201 212 #define SCLK_UART7 202 213 #define CLK_UART8_SRC 203 214 #define CLK_UART8_FRAC 204 215 #define CLK_UART8 205 216 #define SCLK_UART8 206 217 #define CLK_UART9_SRC 207 218 #define CLK_UART9_FRAC 208 219 #define CLK_UART9 209 220 #define SCLK_UART9 210 221 #define PCLK_PWM1_PERI 211 222 #define CLK_PWM1_PERI 212 223 #define CLK_CAPTURE_PWM1_PERI 213 224 #define PCLK_PWM2_PERI 214 225 #define CLK_PWM2_PERI 215 226 #define CLK_CAPTURE_PWM2_PERI 216 227 #define PCLK_PWM3_PERI 217 228 #define CLK_PWM3_PERI 218 229 #define CLK_CAPTURE_PWM3_PERI 219 230 #define PCLK_CAN0 220 231 #define CLK_CAN0 221 232 #define PCLK_CAN1 222 233 #define CLK_CAN1 223 234 #define ACLK_CRYPTO 224 235 #define HCLK_CRYPTO 225 236 #define PCLK_CRYPTO 226 237 #define CLK_CORE_CRYPTO 227 238 #define CLK_PKA_CRYPTO 228 239 #define HCLK_KLAD 229 240 #define PCLK_KEY_READER 230 241 #define HCLK_RK_RNG_NS 231 242 #define HCLK_RK_RNG_S 232 243 #define HCLK_TRNG_NS 233 244 #define HCLK_TRNG_S 234 245 #define HCLK_CRYPTO_S 235 246 #define PCLK_PERI_WDT 236 247 #define TCLK_PERI_WDT 237 248 #define ACLK_SYSMEM 238 249 #define HCLK_BOOTROM 239 250 #define PCLK_PERI_GRF 240 251 #define ACLK_DMAC 241 252 #define ACLK_RKDMAC 242 253 #define PCLK_OTPC_NS 243 254 #define CLK_SBPI_OTPC_NS 244 255 #define CLK_USER_OTPC_NS 245 256 #define PCLK_OTPC_S 246 257 #define CLK_SBPI_OTPC_S 247 258 #define CLK_USER_OTPC_S 248 259 #define CLK_OTPC_ARB 249 260 #define PCLK_OTPPHY 250 261 #define PCLK_USB2PHY 251 262 #define PCLK_PIPEPHY 252 263 #define PCLK_SARADC 253 264 #define CLK_SARADC 254 265 #define PCLK_IOC_VCCIO234 255 266 #define PCLK_PERI_GPIO1 256 267 #define PCLK_PERI_GPIO2 257 268 #define DCLK_PERI_GPIO 258 269 #define DCLK_PERI_GPIO1 259 270 #define DCLK_PERI_GPIO2 260 271 #define ACLK_PHP 261 272 #define PCLK_PHP 262 273 #define ACLK_PCIE20_MST 263 274 #define ACLK_PCIE20_SLV 264 275 #define ACLK_PCIE20_DBI 265 276 #define PCLK_PCIE20 266 277 #define CLK_PCIE20_AUX 267 278 #define ACLK_USB3OTG 268 279 #define CLK_USB3OTG_SUSPEND 269 280 #define CLK_USB3OTG_REF 270 281 #define CLK_PIPEPHY_REF_FUNC 271 282 #define CLK_200M_PMU 272 283 #define CLK_RTC_32K 273 284 #define CLK_RTC32K_FRAC 274 285 #define BUSCLK_PDPMU0 275 286 #define PCLK_PMU0_CRU 276 287 #define PCLK_PMU0_PMU 277 288 #define CLK_PMU0_PMU 278 289 #define PCLK_PMU0_HP_TIMER 279 290 #define CLK_PMU0_HP_TIMER 280 291 #define CLK_PMU0_32K_HP_TIMER 281 292 #define PCLK_PMU0_PVTM 282 293 #define CLK_PMU0_PVTM 283 294 #define PCLK_IOC_PMUIO 284 295 #define PCLK_PMU0_GPIO0 285 296 #define DBCLK_PMU0_GPIO0 286 297 #define PCLK_PMU0_GRF 287 298 #define PCLK_PMU0_SGRF 288 299 #define CLK_DDR_FAIL_SAFE 289 300 #define PCLK_PMU0_SCRKEYGEN 290 301 #define PCLK_PMU1_CRU 291 302 #define HCLK_PMU1_MEM 292 303 #define PCLK_PMU0_I2C0 293 304 #define CLK_PMU0_I2C0 294 305 #define PCLK_PMU1_UART0 295 306 #define CLK_PMU1_UART0_SRC 296 307 #define CLK_PMU1_UART0_FRAC 297 308 #define CLK_PMU1_UART0 298 309 #define SCLK_PMU1_UART0 299 310 #define PCLK_PMU1_SPI0 300 311 #define CLK_PMU1_SPI0 301 312 #define SCLK_IN_PMU1_SPI0 302 313 #define PCLK_PMU1_PWM0 303 314 #define CLK_PMU1_PWM0 304 315 #define CLK_CAPTURE_PMU1_PWM0 305 316 #define CLK_PMU1_WIFI 306 317 #define FCLK_PMU1_CM0_CORE 307 318 #define CLK_PMU1_CM0_RTC 308 319 #define PCLK_PMU1_WDTNS 309 320 #define CLK_PMU1_WDTNS 310 321 #define PCLK_PMU1_MAILBOX 311 322 #define CLK_PIPEPHY_DIV 312 323 #define CLK_PIPEPHY_XIN24M 313 324 #define CLK_PIPEPHY_REF 314 325 #define CLK_24M_SSCSRC 315 326 #define CLK_USB2PHY_XIN24M 316 327 #define CLK_USB2PHY_REF 317 328 #define CLK_MIPIDSIPHY_XIN24M 318 329 #define CLK_MIPIDSIPHY_REF 319 330 #define ACLK_RGA_PRE 320 331 #define HCLK_RGA_PRE 321 332 #define ACLK_RGA 322 333 #define HCLK_RGA 323 334 #define CLK_RGA_CORE 324 335 #define ACLK_JDEC 325 336 #define HCLK_JDEC 326 337 #define ACLK_VDPU_PRE 327 338 #define CLK_RKVDEC_HEVC_CA 328 339 #define HCLK_VDPU_PRE 329 340 #define ACLK_RKVDEC 330 341 #define HCLK_RKVDEC 331 342 #define CLK_RKVENC_CORE 332 343 #define ACLK_VEPU_PRE 333 344 #define HCLK_VEPU_PRE 334 345 #define ACLK_RKVENC 335 346 #define HCLK_RKVENC 336 347 #define ACLK_VI 337 348 #define HCLK_VI 338 349 #define PCLK_VI 339 350 #define ACLK_ISP 340 351 #define HCLK_ISP 341 352 #define CLK_ISP 342 353 #define ACLK_VICAP 343 354 #define HCLK_VICAP 344 355 #define DCLK_VICAP 345 356 #define CSIRX0_CLK_DATA 346 357 #define CSIRX1_CLK_DATA 347 358 #define CSIRX2_CLK_DATA 348 359 #define CSIRX3_CLK_DATA 349 360 #define PCLK_CSIHOST0 350 361 #define PCLK_CSIHOST1 351 362 #define PCLK_CSIHOST2 352 363 #define PCLK_CSIHOST3 353 364 #define PCLK_CSIPHY0 354 365 #define PCLK_CSIPHY1 355 366 #define ACLK_VO_PRE 356 367 #define HCLK_VO_PRE 357 368 #define ACLK_VOP 358 369 #define HCLK_VOP 359 370 #define DCLK_VOP 360 371 #define DCLK_VOP1 361 372 #define ACLK_CRYPTO_S 362 373 #define PCLK_CRYPTO_S 363 374 #define CLK_CORE_CRYPTO_S 364 375 #define CLK_PKA_CRYPTO_S 365 376 377 #define CLK_NR_CLKS (CLK_PKA_CRYPTO_S + 1) 378 379 /* soft-reset indices */ 380 381 /********Name=SOFTRST_CON01,Offset=0x404********/ 382 #define SRST_A_TOP_BIU 16 383 #define SRST_A_TOP_VIO_BIU 17 384 #define SRST_REF_PVTPLL_LOGIC 18 385 /********Name=SOFTRST_CON03,Offset=0x40C********/ 386 #define SRST_NCOREPORESET0 48 387 #define SRST_NCOREPORESET1 49 388 #define SRST_NCOREPORESET2 50 389 #define SRST_NCOREPORESET3 51 390 #define SRST_NCORESET0 52 391 #define SRST_NCORESET1 53 392 #define SRST_NCORESET2 54 393 #define SRST_NCORESET3 55 394 #define SRST_NL2RESET 56 395 /********Name=SOFTRST_CON04,Offset=0x410********/ 396 #define SRST_DAP 73 397 #define SRST_P_DBG_DAPLITE 74 398 #define SRST_REF_PVTPLL_CORE 77 399 /********Name=SOFTRST_CON05,Offset=0x414********/ 400 #define SRST_A_CORE_BIU 80 401 #define SRST_P_CORE_BIU 81 402 #define SRST_H_CORE_BIU 82 403 /********Name=SOFTRST_CON06,Offset=0x418********/ 404 #define SRST_A_NPU_BIU 98 405 #define SRST_H_NPU_BIU 99 406 #define SRST_A_RKNN 100 407 #define SRST_H_RKNN 101 408 #define SRST_REF_PVTPLL_NPU 102 409 /********Name=SOFTRST_CON08,Offset=0x420********/ 410 #define SRST_A_GPU_BIU 131 411 #define SRST_GPU 132 412 #define SRST_REF_PVTPLL_GPU 133 413 #define SRST_GPU_BRG_BIU 134 414 /********Name=SOFTRST_CON09,Offset=0x424********/ 415 #define SRST_RKVENC_CORE 144 416 #define SRST_A_VEPU_BIU 147 417 #define SRST_H_VEPU_BIU 148 418 #define SRST_A_RKVENC 149 419 #define SRST_H_RKVENC 150 420 /********Name=SOFTRST_CON10,Offset=0x428********/ 421 #define SRST_RKVDEC_HEVC_CA 162 422 #define SRST_A_VDPU_BIU 165 423 #define SRST_H_VDPU_BIU 166 424 #define SRST_A_RKVDEC 167 425 #define SRST_H_RKVDEC 168 426 /********Name=SOFTRST_CON11,Offset=0x42C********/ 427 #define SRST_A_VI_BIU 179 428 #define SRST_H_VI_BIU 180 429 #define SRST_P_VI_BIU 181 430 #define SRST_ISP 184 431 #define SRST_A_VICAP 185 432 #define SRST_H_VICAP 186 433 #define SRST_D_VICAP 187 434 #define SRST_I0_VICAP 188 435 #define SRST_I1_VICAP 189 436 #define SRST_I2_VICAP 190 437 #define SRST_I3_VICAP 191 438 /********Name=SOFTRST_CON12,Offset=0x430********/ 439 #define SRST_P_CSIHOST0 192 440 #define SRST_P_CSIHOST1 193 441 #define SRST_P_CSIHOST2 194 442 #define SRST_P_CSIHOST3 195 443 #define SRST_P_CSIPHY0 196 444 #define SRST_P_CSIPHY1 197 445 /********Name=SOFTRST_CON13,Offset=0x434********/ 446 #define SRST_A_VO_BIU 211 447 #define SRST_H_VO_BIU 212 448 #define SRST_A_VOP 214 449 #define SRST_H_VOP 215 450 #define SRST_D_VOP 216 451 #define SRST_D_VOP1 217 452 /********Name=SOFTRST_CON14,Offset=0x438********/ 453 #define SRST_A_RGA_BIU 227 454 #define SRST_H_RGA_BIU 228 455 #define SRST_A_RGA 230 456 #define SRST_H_RGA 231 457 #define SRST_RGA_CORE 232 458 #define SRST_A_JDEC 233 459 #define SRST_H_JDEC 234 460 /********Name=SOFTRST_CON15,Offset=0x43C********/ 461 #define SRST_B_EBK_BIU 242 462 #define SRST_P_EBK_BIU 243 463 #define SRST_AHB2AXI_EBC 244 464 #define SRST_H_EBC 245 465 #define SRST_D_EBC 246 466 #define SRST_H_EINK 247 467 #define SRST_P_EINK 248 468 /********Name=SOFTRST_CON16,Offset=0x440********/ 469 #define SRST_P_PHP_BIU 258 470 #define SRST_A_PHP_BIU 259 471 #define SRST_P_PCIE20 263 472 #define SRST_PCIE20_POWERUP 264 473 #define SRST_USB3OTG 266 474 /********Name=SOFTRST_CON17,Offset=0x444********/ 475 #define SRST_PIPEPHY 275 476 /********Name=SOFTRST_CON18,Offset=0x448********/ 477 #define SRST_A_BUS_BIU 291 478 #define SRST_H_BUS_BIU 292 479 #define SRST_P_BUS_BIU 293 480 /********Name=SOFTRST_CON19,Offset=0x44C********/ 481 #define SRST_P_I2C1 304 482 #define SRST_P_I2C2 305 483 #define SRST_P_I2C3 306 484 #define SRST_P_I2C4 307 485 #define SRST_P_I2C5 308 486 #define SRST_I2C1 310 487 #define SRST_I2C2 311 488 #define SRST_I2C3 312 489 #define SRST_I2C4 313 490 #define SRST_I2C5 314 491 /********Name=SOFTRST_CON20,Offset=0x450********/ 492 #define SRST_BUS_GPIO3 325 493 #define SRST_BUS_GPIO4 326 494 /********Name=SOFTRST_CON21,Offset=0x454********/ 495 #define SRST_P_TIMER 336 496 #define SRST_TIMER0 337 497 #define SRST_TIMER1 338 498 #define SRST_TIMER2 339 499 #define SRST_TIMER3 340 500 #define SRST_TIMER4 341 501 #define SRST_TIMER5 342 502 #define SRST_P_STIMER 343 503 #define SRST_STIMER0 344 504 #define SRST_STIMER1 345 505 /********Name=SOFTRST_CON22,Offset=0x458********/ 506 #define SRST_P_WDTNS 352 507 #define SRST_WDTNS 353 508 #define SRST_P_GRF 354 509 #define SRST_P_SGRF 355 510 #define SRST_P_MAILBOX 356 511 #define SRST_P_INTC 357 512 #define SRST_A_BUS_GIC400 358 513 #define SRST_A_BUS_GIC400_DEBUG 359 514 /********Name=SOFTRST_CON23,Offset=0x45C********/ 515 #define SRST_A_BUS_SPINLOCK 368 516 #define SRST_A_DCF 369 517 #define SRST_P_DCF 370 518 #define SRST_F_BUS_CM0_CORE 371 519 #define SRST_T_BUS_CM0_JTAG 373 520 #define SRST_H_ICACHE 376 521 #define SRST_H_DCACHE 377 522 /********Name=SOFTRST_CON24,Offset=0x460********/ 523 #define SRST_P_TSADC 384 524 #define SRST_TSADC 385 525 #define SRST_TSADCPHY 386 526 #define SRST_P_DFT2APB 388 527 /********Name=SOFTRST_CON25,Offset=0x464********/ 528 #define SRST_A_GMAC 401 529 #define SRST_P_APB2ASB_VCCIO156 405 530 #define SRST_P_DSIPHY 408 531 #define SRST_P_DSITX 409 532 #define SRST_P_CPU_EMA_DET 410 533 #define SRST_P_HASH 411 534 #define SRST_P_TOPCRU 415 535 /********Name=SOFTRST_CON26,Offset=0x468********/ 536 #define SRST_P_ASB2APB_VCCIO156 416 537 #define SRST_P_IOC_VCCIO156 417 538 #define SRST_P_GPIO3_VCCIO156 418 539 #define SRST_P_GPIO4_VCCIO156 419 540 #define SRST_P_SARADC_VCCIO156 420 541 #define SRST_SARADC_VCCIO156 421 542 #define SRST_SARADC_VCCIO156_PHY 422 543 /********Name=SOFTRST_CON27,Offset=0x46c********/ 544 #define SRST_A_MAC100 433 545 546 /* (0x10200 - 0x400) / 4 * 16 = 260096 */ 547 /********Name=PMU0SOFTRST_CON00,Offset=0x10200********/ 548 #define SRST_P_PMU0_CRU 260096 549 #define SRST_P_PMU0_PMU 260097 550 #define SRST_PMU0_PMU 260098 551 #define SRST_P_PMU0_HP_TIMER 260099 552 #define SRST_PMU0_HP_TIMER 260100 553 #define SRST_PMU0_32K_HP_TIMER 260101 554 #define SRST_P_PMU0_PVTM 260102 555 #define SRST_PMU0_PVTM 260103 556 #define SRST_P_IOC_PMUIO 260104 557 #define SRST_P_PMU0_GPIO0 260105 558 #define SRST_PMU0_GPIO0 260106 559 #define SRST_P_PMU0_GRF 260107 560 #define SRST_P_PMU0_SGRF 260108 561 /********Name=PMU0SOFTRST_CON01,Offset=0x10204********/ 562 #define SRST_DDR_FAIL_SAFE 260112 563 #define SRST_P_PMU0_SCRKEYGEN 260113 564 /********Name=PMU0SOFTRST_CON02,Offset=0x10208********/ 565 #define SRST_P_PMU0_I2C0 260136 566 #define SRST_PMU0_I2C0 260137 567 568 /* (0x18200 - 0x400) / 4 * 16 = 391168 */ 569 /********Name=PMU1SOFTRST_CON00,Offset=0x18200********/ 570 #define SRST_P_PMU1_CRU 391168 571 #define SRST_H_PMU1_MEM 391170 572 #define SRST_H_PMU1_BIU 391171 573 #define SRST_P_PMU1_BIU 391172 574 #define SRST_P_PMU1_UART0 391175 575 #define SRST_S_PMU1_UART0 391178 576 /********Name=PMU1SOFTRST_CON01,Offset=0x18204********/ 577 #define SRST_P_PMU1_SPI0 391184 578 #define SRST_PMU1_SPI0 391185 579 #define SRST_P_PMU1_PWM0 391187 580 #define SRST_PMU1_PWM0 391188 581 /********Name=PMU1SOFTRST_CON02,Offset=0x18208********/ 582 #define SRST_F_PMU1_CM0_CORE 391200 583 #define SRST_T_PMU1_CM0_JTAG 391202 584 #define SRST_P_PMU1_WDTNS 391203 585 #define SRST_PMU1_WDTNS 391204 586 #define SRST_PMU1_MAILBOX 391208 587 588 /* (0x20200 - 0x400) / 4 * 16 = 522240 */ 589 /********Name=DDRSOFTRST_CON00,Offset=0x20200********/ 590 #define SRST_MSCH_BRG_BIU 522244 591 #define SRST_P_MSCH_BIU 522245 592 #define SRST_P_DDR_HWLP 522246 593 #define SRST_P_DDR_PHY 522248 594 #define SRST_P_DDR_DFICTL 522249 595 #define SRST_P_DDR_DMA2DDR 522250 596 /********Name=DDRSOFTRST_CON01,Offset=0x20204********/ 597 #define SRST_P_DDR_MON 522256 598 #define SRST_TM_DDR_MON 522257 599 #define SRST_P_DDR_GRF 522258 600 #define SRST_P_DDR_CRU 522259 601 #define SRST_P_SUBDDR_CRU 522260 602 603 /* (0x28200 - 0x400) / 4 * 16 = 653312 */ 604 /********Name=SUBDDRSOFTRST_CON00,Offset=0x28200********/ 605 #define SRST_MSCH_BIU 653313 606 #define SRST_DDR_PHY 653316 607 #define SRST_DDR_DFICTL 653317 608 #define SRST_DDR_SCRAMBLE 653318 609 #define SRST_DDR_MON 653319 610 #define SRST_A_DDR_SPLIT 653320 611 #define SRST_DDR_DMA2DDR 653321 612 613 /* (0x30400 - 0x400) / 4 * 16 = 786432 */ 614 /********Name=PERISOFTRST_CON01,Offset=0x30404********/ 615 #define SRST_A_PERI_BIU 786451 616 #define SRST_H_PERI_BIU 786452 617 #define SRST_P_PERI_BIU 786453 618 #define SRST_P_PERICRU 786454 619 /********Name=PERISOFTRST_CON02,Offset=0x30408********/ 620 #define SRST_H_SAI0_8CH 786464 621 #define SRST_M_SAI0_8CH 786467 622 #define SRST_H_SAI1_8CH 786469 623 #define SRST_M_SAI1_8CH 786472 624 #define SRST_H_SAI2_2CH 786474 625 #define SRST_M_SAI2_2CH 786477 626 /********Name=PERISOFTRST_CON03,Offset=0x3040C********/ 627 #define SRST_H_DSM 786481 628 #define SRST_DSM 786482 629 #define SRST_H_PDM 786484 630 #define SRST_M_PDM 786485 631 #define SRST_H_SPDIF 786488 632 #define SRST_M_SPDIF 786491 633 /********Name=PERISOFTRST_CON04,Offset=0x30410********/ 634 #define SRST_H_SDMMC0 786496 635 #define SRST_H_SDMMC1 786498 636 #define SRST_H_EMMC 786504 637 #define SRST_A_EMMC 786505 638 #define SRST_C_EMMC 786506 639 #define SRST_B_EMMC 786507 640 #define SRST_T_EMMC 786508 641 #define SRST_S_SFC 786509 642 #define SRST_H_SFC 786510 643 /********Name=PERISOFTRST_CON05,Offset=0x30414********/ 644 #define SRST_H_USB2HOST 786512 645 #define SRST_H_USB2HOST_ARB 786513 646 #define SRST_USB2HOST_UTMI 786514 647 /********Name=PERISOFTRST_CON06,Offset=0x30418********/ 648 #define SRST_P_SPI1 786528 649 #define SRST_SPI1 786529 650 #define SRST_P_SPI2 786531 651 #define SRST_SPI2 786532 652 /********Name=PERISOFTRST_CON07,Offset=0x3041C********/ 653 #define SRST_P_UART1 786544 654 #define SRST_P_UART2 786545 655 #define SRST_P_UART3 786546 656 #define SRST_P_UART4 786547 657 #define SRST_P_UART5 786548 658 #define SRST_P_UART6 786549 659 #define SRST_P_UART7 786550 660 #define SRST_P_UART8 786551 661 #define SRST_P_UART9 786552 662 #define SRST_S_UART1 786555 663 #define SRST_S_UART2 786558 664 /********Name=PERISOFTRST_CON08,Offset=0x30420********/ 665 #define SRST_S_UART3 786561 666 #define SRST_S_UART4 786564 667 #define SRST_S_UART5 786567 668 #define SRST_S_UART6 786570 669 #define SRST_S_UART7 786573 670 /********Name=PERISOFTRST_CON09,Offset=0x30424********/ 671 #define SRST_S_UART8 786576 672 #define SRST_S_UART9 786579 673 /********Name=PERISOFTRST_CON10,Offset=0x30428********/ 674 #define SRST_P_PWM1_PERI 786592 675 #define SRST_PWM1_PERI 786593 676 #define SRST_P_PWM2_PERI 786595 677 #define SRST_PWM2_PERI 786596 678 #define SRST_P_PWM3_PERI 786598 679 #define SRST_PWM3_PERI 786599 680 /********Name=PERISOFTRST_CON11,Offset=0x3042C********/ 681 #define SRST_P_CAN0 786608 682 #define SRST_CAN0 786609 683 #define SRST_P_CAN1 786610 684 #define SRST_CAN1 786611 685 /********Name=PERISOFTRST_CON12,Offset=0x30430********/ 686 #define SRST_A_CRYPTO 786624 687 #define SRST_H_CRYPTO 786625 688 #define SRST_P_CRYPTO 786626 689 #define SRST_CORE_CRYPTO 786627 690 #define SRST_PKA_CRYPTO 786628 691 #define SRST_H_KLAD 786629 692 #define SRST_P_KEY_READER 786630 693 #define SRST_H_RK_RNG_NS 786631 694 #define SRST_H_RK_RNG_S 786632 695 #define SRST_H_TRNG_NS 786633 696 #define SRST_H_TRNG_S 786634 697 #define SRST_H_CRYPTO_S 786635 698 /********Name=PERISOFTRST_CON13,Offset=0x30434********/ 699 #define SRST_P_PERI_WDT 786640 700 #define SRST_T_PERI_WDT 786641 701 #define SRST_A_SYSMEM 786642 702 #define SRST_H_BOOTROM 786643 703 #define SRST_P_PERI_GRF 786644 704 #define SRST_A_DMAC 786645 705 #define SRST_A_RKDMAC 786646 706 /********Name=PERISOFTRST_CON14,Offset=0x30438********/ 707 #define SRST_P_OTPC_NS 786656 708 #define SRST_SBPI_OTPC_NS 786657 709 #define SRST_USER_OTPC_NS 786658 710 #define SRST_P_OTPC_S 786659 711 #define SRST_SBPI_OTPC_S 786660 712 #define SRST_USER_OTPC_S 786661 713 #define SRST_OTPC_ARB 786662 714 #define SRST_P_OTPPHY 786663 715 #define SRST_OTP_NPOR 786664 716 /********Name=PERISOFTRST_CON15,Offset=0x3043C********/ 717 #define SRST_P_USB2PHY 786672 718 #define SRST_USB2PHY_POR 786676 719 #define SRST_USB2PHY_OTG 786677 720 #define SRST_USB2PHY_HOST 786678 721 #define SRST_P_PIPEPHY 786679 722 /********Name=PERISOFTRST_CON16,Offset=0x30440********/ 723 #define SRST_P_SARADC 786692 724 #define SRST_SARADC 786693 725 #define SRST_SARADC_PHY 786694 726 #define SRST_P_IOC_VCCIO234 786700 727 /********Name=PERISOFTRST_CON17,Offset=0x30444********/ 728 #define SRST_P_PERI_GPIO1 786704 729 #define SRST_P_PERI_GPIO2 786705 730 #define SRST_PERI_GPIO1 786706 731 #define SRST_PERI_GPIO2 786707 732 733 #endif 734