1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2017 Rockchip Electronics Co., Ltd
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun #include <asm/io.h>
7*4882a593Smuzhiyun #include <asm/arch/hardware.h>
8*4882a593Smuzhiyun #include <asm/arch/bootrom.h>
9*4882a593Smuzhiyun #include <asm/arch/grf_rk3128.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #define GRF_GPIO1C_IOMUX 0x200080c0
12*4882a593Smuzhiyun #define SDMMC_INTMASK 0x10214024
13*4882a593Smuzhiyun #define READLATENCY_VAL 0x3f
14*4882a593Smuzhiyun #define BUS_MSCH_QOS_BASE 0x10128014
15*4882a593Smuzhiyun #define CPU_AXI_QOS_PRIORITY_BASE 0x1012f188
16*4882a593Smuzhiyun #define CPU_AXI_QOS_PRIORITY_LEVEL(h, l) \
17*4882a593Smuzhiyun ((((h) & 3) << 8) | (((h) & 3) << 2) | ((l) & 3))
18*4882a593Smuzhiyun #define CPU_AXI_CIF_QOS_PRIORITY_BASE 0x1012f208
19*4882a593Smuzhiyun
arch_cpu_init(void)20*4882a593Smuzhiyun int arch_cpu_init(void)
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun /* We do some SoC one time setting here. */
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /* Read latency configure */
25*4882a593Smuzhiyun writel(READLATENCY_VAL, BUS_MSCH_QOS_BASE);
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* Set lcdc cpu axi qos priority level */
28*4882a593Smuzhiyun writel(CPU_AXI_QOS_PRIORITY_LEVEL(3, 3), CPU_AXI_QOS_PRIORITY_BASE);
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /* Set GPIO1_C1 iomux to gpio, default sdcard_detn */
31*4882a593Smuzhiyun writel(0x00040000, GRF_GPIO1C_IOMUX);
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #ifdef CONFIG_ROCKCHIP_RK3126
34*4882a593Smuzhiyun /*
35*4882a593Smuzhiyun * Disable interrupt, otherwise it always generates wakeup signal. This
36*4882a593Smuzhiyun * is an IC hardware issue.
37*4882a593Smuzhiyun */
38*4882a593Smuzhiyun writel(0, SDMMC_INTMASK);
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /* raise cif ddr qos priority */
41*4882a593Smuzhiyun writel(CPU_AXI_QOS_PRIORITY_LEVEL(3, 3), CPU_AXI_CIF_QOS_PRIORITY_BASE);
42*4882a593Smuzhiyun #endif
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun return 0;
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
board_debug_uart_init(void)47*4882a593Smuzhiyun void board_debug_uart_init(void)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun struct rk3128_grf * const grf __maybe_unused =
50*4882a593Smuzhiyun (struct rk3128_grf * const)0x20008000;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun enum {
53*4882a593Smuzhiyun /* UART2 */
54*4882a593Smuzhiyun GPIO1C2_SHIFT = 4,
55*4882a593Smuzhiyun GPIO1C2_MASK = GENMASK(5, 4),
56*4882a593Smuzhiyun GPIO1C2_GPIO = 0,
57*4882a593Smuzhiyun GPIO1C2_MMC0_D0 = 1,
58*4882a593Smuzhiyun GPIO1C2_UART2_TX = 2,
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun GPIO1C3_SHIFT = 6,
61*4882a593Smuzhiyun GPIO1C3_MASK = GENMASK(7, 6),
62*4882a593Smuzhiyun GPIO1C3_GPIO = 0,
63*4882a593Smuzhiyun GPIO1C2_MMC0_D1 = 1,
64*4882a593Smuzhiyun GPIO1C2_UART2_RX = 2,
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun rk_clrsetreg(&grf->gpio1c_iomux,
68*4882a593Smuzhiyun GPIO1C2_MASK, GPIO1C2_UART2_TX << GPIO1C2_SHIFT);
69*4882a593Smuzhiyun rk_clrsetreg(&grf->gpio1c_iomux,
70*4882a593Smuzhiyun GPIO1C3_MASK, GPIO1C2_UART2_RX << GPIO1C3_SHIFT);
71*4882a593Smuzhiyun }
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