1 /*
2 * Copyright (c) 2017 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6 #include <asm/io.h>
7 #include <asm/arch/hardware.h>
8 #include <asm/arch/bootrom.h>
9 #include <asm/arch/grf_rk3128.h>
10
11 #define GRF_GPIO1C_IOMUX 0x200080c0
12 #define SDMMC_INTMASK 0x10214024
13 #define READLATENCY_VAL 0x3f
14 #define BUS_MSCH_QOS_BASE 0x10128014
15 #define CPU_AXI_QOS_PRIORITY_BASE 0x1012f188
16 #define CPU_AXI_QOS_PRIORITY_LEVEL(h, l) \
17 ((((h) & 3) << 8) | (((h) & 3) << 2) | ((l) & 3))
18 #define CPU_AXI_CIF_QOS_PRIORITY_BASE 0x1012f208
19
arch_cpu_init(void)20 int arch_cpu_init(void)
21 {
22 /* We do some SoC one time setting here. */
23
24 /* Read latency configure */
25 writel(READLATENCY_VAL, BUS_MSCH_QOS_BASE);
26
27 /* Set lcdc cpu axi qos priority level */
28 writel(CPU_AXI_QOS_PRIORITY_LEVEL(3, 3), CPU_AXI_QOS_PRIORITY_BASE);
29
30 /* Set GPIO1_C1 iomux to gpio, default sdcard_detn */
31 writel(0x00040000, GRF_GPIO1C_IOMUX);
32
33 #ifdef CONFIG_ROCKCHIP_RK3126
34 /*
35 * Disable interrupt, otherwise it always generates wakeup signal. This
36 * is an IC hardware issue.
37 */
38 writel(0, SDMMC_INTMASK);
39
40 /* raise cif ddr qos priority */
41 writel(CPU_AXI_QOS_PRIORITY_LEVEL(3, 3), CPU_AXI_CIF_QOS_PRIORITY_BASE);
42 #endif
43
44 return 0;
45 }
46
board_debug_uart_init(void)47 void board_debug_uart_init(void)
48 {
49 struct rk3128_grf * const grf __maybe_unused =
50 (struct rk3128_grf * const)0x20008000;
51
52 enum {
53 /* UART2 */
54 GPIO1C2_SHIFT = 4,
55 GPIO1C2_MASK = GENMASK(5, 4),
56 GPIO1C2_GPIO = 0,
57 GPIO1C2_MMC0_D0 = 1,
58 GPIO1C2_UART2_TX = 2,
59
60 GPIO1C3_SHIFT = 6,
61 GPIO1C3_MASK = GENMASK(7, 6),
62 GPIO1C3_GPIO = 0,
63 GPIO1C2_MMC0_D1 = 1,
64 GPIO1C2_UART2_RX = 2,
65 };
66
67 rk_clrsetreg(&grf->gpio1c_iomux,
68 GPIO1C2_MASK, GPIO1C2_UART2_TX << GPIO1C2_SHIFT);
69 rk_clrsetreg(&grf->gpio1c_iomux,
70 GPIO1C3_MASK, GPIO1C2_UART2_RX << GPIO1C3_SHIFT);
71 }
72