1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2020 Rockchip Electronics Co., Ltd
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <common.h>
7*4882a593Smuzhiyun #include <dm.h>
8*4882a593Smuzhiyun #include <ram.h>
9*4882a593Smuzhiyun #include <asm/io.h>
10*4882a593Smuzhiyun #include <asm/arch/param.h>
11*4882a593Smuzhiyun #include <asm/arch/rk_atags.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
14*4882a593Smuzhiyun
fpga_init_atags(void)15*4882a593Smuzhiyun static void fpga_init_atags(void)
16*4882a593Smuzhiyun {
17*4882a593Smuzhiyun #ifdef CONFIG_FPGA_RAM
18*4882a593Smuzhiyun struct tag_ram_partition t_ram_part;
19*4882a593Smuzhiyun #endif
20*4882a593Smuzhiyun struct tag_bootdev t_bootdev;
21*4882a593Smuzhiyun struct tag_ddr_mem t_ddrmem;
22*4882a593Smuzhiyun struct tag_serial t_serial;
23*4882a593Smuzhiyun struct tag_tos_mem t_tos;
24*4882a593Smuzhiyun #if defined(CONFIG_ARM64) || defined(CONFIG_ARM64_BOOT_AARCH32)
25*4882a593Smuzhiyun struct tag_atf_mem t_atf;
26*4882a593Smuzhiyun #endif
27*4882a593Smuzhiyun /* destroy ! */
28*4882a593Smuzhiyun atags_destroy();
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /* serial */
31*4882a593Smuzhiyun memset(&t_serial, 0, sizeof(t_serial));
32*4882a593Smuzhiyun t_serial.version = 0;
33*4882a593Smuzhiyun t_serial.enable = 1;
34*4882a593Smuzhiyun t_serial.addr = CONFIG_DEBUG_UART_BASE;
35*4882a593Smuzhiyun t_serial.baudrate = CONFIG_BAUDRATE;
36*4882a593Smuzhiyun t_serial.m_mode = 0;
37*4882a593Smuzhiyun t_serial.id = 2;
38*4882a593Smuzhiyun atags_set_tag(ATAG_SERIAL, &t_serial);
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /* ddr memory */
41*4882a593Smuzhiyun memset(&t_ddrmem, 0, sizeof(t_ddrmem));
42*4882a593Smuzhiyun t_ddrmem.version = 0;
43*4882a593Smuzhiyun t_ddrmem.count = 1;
44*4882a593Smuzhiyun t_ddrmem.bank[0] = CONFIG_SYS_SDRAM_BASE;
45*4882a593Smuzhiyun t_ddrmem.bank[1] = SZ_1G;
46*4882a593Smuzhiyun atags_set_tag(ATAG_DDR_MEM, &t_ddrmem);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /* bootdev */
49*4882a593Smuzhiyun memset(&t_bootdev, 0, sizeof(t_bootdev));
50*4882a593Smuzhiyun t_bootdev.version = 0;
51*4882a593Smuzhiyun #ifdef CONFIG_FPGA_RAM
52*4882a593Smuzhiyun t_bootdev.devtype = BOOT_TYPE_RAM;
53*4882a593Smuzhiyun #else
54*4882a593Smuzhiyun t_bootdev.devtype = BOOT_TYPE_EMMC;
55*4882a593Smuzhiyun #endif
56*4882a593Smuzhiyun t_bootdev.devnum = 0;
57*4882a593Smuzhiyun t_bootdev.sdupdate = 0;
58*4882a593Smuzhiyun atags_set_tag(ATAG_BOOTDEV, &t_bootdev);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /* atf */
61*4882a593Smuzhiyun #if defined(CONFIG_ARM64) || defined(CONFIG_ARM64_BOOT_AARCH32)
62*4882a593Smuzhiyun memset(&t_atf, 0, sizeof(t_atf));
63*4882a593Smuzhiyun t_atf.version = 0;
64*4882a593Smuzhiyun t_atf.phy_addr = CONFIG_SYS_SDRAM_BASE;
65*4882a593Smuzhiyun t_atf.size = SZ_1M;
66*4882a593Smuzhiyun t_atf.flags = 0;
67*4882a593Smuzhiyun atags_set_tag(ATAG_ATF_MEM, &t_atf);
68*4882a593Smuzhiyun #endif
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /* op-tee */
71*4882a593Smuzhiyun memset(&t_tos, 0, sizeof(t_tos));
72*4882a593Smuzhiyun t_tos.version = 0;
73*4882a593Smuzhiyun strcpy(t_tos.tee_mem.name, "op-tee");
74*4882a593Smuzhiyun #ifdef CONFIG_ARM64
75*4882a593Smuzhiyun t_tos.tee_mem.phy_addr = 0x8400000; /* 132M offset */
76*4882a593Smuzhiyun t_tos.tee_mem.size = 0x1e00000; /* 30M size */
77*4882a593Smuzhiyun #endif
78*4882a593Smuzhiyun t_tos.tee_mem.flags = 1;
79*4882a593Smuzhiyun atags_set_tag(ATAG_TOS_MEM, &t_tos);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun #ifdef CONFIG_FPGA_RAM
82*4882a593Smuzhiyun /* ram part */
83*4882a593Smuzhiyun memset(&t_ram_part, 0, sizeof(t_ram_part));
84*4882a593Smuzhiyun t_ram_part.version = 0;
85*4882a593Smuzhiyun t_ram_part.count = 1;
86*4882a593Smuzhiyun strcpy(t_ram_part.part[0].name, "boot");
87*4882a593Smuzhiyun t_ram_part.part[0].start = 0x4000000; /* 64M offset */
88*4882a593Smuzhiyun t_ram_part.part[0].size = 0x2000000; /* 32M size */
89*4882a593Smuzhiyun atags_set_tag(ATAG_RAM_PARTITION, &t_ram_part);
90*4882a593Smuzhiyun #endif
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun
arch_fpga_init(void)93*4882a593Smuzhiyun int arch_fpga_init(void)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun fpga_init_atags();
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun return 0;
98*4882a593Smuzhiyun }
99