1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2020 Rockchip Electronics Co., Ltd
4 */
5
6 #include <common.h>
7 #include <dm.h>
8 #include <ram.h>
9 #include <asm/io.h>
10 #include <asm/arch/param.h>
11 #include <asm/arch/rk_atags.h>
12
13 DECLARE_GLOBAL_DATA_PTR;
14
fpga_init_atags(void)15 static void fpga_init_atags(void)
16 {
17 #ifdef CONFIG_FPGA_RAM
18 struct tag_ram_partition t_ram_part;
19 #endif
20 struct tag_bootdev t_bootdev;
21 struct tag_ddr_mem t_ddrmem;
22 struct tag_serial t_serial;
23 struct tag_tos_mem t_tos;
24 #if defined(CONFIG_ARM64) || defined(CONFIG_ARM64_BOOT_AARCH32)
25 struct tag_atf_mem t_atf;
26 #endif
27 /* destroy ! */
28 atags_destroy();
29
30 /* serial */
31 memset(&t_serial, 0, sizeof(t_serial));
32 t_serial.version = 0;
33 t_serial.enable = 1;
34 t_serial.addr = CONFIG_DEBUG_UART_BASE;
35 t_serial.baudrate = CONFIG_BAUDRATE;
36 t_serial.m_mode = 0;
37 t_serial.id = 2;
38 atags_set_tag(ATAG_SERIAL, &t_serial);
39
40 /* ddr memory */
41 memset(&t_ddrmem, 0, sizeof(t_ddrmem));
42 t_ddrmem.version = 0;
43 t_ddrmem.count = 1;
44 t_ddrmem.bank[0] = CONFIG_SYS_SDRAM_BASE;
45 t_ddrmem.bank[1] = SZ_1G;
46 atags_set_tag(ATAG_DDR_MEM, &t_ddrmem);
47
48 /* bootdev */
49 memset(&t_bootdev, 0, sizeof(t_bootdev));
50 t_bootdev.version = 0;
51 #ifdef CONFIG_FPGA_RAM
52 t_bootdev.devtype = BOOT_TYPE_RAM;
53 #else
54 t_bootdev.devtype = BOOT_TYPE_EMMC;
55 #endif
56 t_bootdev.devnum = 0;
57 t_bootdev.sdupdate = 0;
58 atags_set_tag(ATAG_BOOTDEV, &t_bootdev);
59
60 /* atf */
61 #if defined(CONFIG_ARM64) || defined(CONFIG_ARM64_BOOT_AARCH32)
62 memset(&t_atf, 0, sizeof(t_atf));
63 t_atf.version = 0;
64 t_atf.phy_addr = CONFIG_SYS_SDRAM_BASE;
65 t_atf.size = SZ_1M;
66 t_atf.flags = 0;
67 atags_set_tag(ATAG_ATF_MEM, &t_atf);
68 #endif
69
70 /* op-tee */
71 memset(&t_tos, 0, sizeof(t_tos));
72 t_tos.version = 0;
73 strcpy(t_tos.tee_mem.name, "op-tee");
74 #ifdef CONFIG_ARM64
75 t_tos.tee_mem.phy_addr = 0x8400000; /* 132M offset */
76 t_tos.tee_mem.size = 0x1e00000; /* 30M size */
77 #endif
78 t_tos.tee_mem.flags = 1;
79 atags_set_tag(ATAG_TOS_MEM, &t_tos);
80
81 #ifdef CONFIG_FPGA_RAM
82 /* ram part */
83 memset(&t_ram_part, 0, sizeof(t_ram_part));
84 t_ram_part.version = 0;
85 t_ram_part.count = 1;
86 strcpy(t_ram_part.part[0].name, "boot");
87 t_ram_part.part[0].start = 0x4000000; /* 64M offset */
88 t_ram_part.part[0].size = 0x2000000; /* 32M size */
89 atags_set_tag(ATAG_RAM_PARTITION, &t_ram_part);
90 #endif
91 }
92
arch_fpga_init(void)93 int arch_fpga_init(void)
94 {
95 fpga_init_atags();
96
97 return 0;
98 }
99