1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <linux/libfdt.h>
9*4882a593Smuzhiyun #include <linux/err.h>
10*4882a593Smuzhiyun #include <asm/arch/gxbb.h>
11*4882a593Smuzhiyun #include <asm/arch/sm.h>
12*4882a593Smuzhiyun #include <asm/armv8/mmu.h>
13*4882a593Smuzhiyun #include <asm/unaligned.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
16*4882a593Smuzhiyun
dram_init(void)17*4882a593Smuzhiyun int dram_init(void)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun const fdt64_t *val;
20*4882a593Smuzhiyun int offset;
21*4882a593Smuzhiyun int len;
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun offset = fdt_path_offset(gd->fdt_blob, "/memory");
24*4882a593Smuzhiyun if (offset < 0)
25*4882a593Smuzhiyun return -EINVAL;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun val = fdt_getprop(gd->fdt_blob, offset, "reg", &len);
28*4882a593Smuzhiyun if (len < sizeof(*val) * 2)
29*4882a593Smuzhiyun return -EINVAL;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* Use unaligned access since cache is still disabled */
32*4882a593Smuzhiyun gd->ram_size = get_unaligned_be64(&val[1]);
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun return 0;
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun
dram_init_banksize(void)37*4882a593Smuzhiyun int dram_init_banksize(void)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun /* Reserve first 16 MiB of RAM for firmware */
40*4882a593Smuzhiyun gd->bd->bi_dram[0].start = 0x1000000;
41*4882a593Smuzhiyun gd->bd->bi_dram[0].size = 0xf000000;
42*4882a593Smuzhiyun /* Reserve 2 MiB for ARM Trusted Firmware (BL31) */
43*4882a593Smuzhiyun gd->bd->bi_dram[1].start = 0x10000000;
44*4882a593Smuzhiyun gd->bd->bi_dram[1].size = gd->ram_size - 0x10200000;
45*4882a593Smuzhiyun return 0;
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
reset_cpu(ulong addr)48*4882a593Smuzhiyun void reset_cpu(ulong addr)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun psci_system_reset();
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun static struct mm_region gxbb_mem_map[] = {
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun .virt = 0x0UL,
56*4882a593Smuzhiyun .phys = 0x0UL,
57*4882a593Smuzhiyun .size = 0x80000000UL,
58*4882a593Smuzhiyun .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
59*4882a593Smuzhiyun PTE_BLOCK_INNER_SHARE
60*4882a593Smuzhiyun }, {
61*4882a593Smuzhiyun .virt = 0x80000000UL,
62*4882a593Smuzhiyun .phys = 0x80000000UL,
63*4882a593Smuzhiyun .size = 0x80000000UL,
64*4882a593Smuzhiyun .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
65*4882a593Smuzhiyun PTE_BLOCK_NON_SHARE |
66*4882a593Smuzhiyun PTE_BLOCK_PXN | PTE_BLOCK_UXN
67*4882a593Smuzhiyun }, {
68*4882a593Smuzhiyun /* List terminator */
69*4882a593Smuzhiyun 0,
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun };
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun struct mm_region *mem_map = gxbb_mem_map;
74