1 /*
2 * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <common.h>
8 #include <linux/libfdt.h>
9 #include <linux/err.h>
10 #include <asm/arch/gxbb.h>
11 #include <asm/arch/sm.h>
12 #include <asm/armv8/mmu.h>
13 #include <asm/unaligned.h>
14
15 DECLARE_GLOBAL_DATA_PTR;
16
dram_init(void)17 int dram_init(void)
18 {
19 const fdt64_t *val;
20 int offset;
21 int len;
22
23 offset = fdt_path_offset(gd->fdt_blob, "/memory");
24 if (offset < 0)
25 return -EINVAL;
26
27 val = fdt_getprop(gd->fdt_blob, offset, "reg", &len);
28 if (len < sizeof(*val) * 2)
29 return -EINVAL;
30
31 /* Use unaligned access since cache is still disabled */
32 gd->ram_size = get_unaligned_be64(&val[1]);
33
34 return 0;
35 }
36
dram_init_banksize(void)37 int dram_init_banksize(void)
38 {
39 /* Reserve first 16 MiB of RAM for firmware */
40 gd->bd->bi_dram[0].start = 0x1000000;
41 gd->bd->bi_dram[0].size = 0xf000000;
42 /* Reserve 2 MiB for ARM Trusted Firmware (BL31) */
43 gd->bd->bi_dram[1].start = 0x10000000;
44 gd->bd->bi_dram[1].size = gd->ram_size - 0x10200000;
45 return 0;
46 }
47
reset_cpu(ulong addr)48 void reset_cpu(ulong addr)
49 {
50 psci_system_reset();
51 }
52
53 static struct mm_region gxbb_mem_map[] = {
54 {
55 .virt = 0x0UL,
56 .phys = 0x0UL,
57 .size = 0x80000000UL,
58 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
59 PTE_BLOCK_INNER_SHARE
60 }, {
61 .virt = 0x80000000UL,
62 .phys = 0x80000000UL,
63 .size = 0x80000000UL,
64 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
65 PTE_BLOCK_NON_SHARE |
66 PTE_BLOCK_PXN | PTE_BLOCK_UXN
67 }, {
68 /* List terminator */
69 0,
70 }
71 };
72
73 struct mm_region *mem_map = gxbb_mem_map;
74