1 /* 2 * linux/include/asm-arm/proc-armv/ptrace.h 3 * 4 * Copyright (C) 1996-1999 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #ifndef __ASM_PROC_PTRACE_H 11 #define __ASM_PROC_PTRACE_H 12 13 #ifdef CONFIG_ARM64 14 15 #define PCMASK 0 16 17 #ifndef __ASSEMBLY__ 18 19 /* 20 * This struct defines the way the registers are stored 21 * on the stack during an exception. 22 */ 23 struct pt_regs { 24 /* 25 * system register 26 * 27 * Note: never change order! see "_exception_entry" and "exception_exit" 28 */ 29 unsigned long ttbr0; 30 unsigned long hcr; /* hcr_el2/scr_el3 */ 31 unsigned long sctlr; 32 unsigned long sp; 33 unsigned long spsr; 34 unsigned long vbar; 35 unsigned long daif; 36 unsigned long esr; 37 38 unsigned long elr; 39 unsigned long regs[31]; 40 }; 41 42 #endif /* __ASSEMBLY__ */ 43 44 #else /* CONFIG_ARM64 */ 45 46 #define USR26_MODE 0x00 47 #define FIQ26_MODE 0x01 48 #define IRQ26_MODE 0x02 49 #define SVC26_MODE 0x03 50 #define USR_MODE 0x10 51 #define FIQ_MODE 0x11 52 #define IRQ_MODE 0x12 53 #define SVC_MODE 0x13 54 #define ABT_MODE 0x17 55 #define HYP_MODE 0x1a 56 #define UND_MODE 0x1b 57 #define SYSTEM_MODE 0x1f 58 #define MODE_MASK 0x1f 59 #define T_BIT 0x20 60 #define F_BIT 0x40 61 #define I_BIT 0x80 62 #define A_BIT 0x100 63 #define CC_V_BIT (1 << 28) 64 #define CC_C_BIT (1 << 29) 65 #define CC_Z_BIT (1 << 30) 66 #define CC_N_BIT (1 << 31) 67 #define PCMASK 0 68 69 #ifndef __ASSEMBLY__ 70 71 /* this struct defines the way the registers are stored on the 72 stack during a system call. */ 73 74 struct pt_regs { 75 long uregs[18]; 76 }; 77 78 #define ARM_cpsr uregs[16] 79 #define ARM_pc uregs[15] 80 #define ARM_lr uregs[14] 81 #define ARM_sp uregs[13] 82 #define ARM_ip uregs[12] 83 #define ARM_fp uregs[11] 84 #define ARM_r10 uregs[10] 85 #define ARM_r9 uregs[9] 86 #define ARM_r8 uregs[8] 87 #define ARM_r7 uregs[7] 88 #define ARM_r6 uregs[6] 89 #define ARM_r5 uregs[5] 90 #define ARM_r4 uregs[4] 91 #define ARM_r3 uregs[3] 92 #define ARM_r2 uregs[2] 93 #define ARM_r1 uregs[1] 94 #define ARM_r0 uregs[0] 95 #define ARM_ORIG_r0 uregs[17] 96 97 #ifdef __KERNEL__ 98 99 #define user_mode(regs) \ 100 (((regs)->ARM_cpsr & 0xf) == 0) 101 102 #ifdef CONFIG_ARM_THUMB 103 #define thumb_mode(regs) \ 104 (((regs)->ARM_cpsr & T_BIT)) 105 #else 106 #define thumb_mode(regs) (0) 107 #endif 108 109 #define processor_mode(regs) \ 110 ((regs)->ARM_cpsr & MODE_MASK) 111 112 #define interrupts_enabled(regs) \ 113 (!((regs)->ARM_cpsr & I_BIT)) 114 115 #define fast_interrupts_enabled(regs) \ 116 (!((regs)->ARM_cpsr & F_BIT)) 117 118 #define condition_codes(regs) \ 119 ((regs)->ARM_cpsr & (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT)) 120 121 /* Are the current registers suitable for user mode? 122 * (used to maintain security in signal handlers) 123 */ valid_user_regs(struct pt_regs * regs)124static inline int valid_user_regs(struct pt_regs *regs) 125 { 126 if ((regs->ARM_cpsr & 0xf) == 0 && 127 (regs->ARM_cpsr & (F_BIT|I_BIT)) == 0) 128 return 1; 129 130 /* 131 * Force CPSR to something logical... 132 */ 133 regs->ARM_cpsr &= (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT|0x10); 134 135 return 0; 136 } 137 138 #endif /* __KERNEL__ */ 139 140 #endif /* __ASSEMBLY__ */ 141 142 #endif /* CONFIG_ARM64 */ 143 144 #endif 145