1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef _ASM_ARCH_SDRAM_RK322X_H 7 #define _ASM_ARCH_SDRAM_RK322X_H 8 9 #include <common.h> 10 11 struct rk322x_sdram_channel { 12 /* 13 * bit width in address, eg: 14 * 8 banks using 3 bit to address, 15 * 2 cs using 1 bit to address. 16 */ 17 u8 rank; 18 u8 col; 19 u8 bk; 20 u8 bw; 21 u8 dbw; 22 u8 row_3_4; 23 u8 cs0_row; 24 u8 cs1_row; 25 #if CONFIG_IS_ENABLED(OF_PLATDATA) 26 /* 27 * For of-platdata, which would otherwise convert this into two 28 * byte-swapped integers. With a size of 9 bytes, this struct will 29 * appear in of-platdata as a byte array. 30 * 31 * If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff) 32 */ 33 u8 dummy; 34 #endif 35 }; 36 37 struct rk322x_ddr_pctl { 38 u32 scfg; 39 u32 sctl; 40 u32 stat; 41 u32 intrstat; 42 u32 reserved0[(0x40 - 0x10) / 4]; 43 u32 mcmd; 44 u32 powctl; 45 u32 powstat; 46 u32 cmdtstat; 47 u32 cmdtstaten; 48 u32 reserved1[(0x60 - 0x54) / 4]; 49 u32 mrrcfg0; 50 u32 mrrstat0; 51 u32 mrrstat1; 52 u32 reserved2[(0x7c - 0x6c) / 4]; 53 54 u32 mcfg1; 55 u32 mcfg; 56 u32 ppcfg; 57 u32 mstat; 58 u32 lpddr2zqcfg; 59 u32 reserved3; 60 61 u32 dtupdes; 62 u32 dtuna; 63 u32 dtune; 64 u32 dtuprd0; 65 u32 dtuprd1; 66 u32 dtuprd2; 67 u32 dtuprd3; 68 u32 dtuawdt; 69 u32 reserved4[(0xc0 - 0xb4) / 4]; 70 71 u32 togcnt1u; 72 u32 tinit; 73 u32 trsth; 74 u32 togcnt100n; 75 u32 trefi; 76 u32 tmrd; 77 u32 trfc; 78 u32 trp; 79 u32 trtw; 80 u32 tal; 81 u32 tcl; 82 u32 tcwl; 83 u32 tras; 84 u32 trc; 85 u32 trcd; 86 u32 trrd; 87 u32 trtp; 88 u32 twr; 89 u32 twtr; 90 u32 texsr; 91 u32 txp; 92 u32 txpdll; 93 u32 tzqcs; 94 u32 tzqcsi; 95 u32 tdqs; 96 u32 tcksre; 97 u32 tcksrx; 98 u32 tcke; 99 u32 tmod; 100 u32 trstl; 101 u32 tzqcl; 102 u32 tmrr; 103 u32 tckesr; 104 u32 tdpd; 105 u32 tref_mem_ddr3; 106 u32 reserved5[(0x180 - 0x14c) / 4]; 107 u32 ecccfg; 108 u32 ecctst; 109 u32 eccclr; 110 u32 ecclog; 111 u32 reserved6[(0x200 - 0x190) / 4]; 112 u32 dtuwactl; 113 u32 dturactl; 114 u32 dtucfg; 115 u32 dtuectl; 116 u32 dtuwd0; 117 u32 dtuwd1; 118 u32 dtuwd2; 119 u32 dtuwd3; 120 u32 dtuwdm; 121 u32 dturd0; 122 u32 dturd1; 123 u32 dturd2; 124 u32 dturd3; 125 u32 dtulfsrwd; 126 u32 dtulfsrrd; 127 u32 dtueaf; 128 /* dfi control registers */ 129 u32 dfitctrldelay; 130 u32 dfiodtcfg; 131 u32 dfiodtcfg1; 132 u32 dfiodtrankmap; 133 /* dfi write data registers */ 134 u32 dfitphywrdata; 135 u32 dfitphywrlat; 136 u32 reserved7[(0x260 - 0x258) / 4]; 137 u32 dfitrddataen; 138 u32 dfitphyrdlat; 139 u32 reserved8[(0x270 - 0x268) / 4]; 140 u32 dfitphyupdtype0; 141 u32 dfitphyupdtype1; 142 u32 dfitphyupdtype2; 143 u32 dfitphyupdtype3; 144 u32 dfitctrlupdmin; 145 u32 dfitctrlupdmax; 146 u32 dfitctrlupddly; 147 u32 reserved9; 148 u32 dfiupdcfg; 149 u32 dfitrefmski; 150 u32 dfitctrlupdi; 151 u32 reserved10[(0x2ac - 0x29c) / 4]; 152 u32 dfitrcfg0; 153 u32 dfitrstat0; 154 u32 dfitrwrlvlen; 155 u32 dfitrrdlvlen; 156 u32 dfitrrdlvlgateen; 157 u32 dfiststat0; 158 u32 dfistcfg0; 159 u32 dfistcfg1; 160 u32 reserved11; 161 u32 dfitdramclken; 162 u32 dfitdramclkdis; 163 u32 dfistcfg2; 164 u32 dfistparclr; 165 u32 dfistparlog; 166 u32 reserved12[(0x2f0 - 0x2e4) / 4]; 167 168 u32 dfilpcfg0; 169 u32 reserved13[(0x300 - 0x2f4) / 4]; 170 u32 dfitrwrlvlresp0; 171 u32 dfitrwrlvlresp1; 172 u32 dfitrwrlvlresp2; 173 u32 dfitrrdlvlresp0; 174 u32 dfitrrdlvlresp1; 175 u32 dfitrrdlvlresp2; 176 u32 dfitrwrlvldelay0; 177 u32 dfitrwrlvldelay1; 178 u32 dfitrwrlvldelay2; 179 u32 dfitrrdlvldelay0; 180 u32 dfitrrdlvldelay1; 181 u32 dfitrrdlvldelay2; 182 u32 dfitrrdlvlgatedelay0; 183 u32 dfitrrdlvlgatedelay1; 184 u32 dfitrrdlvlgatedelay2; 185 u32 dfitrcmd; 186 u32 reserved14[(0x3f8 - 0x340) / 4]; 187 u32 ipvr; 188 u32 iptr; 189 }; 190 check_member(rk322x_ddr_pctl, iptr, 0x03fc); 191 192 struct rk322x_ddr_phy { 193 u32 ddrphy_reg[0x100]; 194 }; 195 196 struct rk322x_pctl_timing { 197 u32 togcnt1u; 198 u32 tinit; 199 u32 trsth; 200 u32 togcnt100n; 201 u32 trefi; 202 u32 tmrd; 203 u32 trfc; 204 u32 trp; 205 u32 trtw; 206 u32 tal; 207 u32 tcl; 208 u32 tcwl; 209 u32 tras; 210 u32 trc; 211 u32 trcd; 212 u32 trrd; 213 u32 trtp; 214 u32 twr; 215 u32 twtr; 216 u32 texsr; 217 u32 txp; 218 u32 txpdll; 219 u32 tzqcs; 220 u32 tzqcsi; 221 u32 tdqs; 222 u32 tcksre; 223 u32 tcksrx; 224 u32 tcke; 225 u32 tmod; 226 u32 trstl; 227 u32 tzqcl; 228 u32 tmrr; 229 u32 tckesr; 230 u32 tdpd; 231 u32 trefi_mem_ddr3; 232 }; 233 234 struct rk322x_phy_timing { 235 u32 mr[4]; 236 u32 mr11; 237 u32 bl; 238 u32 cl_al; 239 }; 240 241 struct rk322x_msch_timings { 242 u32 ddrtiming; 243 u32 ddrmode; 244 u32 readlatency; 245 u32 activate; 246 u32 devtodev; 247 }; 248 249 struct rk322x_service_sys { 250 u32 id_coreid; 251 u32 id_revisionid; 252 u32 ddrconf; 253 u32 ddrtiming; 254 u32 ddrmode; 255 u32 readlatency; 256 u32 activate; 257 u32 devtodev; 258 }; 259 260 struct rk322x_base_params { 261 struct rk322x_msch_timings noc_timing; 262 u32 ddrconfig; 263 u32 ddr_freq; 264 u32 dramtype; 265 /* 266 * unused for rk322x 267 */ 268 u32 stride; 269 u32 odt; 270 }; 271 272 /* PCT_DFISTCFG0 */ 273 #define DFI_INIT_START (1 << 0) 274 #define DFI_DATA_BYTE_DISABLE_EN (1 << 2) 275 276 /* PCT_DFISTCFG1 */ 277 #define DFI_DRAM_CLK_SR_EN (1 << 0) 278 #define DFI_DRAM_CLK_DPD_EN (1 << 1) 279 280 /* PCT_DFISTCFG2 */ 281 #define DFI_PARITY_INTR_EN (1 << 0) 282 #define DFI_PARITY_EN (1 << 1) 283 284 /* PCT_DFILPCFG0 */ 285 #define TLP_RESP_TIME_SHIFT 16 286 #define LP_SR_EN (1 << 8) 287 #define LP_PD_EN (1 << 0) 288 289 /* PCT_DFITCTRLDELAY */ 290 #define TCTRL_DELAY_TIME_SHIFT 0 291 292 /* PCT_DFITPHYWRDATA */ 293 #define TPHY_WRDATA_TIME_SHIFT 0 294 295 /* PCT_DFITPHYRDLAT */ 296 #define TPHY_RDLAT_TIME_SHIFT 0 297 298 /* PCT_DFITDRAMCLKDIS */ 299 #define TDRAM_CLK_DIS_TIME_SHIFT 0 300 301 /* PCT_DFITDRAMCLKEN */ 302 #define TDRAM_CLK_EN_TIME_SHIFT 0 303 304 /* PCTL_DFIODTCFG */ 305 #define RANK0_ODT_WRITE_SEL (1 << 3) 306 #define RANK1_ODT_WRITE_SEL (1 << 11) 307 308 /* PCTL_DFIODTCFG1 */ 309 #define ODT_LEN_BL8_W_SHIFT 16 310 311 /* PUBL_ACDLLCR */ 312 #define ACDLLCR_DLLDIS (1 << 31) 313 #define ACDLLCR_DLLSRST (1 << 30) 314 315 /* PUBL_DXDLLCR */ 316 #define DXDLLCR_DLLDIS (1 << 31) 317 #define DXDLLCR_DLLSRST (1 << 30) 318 319 /* PUBL_DLLGCR */ 320 #define DLLGCR_SBIAS (1 << 30) 321 322 /* PUBL_DXGCR */ 323 #define DQSRTT (1 << 9) 324 #define DQRTT (1 << 10) 325 326 /* PIR */ 327 #define PIR_INIT (1 << 0) 328 #define PIR_DLLSRST (1 << 1) 329 #define PIR_DLLLOCK (1 << 2) 330 #define PIR_ZCAL (1 << 3) 331 #define PIR_ITMSRST (1 << 4) 332 #define PIR_DRAMRST (1 << 5) 333 #define PIR_DRAMINIT (1 << 6) 334 #define PIR_QSTRN (1 << 7) 335 #define PIR_RVTRN (1 << 8) 336 #define PIR_ICPC (1 << 16) 337 #define PIR_DLLBYP (1 << 17) 338 #define PIR_CTLDINIT (1 << 18) 339 #define PIR_CLRSR (1 << 28) 340 #define PIR_LOCKBYP (1 << 29) 341 #define PIR_ZCALBYP (1 << 30) 342 #define PIR_INITBYP (1u << 31) 343 344 /* PGCR */ 345 #define PGCR_DFTLMT_SHIFT 3 346 #define PGCR_DFTCMP_SHIFT 2 347 #define PGCR_DQSCFG_SHIFT 1 348 #define PGCR_ITMDMD_SHIFT 0 349 350 /* PGSR */ 351 #define PGSR_IDONE (1 << 0) 352 #define PGSR_DLDONE (1 << 1) 353 #define PGSR_ZCDONE (1 << 2) 354 #define PGSR_DIDONE (1 << 3) 355 #define PGSR_DTDONE (1 << 4) 356 #define PGSR_DTERR (1 << 5) 357 #define PGSR_DTIERR (1 << 6) 358 #define PGSR_DFTERR (1 << 7) 359 #define PGSR_RVERR (1 << 8) 360 #define PGSR_RVEIRR (1 << 9) 361 362 /* PTR0 */ 363 #define PRT_ITMSRST_SHIFT 18 364 #define PRT_DLLLOCK_SHIFT 6 365 #define PRT_DLLSRST_SHIFT 0 366 367 /* PTR1 */ 368 #define PRT_DINIT0_SHIFT 0 369 #define PRT_DINIT1_SHIFT 19 370 371 /* PTR2 */ 372 #define PRT_DINIT2_SHIFT 0 373 #define PRT_DINIT3_SHIFT 17 374 375 /* DCR */ 376 #define DDRMD_LPDDR 0 377 #define DDRMD_DDR 1 378 #define DDRMD_DDR2 2 379 #define DDRMD_DDR3 3 380 #define DDRMD_LPDDR2_LPDDR3 4 381 #define DDRMD_MASK 7 382 #define DDRMD_SHIFT 0 383 #define PDQ_MASK 7 384 #define PDQ_SHIFT 4 385 386 /* DXCCR */ 387 #define DQSNRES_MASK 0xf 388 #define DQSNRES_SHIFT 8 389 #define DQSRES_MASK 0xf 390 #define DQSRES_SHIFT 4 391 392 /* DTPR */ 393 #define TDQSCKMAX_SHIFT 27 394 #define TDQSCKMAX_MASK 7 395 #define TDQSCK_SHIFT 24 396 #define TDQSCK_MASK 7 397 398 /* DSGCR */ 399 #define DQSGX_SHIFT 5 400 #define DQSGX_MASK 7 401 #define DQSGE_SHIFT 8 402 #define DQSGE_MASK 7 403 404 /* SCTL */ 405 #define INIT_STATE 0 406 #define CFG_STATE 1 407 #define GO_STATE 2 408 #define SLEEP_STATE 3 409 #define WAKEUP_STATE 4 410 411 /* STAT */ 412 #define LP_TRIG_SHIFT 4 413 #define LP_TRIG_MASK 7 414 #define PCTL_STAT_MASK 7 415 #define INIT_MEM 0 416 #define CONFIG 1 417 #define CONFIG_REQ 2 418 #define ACCESS 3 419 #define ACCESS_REQ 4 420 #define LOW_POWER 5 421 #define LOW_POWER_ENTRY_REQ 6 422 #define LOW_POWER_EXIT_REQ 7 423 424 /* ZQCR*/ 425 #define PD_OUTPUT_SHIFT 0 426 #define PU_OUTPUT_SHIFT 5 427 #define PD_ONDIE_SHIFT 10 428 #define PU_ONDIE_SHIFT 15 429 #define ZDEN_SHIFT 28 430 431 /* DDLGCR */ 432 #define SBIAS_BYPASS (1 << 23) 433 434 /* MCFG */ 435 #define MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT 24 436 #define PD_IDLE_SHIFT 8 437 #define MDDR_EN (2 << 22) 438 #define LPDDR2_EN (3 << 22) 439 #define LPDDR3_EN (1 << 22) 440 #define DDR2_EN (0 << 5) 441 #define DDR3_EN (1 << 5) 442 #define LPDDR2_S2 (0 << 6) 443 #define LPDDR2_S4 (1 << 6) 444 #define MDDR_LPDDR2_BL_2 (0 << 20) 445 #define MDDR_LPDDR2_BL_4 (1 << 20) 446 #define MDDR_LPDDR2_BL_8 (2 << 20) 447 #define MDDR_LPDDR2_BL_16 (3 << 20) 448 #define DDR2_DDR3_BL_4 0 449 #define DDR2_DDR3_BL_8 1 450 #define TFAW_SHIFT 18 451 #define PD_EXIT_SLOW (0 << 17) 452 #define PD_EXIT_FAST (1 << 17) 453 #define PD_TYPE_SHIFT 16 454 #define BURSTLENGTH_SHIFT 20 455 456 /* POWCTL */ 457 #define POWER_UP_START (1 << 0) 458 459 /* POWSTAT */ 460 #define POWER_UP_DONE (1 << 0) 461 462 /* MCMD */ 463 enum { 464 DESELECT_CMD = 0, 465 PREA_CMD, 466 REF_CMD, 467 MRS_CMD, 468 ZQCS_CMD, 469 ZQCL_CMD, 470 RSTL_CMD, 471 MRR_CMD = 8, 472 DPDE_CMD, 473 }; 474 475 #define BANK_ADDR_MASK 7 476 #define BANK_ADDR_SHIFT 17 477 #define CMD_ADDR_MASK 0x1fff 478 #define CMD_ADDR_SHIFT 4 479 480 #define LPDDR23_MA_SHIFT 4 481 #define LPDDR23_MA_MASK 0xff 482 #define LPDDR23_OP_SHIFT 12 483 #define LPDDR23_OP_MASK 0xff 484 485 #define START_CMD (1u << 31) 486 487 /* DDRPHY REG */ 488 enum { 489 /* DDRPHY_REG0 */ 490 SOFT_RESET_MASK = 3, 491 SOFT_DERESET_ANALOG = 1 << 2, 492 SOFT_DERESET_DIGITAL = 1 << 3, 493 SOFT_RESET_SHIFT = 2, 494 495 /* DDRPHY REG1 */ 496 PHY_DDR3 = 0, 497 PHY_DDR2 = 1, 498 PHY_LPDDR3 = 2, 499 PHY_LPDDR2 = 3, 500 501 PHT_BL_8 = 1 << 2, 502 PHY_BL_4 = 0 << 2, 503 504 /* DDRPHY_REG2 */ 505 MEMORY_SELECT_DDR3 = 0 << 0, 506 MEMORY_SELECT_LPDDR3 = 2 << 0, 507 MEMORY_SELECT_LPDDR2 = 3 << 0, 508 DQS_SQU_CAL_SEL_CS0_CS1 = 0 << 4, 509 DQS_SQU_CAL_SEL_CS1 = 1 << 4, 510 DQS_SQU_CAL_SEL_CS0 = 2 << 4, 511 DQS_SQU_CAL_NORMAL_MODE = 0 << 1, 512 DQS_SQU_CAL_BYPASS_MODE = 1 << 1, 513 DQS_SQU_CAL_START = 1 << 0, 514 DQS_SQU_NO_CAL = 0 << 0, 515 }; 516 517 /* CK pull up/down driver strength control */ 518 enum { 519 PHY_RON_RTT_DISABLE = 0, 520 PHY_RON_RTT_451OHM = 1, 521 PHY_RON_RTT_225OHM, 522 PHY_RON_RTT_150OHM, 523 PHY_RON_RTT_112OHM, 524 PHY_RON_RTT_90OHM, 525 PHY_RON_RTT_75OHM, 526 PHY_RON_RTT_64OHM = 7, 527 528 PHY_RON_RTT_56OHM = 16, 529 PHY_RON_RTT_50OHM, 530 PHY_RON_RTT_45OHM, 531 PHY_RON_RTT_41OHM, 532 PHY_RON_RTT_37OHM, 533 PHY_RON_RTT_34OHM, 534 PHY_RON_RTT_33OHM, 535 PHY_RON_RTT_30OHM = 23, 536 537 PHY_RON_RTT_28OHM = 24, 538 PHY_RON_RTT_26OHM, 539 PHY_RON_RTT_25OHM, 540 PHY_RON_RTT_23OHM, 541 PHY_RON_RTT_22OHM, 542 PHY_RON_RTT_21OHM, 543 PHY_RON_RTT_20OHM, 544 PHY_RON_RTT_19OHM = 31, 545 }; 546 547 /* DQS squelch DLL delay */ 548 enum { 549 DQS_DLL_NO_DELAY = 0, 550 DQS_DLL_22P5_DELAY, 551 DQS_DLL_45_DELAY, 552 DQS_DLL_67P5_DELAY, 553 DQS_DLL_90_DELAY, 554 DQS_DLL_112P5_DELAY, 555 DQS_DLL_135_DELAY, 556 DQS_DLL_157P5_DELAY, 557 }; 558 559 /* GRF_SOC_CON0 */ 560 #define GRF_DDR_16BIT_EN (((0x1 << 0) << 16) | (0x1 << 0)) 561 #define GRF_DDR_32BIT_EN (((0x1 << 0) << 16) | (0x0 << 0)) 562 #define GRF_MSCH_NOC_16BIT_EN (((0x1 << 7) << 16) | (0x1 << 7)) 563 #define GRF_MSCH_NOC_32BIT_EN (((0x1 << 7) << 16) | (0x0 << 7)) 564 565 #define GRF_DDRPHY_BUFFEREN_CORE_EN (((0x1 << 8) << 16) | (0x0 << 8)) 566 #define GRF_DDRPHY_BUFFEREN_CORE_DIS (((0x1 << 8) << 16) | (0x1 << 8)) 567 568 #define GRF_DDR3_EN (((0x1 << 6) << 16) | (0x1 << 6)) 569 #define GRF_LPDDR2_3_EN (((0x1 << 6) << 16) | (0x0 << 6)) 570 571 #define PHY_DRV_ODT_SET(n) (((n) << 4) | (n)) 572 #define DDR3_DLL_RESET (1 << 8) 573 574 #endif /* _ASM_ARCH_SDRAM_RK322X_H */ 575