1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2020 Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _ASM_ARCH_PMU_RK3308_H 7*4882a593Smuzhiyun #define _ASM_ARCH_PMU_RK3308_H 8*4882a593Smuzhiyun struct rk3308_pmu { 9*4882a593Smuzhiyun u32 reserved0[4]; 10*4882a593Smuzhiyun u32 wakeup_cfg2_lo; 11*4882a593Smuzhiyun u32 reserved1; 12*4882a593Smuzhiyun u32 pwrdn_con_lo; 13*4882a593Smuzhiyun u32 reserved2; 14*4882a593Smuzhiyun u32 pwrdn_st; 15*4882a593Smuzhiyun u32 pwrmode_core_con_lo; 16*4882a593Smuzhiyun u32 reserved3; 17*4882a593Smuzhiyun u32 pwrmode_common_con_lo; 18*4882a593Smuzhiyun u32 pwrmode_common_con_hi; 19*4882a593Smuzhiyun u32 sft_con_lo; 20*4882a593Smuzhiyun u32 sft_con_hi; 21*4882a593Smuzhiyun u32 int_con_lo; 22*4882a593Smuzhiyun u32 int_con_hi; 23*4882a593Smuzhiyun u32 int_st; 24*4882a593Smuzhiyun u32 reserved4[6]; 25*4882a593Smuzhiyun u32 core_pwr_st; 26*4882a593Smuzhiyun u32 bus_idle_req_lo; 27*4882a593Smuzhiyun u32 reserved5; 28*4882a593Smuzhiyun u32 bus_idle_st; 29*4882a593Smuzhiyun u32 power_st; 30*4882a593Smuzhiyun u32 osc_cnt_lo; 31*4882a593Smuzhiyun u32 osc_cnt_hi; 32*4882a593Smuzhiyun u32 plllock_cnt_lo; 33*4882a593Smuzhiyun u32 plllock_cnt_hi; 34*4882a593Smuzhiyun u32 pllrst_cnt_lo; 35*4882a593Smuzhiyun u32 pllrst_cnt_hi; 36*4882a593Smuzhiyun u32 reserved6[2]; 37*4882a593Smuzhiyun u32 ddrio_pwron_cnt_lo; 38*4882a593Smuzhiyun u32 ddrio_pwron_cnt_hi; 39*4882a593Smuzhiyun u32 wakeup_rst_clr_cnt_lo; 40*4882a593Smuzhiyun u32 wakeup_rst_clr_cnt_hi; 41*4882a593Smuzhiyun u32 ddr_sref_st; 42*4882a593Smuzhiyun u32 sys_reg0_lo; 43*4882a593Smuzhiyun u32 sys_reg0_hi; 44*4882a593Smuzhiyun u32 sys_reg1_lo; 45*4882a593Smuzhiyun u32 sys_reg1_hi; 46*4882a593Smuzhiyun u32 sys_reg2_lo; 47*4882a593Smuzhiyun u32 sys_reg2_hi; 48*4882a593Smuzhiyun u32 sys_reg3_lo; 49*4882a593Smuzhiyun u32 sys_reg3_hi; 50*4882a593Smuzhiyun u32 scu_pwrdn_cnt_lo; 51*4882a593Smuzhiyun u32 scu_pwrdn_cnt_hi; 52*4882a593Smuzhiyun u32 scu_pwrup_cnt_lo; 53*4882a593Smuzhiyun u32 scu_pwrup_cnt_hi; 54*4882a593Smuzhiyun u32 timeout_cnt_lo; 55*4882a593Smuzhiyun u32 timeout_cnt_hi; 56*4882a593Smuzhiyun u32 cpu0apm_con_lo; 57*4882a593Smuzhiyun u32 cpu1apm_con_lo; 58*4882a593Smuzhiyun u32 cpu2apm_con_lo; 59*4882a593Smuzhiyun u32 cpu3apm_con_lo; 60*4882a593Smuzhiyun u32 info_tx_con_lo; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun check_member(rk3308_pmu, info_tx_con_lo, 0x00f0); 64*4882a593Smuzhiyun enum { /* SFT_CON_LO */ 65*4882a593Smuzhiyun DDR_IO_RET_CFG_SHIFT = 8, 66*4882a593Smuzhiyun DDR_IO_RET_CFG_MASK = 1 << DDR_IO_RET_CFG_SHIFT, 67*4882a593Smuzhiyun DDR_IO_RET_CFG = 0, 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #endif 71