1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2020 Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef _ASM_ARCH_PMU_RK3308_H 7 #define _ASM_ARCH_PMU_RK3308_H 8 struct rk3308_pmu { 9 u32 reserved0[4]; 10 u32 wakeup_cfg2_lo; 11 u32 reserved1; 12 u32 pwrdn_con_lo; 13 u32 reserved2; 14 u32 pwrdn_st; 15 u32 pwrmode_core_con_lo; 16 u32 reserved3; 17 u32 pwrmode_common_con_lo; 18 u32 pwrmode_common_con_hi; 19 u32 sft_con_lo; 20 u32 sft_con_hi; 21 u32 int_con_lo; 22 u32 int_con_hi; 23 u32 int_st; 24 u32 reserved4[6]; 25 u32 core_pwr_st; 26 u32 bus_idle_req_lo; 27 u32 reserved5; 28 u32 bus_idle_st; 29 u32 power_st; 30 u32 osc_cnt_lo; 31 u32 osc_cnt_hi; 32 u32 plllock_cnt_lo; 33 u32 plllock_cnt_hi; 34 u32 pllrst_cnt_lo; 35 u32 pllrst_cnt_hi; 36 u32 reserved6[2]; 37 u32 ddrio_pwron_cnt_lo; 38 u32 ddrio_pwron_cnt_hi; 39 u32 wakeup_rst_clr_cnt_lo; 40 u32 wakeup_rst_clr_cnt_hi; 41 u32 ddr_sref_st; 42 u32 sys_reg0_lo; 43 u32 sys_reg0_hi; 44 u32 sys_reg1_lo; 45 u32 sys_reg1_hi; 46 u32 sys_reg2_lo; 47 u32 sys_reg2_hi; 48 u32 sys_reg3_lo; 49 u32 sys_reg3_hi; 50 u32 scu_pwrdn_cnt_lo; 51 u32 scu_pwrdn_cnt_hi; 52 u32 scu_pwrup_cnt_lo; 53 u32 scu_pwrup_cnt_hi; 54 u32 timeout_cnt_lo; 55 u32 timeout_cnt_hi; 56 u32 cpu0apm_con_lo; 57 u32 cpu1apm_con_lo; 58 u32 cpu2apm_con_lo; 59 u32 cpu3apm_con_lo; 60 u32 info_tx_con_lo; 61 }; 62 63 check_member(rk3308_pmu, info_tx_con_lo, 0x00f0); 64 enum { /* SFT_CON_LO */ 65 DDR_IO_RET_CFG_SHIFT = 8, 66 DDR_IO_RET_CFG_MASK = 1 << DDR_IO_RET_CFG_SHIFT, 67 DDR_IO_RET_CFG = 0, 68 }; 69 70 #endif 71