1 /* 2 * Copyright (c) 2017 Paweł Jarosz <paweljarosz3691@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef _ASM_ARCH_GRF_RK3066_H 8 #define _ASM_ARCH_GRF_RK3066_H 9 10 struct rk3066_grf_gpio_lh { 11 u32 l; 12 u32 h; 13 }; 14 15 struct rk3066_grf { 16 struct rk3066_grf_gpio_lh gpio_dir[7]; 17 struct rk3066_grf_gpio_lh gpio_do[7]; 18 struct rk3066_grf_gpio_lh gpio_en[7]; 19 20 u32 gpio0a_iomux; 21 u32 gpio0b_iomux; 22 u32 gpio0c_iomux; 23 u32 gpio0d_iomux; 24 25 u32 gpio1a_iomux; 26 u32 gpio1b_iomux; 27 u32 gpio1c_iomux; 28 u32 gpio1d_iomux; 29 30 u32 gpio2a_iomux; 31 u32 gpio2b_iomux; 32 u32 gpio2c_iomux; 33 u32 gpio2d_iomux; 34 35 u32 gpio3a_iomux; 36 u32 gpio3b_iomux; 37 u32 gpio3c_iomux; 38 u32 gpio3d_iomux; 39 40 u32 gpio4a_iomux; 41 u32 gpio4b_iomux; 42 u32 gpio4c_iomux; 43 u32 gpio4d_iomux; 44 45 u32 reserved0[5]; 46 47 u32 gpio6b_iomux; 48 49 u32 reserved1[2]; 50 51 struct rk3066_grf_gpio_lh gpio_pull[7]; 52 53 u32 soc_con0; 54 u32 soc_con1; 55 u32 soc_con2; 56 57 u32 soc_status0; 58 59 u32 dmac1_con[3]; 60 u32 dmac2_con[4]; 61 62 u32 uoc0_con[3]; 63 u32 uoc1_con[4]; 64 u32 ddrc_con; 65 u32 ddrc_stat; 66 67 u32 reserved2[10]; 68 69 u32 os_reg[4]; 70 }; 71 check_member(rk3066_grf, os_reg[3], 0x01d4); 72 73 /* GRF_GPIO0A_IOMUX */ 74 enum { 75 GPIO0A6_SHIFT = 12, 76 GPIO0A6_MASK = 1 << GPIO0A6_SHIFT, 77 GPIO0A6_GPIO = 0, 78 GPIO0A6_HOST_DRV_VBUS, 79 80 GPIO0A5_SHIFT = 10, 81 GPIO0A5_MASK = 1 << GPIO0A5_SHIFT, 82 GPIO0A5_GPIO = 0, 83 GPIO0A5_OTG_DRV_VBUS, 84 85 GPIO0A4_SHIFT = 8, 86 GPIO0A4_MASK = 1 << GPIO0A4_SHIFT, 87 GPIO0A4_GPIO = 0, 88 GPIO0A4_PWM1, 89 90 GPIO0A3_SHIFT = 6, 91 GPIO0A3_MASK = 1 << GPIO0A3_SHIFT, 92 GPIO0A3_GPIO = 0, 93 GPIO0A3_PWM0 94 }; 95 96 /* GRF_GPIO0D_IOMUX */ 97 enum { 98 GPIO0D7_SHIFT = 14, 99 GPIO0D7_MASK = 1 << GPIO0D7_SHIFT, 100 GPIO0D7_GPIO = 0, 101 GPIO0D7_PWM3, 102 103 GPIO0D6_SHIFT = 12, 104 GPIO0D6_MASK = 1 << GPIO0D6_SHIFT, 105 GPIO0D6_GPIO = 0, 106 GPIO0D6_PWM2 107 }; 108 109 /* GRF_GPIO1A_IOMUX */ 110 enum { 111 GPIO1A7_SHIFT = 14, 112 GPIO1A7_MASK = 3 << GPIO1A7_SHIFT, 113 GPIO1A7_GPIO = 0, 114 GPIO1A7_UART1_RTS_N, 115 GPIO1A7_SPI0_TXD, 116 117 GPIO1A6_SHIFT = 12, 118 GPIO1A6_MASK = 3 << GPIO1A6_SHIFT, 119 GPIO1A6_GPIO = 0, 120 GPIO1A6_UART1_CTS_N, 121 GPIO1A6_SPI0_RXD, 122 123 GPIO1A5_SHIFT = 10, 124 GPIO1A5_MASK = 3 << GPIO1A5_SHIFT, 125 GPIO1A5_GPIO = 0, 126 GPIO1A5_UART1_SOUT, 127 GPIO1A5_SPI0_CLK, 128 129 GPIO1A4_SHIFT = 8, 130 GPIO1A4_MASK = 3 << GPIO1A4_SHIFT, 131 GPIO1A4_GPIO = 0, 132 GPIO1A4_UART1_SIN, 133 GPIO1A4_SPI0_CSN0, 134 135 GPIO1A3_SHIFT = 6, 136 GPIO1A3_MASK = 1 << GPIO1A3_SHIFT, 137 GPIO1A3_GPIO = 0, 138 GPIO1A3_UART0_RTS_N, 139 140 GPIO1A2_SHIFT = 4, 141 GPIO1A2_MASK = 1 << GPIO1A2_SHIFT, 142 GPIO1A2_GPIO = 0, 143 GPIO1A2_UART0_CTS_N, 144 145 GPIO1A1_SHIFT = 2, 146 GPIO1A1_MASK = 1 << GPIO1A1_SHIFT, 147 GPIO1A1_GPIO = 0, 148 GPIO1A1_UART0_SOUT, 149 150 GPIO1A0_SHIFT = 0, 151 GPIO1A0_MASK = 1 << GPIO1A0_SHIFT, 152 GPIO1A0_GPIO = 0, 153 GPIO1A0_UART0_SIN 154 }; 155 156 /* GRF_GPIO1B_IOMUX */ 157 enum { 158 GPIO1B1_SHIFT = 2, 159 GPIO1B1_MASK = 1 << GPIO1B1_SHIFT, 160 GPIO1B1_GPIO = 0, 161 GPIO1B1_UART2_SOUT, 162 163 GPIO1B0_SHIFT = 0, 164 GPIO1B0_MASK = 1 << GPIO1B0_SHIFT, 165 GPIO1B0_GPIO = 0, 166 GPIO1B0_UART2_SIN 167 }; 168 169 /* GRF_GPIO2C_IOMUX */ 170 enum { 171 GPIO2C7_SHIFT = 14, 172 GPIO2C7_MASK = 3 << GPIO2C7_SHIFT, 173 GPIO2C7_GPIO = 0, 174 GPIO2C7_LCDC1_DATA23, 175 GPIO2C7_SPI1_CSN1, 176 GPIO2C7_HSADC_DATA4, 177 178 GPIO2C6_SHIFT = 12, 179 GPIO2C6_MASK = 3 << GPIO2C6_SHIFT, 180 GPIO2C6_GPIO = 0, 181 GPIO2C6_LCDC1_DATA22, 182 GPIO2C6_SPI1_RXD, 183 GPIO2C6_HSADC_DATA3, 184 185 GPIO2C5_SHIFT = 10, 186 GPIO2C5_MASK = 3 << GPIO2C5_SHIFT, 187 GPIO2C5_GPIO = 0, 188 GPIO2C5_LCDC1_DATA21, 189 GPIO2C5_SPI1_TXD, 190 GPIO2C5_HSADC_DATA2, 191 192 GPIO2C4_SHIFT = 8, 193 GPIO2C4_MASK = 3 << GPIO2C4_SHIFT, 194 GPIO2C4_GPIO = 0, 195 GPIO2C4_LCDC1_DATA20, 196 GPIO2C4_SPI1_CSN0, 197 GPIO2C4_HSADC_DATA1, 198 199 GPIO2C3_SHIFT = 6, 200 GPIO2C3_MASK = 3 << GPIO2C3_SHIFT, 201 GPIO2C3_GPIO = 0, 202 GPIO2C3_LCDC1_DATA19, 203 GPIO2C3_SPI1_CLK, 204 GPIO2C3_HSADC_DATA0 205 }; 206 207 /* GRF_GPIO2D_IOMUX */ 208 enum { 209 GPIO2D7_SHIFT = 14, 210 GPIO2D7_MASK = 1 << GPIO2D7_SHIFT, 211 GPIO2D7_GPIO = 0, 212 GPIO2D7_I2C1_SCL, 213 214 GPIO2D6_SHIFT = 12, 215 GPIO2D6_MASK = 1 << GPIO2D6_SHIFT, 216 GPIO2D6_GPIO = 0, 217 GPIO2D6_I2C1_SDA, 218 219 GPIO2D5_SHIFT = 10, 220 GPIO2D5_MASK = 1 << GPIO2D5_SHIFT, 221 GPIO2D5_GPIO = 0, 222 GPIO2D5_I2C0_SCL, 223 224 GPIO2D4_SHIFT = 8, 225 GPIO2D4_MASK = 1 << GPIO2D4_SHIFT, 226 GPIO2D4_GPIO = 0, 227 GPIO2D4_I2C0_SDA 228 229 }; 230 231 /* GRF_GPIO3A_IOMUX */ 232 enum { 233 GPIO3A7_SHIFT = 14, 234 GPIO3A7_MASK = 1 << GPIO3A7_SHIFT, 235 GPIO3A7_GPIO = 0, 236 GPIO3A7_SDMMC0_WRITE_PRT, 237 238 GPIO3A6_SHIFT = 12, 239 GPIO3A6_MASK = 1 << GPIO3A6_SHIFT, 240 GPIO3A6_GPIO = 0, 241 GPIO3A6_SDMMC0_RSTN_OUT, 242 243 GPIO3A5_SHIFT = 10, 244 GPIO3A5_MASK = 1 << GPIO3A5_SHIFT, 245 GPIO3A5_GPIO = 0, 246 GPIO3A5_I2C4_SCL, 247 248 GPIO3A4_SHIFT = 8, 249 GPIO3A4_MASK = 1 << GPIO3A4_SHIFT, 250 GPIO3A4_GPIO = 0, 251 GPIO3A4_I2C4_SDA, 252 253 GPIO3A3_SHIFT = 6, 254 GPIO3A3_MASK = 1 << GPIO3A3_SHIFT, 255 GPIO3A3_GPIO = 0, 256 GPIO3A3_I2C3_SCL, 257 258 GPIO3A2_SHIFT = 4, 259 GPIO3A2_MASK = 1 << GPIO3A2_SHIFT, 260 GPIO3A2_GPIO = 0, 261 GPIO3A2_I2C3_SDA, 262 263 GPIO3A1_SHIFT = 2, 264 GPIO3A1_MASK = 1 << GPIO3A1_SHIFT, 265 GPIO3A1_GPIO = 0, 266 GPIO3A1_I2C2_SCL, 267 268 GPIO3A0_SHIFT = 0, 269 GPIO3A0_MASK = 1 << GPIO3A0_SHIFT, 270 GPIO3A0_GPIO = 0, 271 GPIO3A0_I2C2_SDA, 272 }; 273 274 /* GRF_GPIO3B_IOMUX */ 275 enum { 276 GPIO3B7_SHIFT = 14, 277 GPIO3B7_MASK = 1 << GPIO3B7_SHIFT, 278 GPIO3B7_GPIO = 0, 279 GPIO3B7_SDMMC0_WRITE_PRT, 280 281 GPIO3B6_SHIFT = 12, 282 GPIO3B6_MASK = 1 << GPIO3B6_SHIFT, 283 GPIO3B6_GPIO = 0, 284 GPIO3B6_SDMMC0_DETECT_N, 285 286 GPIO3B5_SHIFT = 10, 287 GPIO3B5_MASK = 1 << GPIO3B5_SHIFT, 288 GPIO3B5_GPIO = 0, 289 GPIO3B5_SDMMC0_DATA3, 290 291 GPIO3B4_SHIFT = 8, 292 GPIO3B4_MASK = 1 << GPIO3B4_SHIFT, 293 GPIO3B4_GPIO = 0, 294 GPIO3B4_SDMMC0_DATA2, 295 296 GPIO3B3_SHIFT = 6, 297 GPIO3B3_MASK = 1 << GPIO3B3_SHIFT, 298 GPIO3B3_GPIO = 0, 299 GPIO3B3_SDMMC0_DATA1, 300 301 GPIO3B2_SHIFT = 4, 302 GPIO3B2_MASK = 1 << GPIO3B2_SHIFT, 303 GPIO3B2_GPIO = 0, 304 GPIO3B2_SDMMC0_DATA0, 305 306 GPIO3B1_SHIFT = 2, 307 GPIO3B1_MASK = 1 << GPIO3B1_SHIFT, 308 GPIO3B1_GPIO = 0, 309 GPIO3B1_SDMMC0_CMD, 310 311 GPIO3B0_SHIFT = 0, 312 GPIO3B0_MASK = 1 << GPIO3B0_SHIFT, 313 GPIO3B0_GPIO = 0, 314 GPIO3B0_SDMMC0_CLKOUT 315 316 }; 317 318 /* GRF_GPIO3C_IOMUX */ 319 enum { 320 GPIO3C7_SHIFT = 14, 321 GPIO3C7_MASK = 1 << GPIO3C7_SHIFT, 322 GPIO3C7_GPIO = 0, 323 GPIO3C7_SDMMC1_WRITE_PRT, 324 325 GPIO3C6_SHIFT = 12, 326 GPIO3C6_MASK = 1 << GPIO3C6_SHIFT, 327 GPIO3C6_GPIO = 0, 328 GPIO3C6_SDMMC1_DETECT_N, 329 330 GPIO3C5_SHIFT = 10, 331 GPIO3C5_MASK = 1 << GPIO3C5_SHIFT, 332 GPIO3C5_GPIO = 0, 333 GPIO3C5_SDMMC1_CLKOUT, 334 335 GPIO3C4_SHIFT = 8, 336 GPIO3C4_MASK = 1 << GPIO3C4_SHIFT, 337 GPIO3C4_GPIO = 0, 338 GPIO3C4_SDMMC1_DATA3, 339 340 GPIO3C3_SHIFT = 6, 341 GPIO3C3_MASK = 1 << GPIO3C3_SHIFT, 342 GPIO3C3_GPIO = 0, 343 GPIO3C3_SDMMC1_DATA2, 344 345 GPIO3C2_SHIFT = 4, 346 GPIO3C2_MASK = 1 << GPIO3C2_SHIFT, 347 GPIO3C2_GPIO = 0, 348 GPIO3C2_SDMMC1_DATA1, 349 350 GPIO3C1_SHIFT = 2, 351 GPIO3C1_MASK = 1 << GPIO3C1_SHIFT, 352 GPIO3C1_GPIO = 0, 353 GPIO3C1_SDMMC1_DATA0, 354 355 GPIO3C0_SHIFT = 0, 356 GPIO3C0_MASK = 1 << GPIO3C0_SHIFT, 357 GPIO3C0_GPIO = 0, 358 GPIO3C0_SMMC1_CMD 359 }; 360 361 /* GRF_GPIO3D_IOMUX */ 362 enum { 363 GPIO3D7_SHIFT = 14, 364 GPIO3D7_MASK = 3 << GPIO3D7_SHIFT, 365 GPIO3D7_GPIO = 0, 366 GPIO3D7_FLASH_DQS, 367 GPIO3D7_EMMC_CLKOUT, 368 369 GPIO3D6_SHIFT = 12, 370 GPIO3D6_MASK = 1 << GPIO3D6_SHIFT, 371 GPIO3D6_GPIO = 0, 372 GPIO3D6_UART3_RTS_N, 373 374 GPIO3D5_SHIFT = 10, 375 GPIO3D5_MASK = 1 << GPIO3D5_SHIFT, 376 GPIO3D5_GPIO = 0, 377 GPIO3D5_UART3_CTS_N, 378 379 GPIO3D4_SHIFT = 8, 380 GPIO3D4_MASK = 1 << GPIO3D4_SHIFT, 381 GPIO3D4_GPIO = 0, 382 GPIO3D4_UART3_SOUT, 383 384 GPIO3D3_SHIFT = 6, 385 GPIO3D3_MASK = 1 << GPIO3D3_SHIFT, 386 GPIO3D3_GPIO = 0, 387 GPIO3D3_UART3_SIN, 388 389 GPIO3D2_SHIFT = 4, 390 GPIO3D2_MASK = 1 << GPIO3D2_SHIFT, 391 GPIO3D2_GPIO = 0, 392 GPIO3D2_SDMMC1_INT_N, 393 394 GPIO3D1_SHIFT = 2, 395 GPIO3D1_MASK = 1 << GPIO3D1_SHIFT, 396 GPIO3D1_GPIO = 0, 397 GPIO3D1_SDMMC1_BACKEND_PWR, 398 399 GPIO3D0_SHIFT = 0, 400 GPIO3D0_MASK = 1 << GPIO3D0_SHIFT, 401 GPIO3D0_GPIO = 0, 402 GPIO3D0_SDMMC1_PWR_EN 403 404 }; 405 406 /* GRF_GPIO4A_IOMUX */ 407 enum { 408 GPIO4A7_SHIFT = 14, 409 GPIO4A7_MASK = 1 << GPIO4A7_SHIFT, 410 GPIO4A7_GPIO = 0, 411 GPIO4A7_FLASH_DATA15, 412 413 GPIO4A6_SHIFT = 12, 414 GPIO4A6_MASK = 1 << GPIO4A6_SHIFT, 415 GPIO4A6_GPIO = 0, 416 GPIO4A6_FLASH_DATA14, 417 418 GPIO4A5_SHIFT = 10, 419 GPIO4A5_MASK = 1 << GPIO4A5_SHIFT, 420 GPIO4A5_GPIO = 0, 421 GPIO4A5_FLASH_DATA13, 422 423 GPIO4A4_SHIFT = 8, 424 GPIO4A4_MASK = 1 << GPIO4A4_SHIFT, 425 GPIO4A4_GPIO = 0, 426 GPIO4A4_FLASH_DATA12, 427 428 GPIO4A3_SHIFT = 6, 429 GPIO4A3_MASK = 1 << GPIO4A3_SHIFT, 430 GPIO4A3_GPIO = 0, 431 GPIO4A3_FLASH_DATA11, 432 433 GPIO4A2_SHIFT = 4, 434 GPIO4A2_MASK = 1 << GPIO4A2_SHIFT, 435 GPIO4A2_GPIO = 0, 436 GPIO4A2_FLASH_DATA10, 437 438 GPIO4A1_SHIFT = 2, 439 GPIO4A1_MASK = 1 << GPIO4A1_SHIFT, 440 GPIO4A1_GPIO = 0, 441 GPIO4A1_FLASH_DATA9, 442 443 GPIO4A0_SHIFT = 0, 444 GPIO4A0_MASK = 1 << GPIO4A0_SHIFT, 445 GPIO4A0_GPIO = 0, 446 GPIO4A0_FLASH_DATA8 447 448 }; 449 450 /* GRF_GPIO4B_IOMUX */ 451 enum { 452 GPIO4B7_SHIFT = 14, 453 GPIO4B7_MASK = 1 << GPIO4B7_SHIFT, 454 GPIO4B7_GPIO = 0, 455 GPIO4B7_SPI0_CSN1, 456 457 GPIO4B6_SHIFT = 12, 458 GPIO4B6_MASK = 1 << GPIO4B6_SHIFT, 459 GPIO4B6_GPIO = 0, 460 GPIO4B6_FLASH_CSN7, 461 462 GPIO4B5_SHIFT = 10, 463 GPIO4B5_MASK = 1 << GPIO4B5_SHIFT, 464 GPIO4B5_GPIO = 0, 465 GPIO4B5_FLASH_CSN6, 466 467 GPIO4B4_SHIFT = 8, 468 GPIO4B4_MASK = 1 << GPIO4B4_SHIFT, 469 GPIO4B4_GPIO = 0, 470 GPIO4B4_FLASH_CSN5, 471 472 GPIO4B3_SHIFT = 6, 473 GPIO4B3_MASK = 1 << GPIO4B3_SHIFT, 474 GPIO4B3_GPIO = 0, 475 GPIO4B3_FLASH_CSN4, 476 477 GPIO4B2_SHIFT = 4, 478 GPIO4B2_MASK = 3 << GPIO4B2_SHIFT, 479 GPIO4B2_GPIO = 0, 480 GPIO4B2_FLASH_CSN3, 481 GPIO4B2_EMMC_RSTN_OUT, 482 483 GPIO4B1_SHIFT = 2, 484 GPIO4B1_MASK = 3 << GPIO4B1_SHIFT, 485 GPIO4B1_GPIO = 0, 486 GPIO4B1_FLASH_CSN2, 487 GPIO4B1_EMMC_CMD, 488 489 GPIO4B0_SHIFT = 0, 490 GPIO4B0_MASK = 1 << GPIO4B0_SHIFT, 491 GPIO4B0_GPIO = 0, 492 GPIO4B0_FLASH_CSN1 493 }; 494 495 /* GRF_SOC_CON0 */ 496 enum { 497 SMC_MUX_CON_SHIFT = 13, 498 SMC_MUX_CON_MASK = 1 << SMC_MUX_CON_SHIFT, 499 500 NOC_REMAP_SHIFT = 12, 501 NOC_REMAP_MASK = 1 << NOC_REMAP_SHIFT, 502 503 EMMC_FLASH_SEL_SHIFT = 11, 504 EMMC_FLASH_SEL_MASK = 1 << EMMC_FLASH_SEL_SHIFT, 505 506 TZPC_REVISION_SHIFT = 7, 507 TZPC_REVISION_MASK = 0xf << TZPC_REVISION_SHIFT, 508 509 L2CACHE_ACC_SHIFT = 5, 510 L2CACHE_ACC_MASK = 3 << L2CACHE_ACC_SHIFT, 511 512 L2RD_WAIT_SHIFT = 3, 513 L2RD_WAIT_MASK = 3 << L2RD_WAIT_SHIFT, 514 515 IMEMRD_WAIT_SHIFT = 1, 516 IMEMRD_WAIT_MASK = 3 << IMEMRD_WAIT_SHIFT, 517 518 SOC_REMAP_SHIFT = 0, 519 SOC_REMAP_MASK = 1 << SOC_REMAP_SHIFT, 520 }; 521 522 /* GRF_SOC_CON1 */ 523 enum { 524 RKI2C4_SEL_SHIFT = 15, 525 RKI2C4_SEL_MASK = 1 << RKI2C4_SEL_SHIFT, 526 527 RKI2C3_SEL_SHIFT = 14, 528 RKI2C3_SEL_MASK = 1 << RKI2C3_SEL_SHIFT, 529 530 RKI2C2_SEL_SHIFT = 13, 531 RKI2C2_SEL_MASK = 1 << RKI2C2_SEL_SHIFT, 532 533 RKI2C1_SEL_SHIFT = 12, 534 RKI2C1_SEL_MASK = 1 << RKI2C1_SEL_SHIFT, 535 536 RKI2C0_SEL_SHIFT = 11, 537 RKI2C0_SEL_MASK = 1 << RKI2C0_SEL_SHIFT, 538 539 VCODEC_SEL_SHIFT = 10, 540 VCODEC_SEL_MASK = 1 << VCODEC_SEL_SHIFT, 541 542 PERI_EMEM_PAUSE_SHIFT = 9, 543 PERI_EMEM_PAUSE_MASK = 1 << PERI_EMEM_PAUSE_SHIFT, 544 545 PERI_USB_PAUSE_SHIFT = 8, 546 PERI_USB_PAUSE_MASK = 1 << PERI_USB_PAUSE_SHIFT, 547 548 SMC_MUX_MODE_0_SHIFT = 6, 549 SMC_MUX_MODE_0_MASK = 1 << SMC_MUX_MODE_0_SHIFT, 550 551 SMC_SRAM_MW_0_SHIFT = 4, 552 SMC_SRAM_MW_0_MASK = 3 << SMC_SRAM_MW_0_SHIFT, 553 554 SMC_REMAP_0_SHIFT = 3, 555 SMC_REMAP_0_MASK = 1 << SMC_REMAP_0_SHIFT, 556 557 SMC_A_GT_M0_SYNC_SHIFT = 2, 558 SMC_A_GT_M0_SYNC_MASK = 1 << SMC_A_GT_M0_SYNC_SHIFT, 559 560 EMAC_SPEED_SHIFT = 1, 561 EMAC_SPEEC_MASK = 1 << EMAC_SPEED_SHIFT, 562 563 EMAC_MODE_SHIFT = 0, 564 EMAC_MODE_MASK = 1 << EMAC_MODE_SHIFT, 565 }; 566 567 /* GRF_SOC_CON2 */ 568 enum { 569 570 MSCH4_MAINDDR3_SHIFT = 7, 571 MSCH4_MAINDDR3_MASK = 1 << MSCH4_MAINDDR3_SHIFT, 572 MSCH4_MAINDDR3_DDR3 = 1, 573 574 EMAC_NEWRCV_EN_SHIFT = 6, 575 EMAC_NEWRCV_EN_MASK = 1 << EMAC_NEWRCV_EN_SHIFT, 576 577 SW_ADDR15_EN_SHIFT = 5, 578 SW_ADDR15_EN_MASK = 1 << SW_ADDR15_EN_SHIFT, 579 580 SW_ADDR16_EN_SHIFT = 4, 581 SW_ADDR16_EN_MASK = 1 << SW_ADDR16_EN_SHIFT, 582 583 SW_ADDR17_EN_SHIFT = 3, 584 SW_ADDR17_EN_MASK = 1 << SW_ADDR17_EN_SHIFT, 585 586 BANK2_TO_RANK_EN_SHIFT = 2, 587 BANK2_TO_RANK_EN_MASK = 1 << BANK2_TO_RANK_EN_SHIFT, 588 589 RANK_TO_ROW15_EN_SHIFT = 1, 590 RANK_TO_ROW15_EN_MASK = 1 << RANK_TO_ROW15_EN_SHIFT, 591 592 UPCTL_C_ACTIVE_IN_SHIFT = 0, 593 UPCTL_C_ACTIVE_IN_MASK = 1 << UPCTL_C_ACTIVE_IN_SHIFT, 594 UPCTL_C_ACTIVE_IN_MAY = 0, 595 UPCTL_C_ACTIVE_IN_WILL, 596 }; 597 598 /* GRF_DDRC_CON0 */ 599 enum { 600 DTO_LB_SHIFT = 11, 601 DTO_LB_MASK = 3 << DTO_LB_SHIFT, 602 603 DTO_TE_SHIFT = 9, 604 DTO_TE_MASK = 3 << DTO_TE_SHIFT, 605 606 DTO_PDR_SHIFT = 7, 607 DTO_PDR_MASK = 3 << DTO_PDR_SHIFT, 608 609 DTO_PDD_SHIFT = 5, 610 DTO_PDD_MASK = 3 << DTO_PDD_SHIFT, 611 612 DTO_IOM_SHIFT = 3, 613 DTO_IOM_MASK = 3 << DTO_IOM_SHIFT, 614 615 DTO_OE_SHIFT = 1, 616 DTO_OE_MASK = 3 << DTO_OE_SHIFT, 617 618 ATO_AE_SHIFT = 0, 619 ATO_AE_MASK = 1 << ATO_AE_SHIFT, 620 }; 621 #endif 622