1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2015 Google, Inc 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _ASM_ARCH_GPIO_H 8*4882a593Smuzhiyun #define _ASM_ARCH_GPIO_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef CONFIG_ROCKCHIP_GPIO_V2 11*4882a593Smuzhiyun struct rockchip_gpio_regs { 12*4882a593Smuzhiyun u32 swport_dr; 13*4882a593Smuzhiyun u32 swport_ddr; 14*4882a593Smuzhiyun u32 reserved0[(0x30 - 0x08) / 4]; 15*4882a593Smuzhiyun u32 inten; 16*4882a593Smuzhiyun u32 intmask; 17*4882a593Smuzhiyun u32 inttype_level; 18*4882a593Smuzhiyun u32 int_polarity; 19*4882a593Smuzhiyun u32 int_status; 20*4882a593Smuzhiyun u32 int_rawstatus; 21*4882a593Smuzhiyun u32 debounce; 22*4882a593Smuzhiyun u32 porta_eoi; 23*4882a593Smuzhiyun u32 ext_port; 24*4882a593Smuzhiyun u32 reserved1[(0x60 - 0x54) / 4]; 25*4882a593Smuzhiyun u32 ls_sync; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun check_member(rockchip_gpio_regs, ls_sync, 0x60); 28*4882a593Smuzhiyun #else 29*4882a593Smuzhiyun struct rockchip_gpio_regs { 30*4882a593Smuzhiyun u32 swport_dr_l; /* ADDRESS OFFSET: 0x0000 */ 31*4882a593Smuzhiyun u32 swport_dr_h; /* ADDRESS OFFSET: 0x0004 */ 32*4882a593Smuzhiyun u32 swport_ddr_l; /* ADDRESS OFFSET: 0x0008 */ 33*4882a593Smuzhiyun u32 swport_ddr_h; /* ADDRESS OFFSET: 0x000c */ 34*4882a593Smuzhiyun u32 int_en_l; /* ADDRESS OFFSET: 0x0010 */ 35*4882a593Smuzhiyun u32 int_en_h; /* ADDRESS OFFSET: 0x0014 */ 36*4882a593Smuzhiyun u32 int_mask_l; /* ADDRESS OFFSET: 0x0018 */ 37*4882a593Smuzhiyun u32 int_mask_h; /* ADDRESS OFFSET: 0x001c */ 38*4882a593Smuzhiyun u32 int_type_l; /* ADDRESS OFFSET: 0x0020 */ 39*4882a593Smuzhiyun u32 int_type_h; /* ADDRESS OFFSET: 0x0024 */ 40*4882a593Smuzhiyun u32 int_polarity_l; /* ADDRESS OFFSET: 0x0028 */ 41*4882a593Smuzhiyun u32 int_polarity_h; /* ADDRESS OFFSET: 0x002c */ 42*4882a593Smuzhiyun u32 int_bothedge_l; /* ADDRESS OFFSET: 0x0030 */ 43*4882a593Smuzhiyun u32 int_bothedge_h; /* ADDRESS OFFSET: 0x0034 */ 44*4882a593Smuzhiyun u32 debounce_l; /* ADDRESS OFFSET: 0x0038 */ 45*4882a593Smuzhiyun u32 debounce_h; /* ADDRESS OFFSET: 0x003c */ 46*4882a593Smuzhiyun u32 dbclk_div_en_l; /* ADDRESS OFFSET: 0x0040 */ 47*4882a593Smuzhiyun u32 dbclk_div_en_h; /* ADDRESS OFFSET: 0x0044 */ 48*4882a593Smuzhiyun u32 dbclk_div_con; /* ADDRESS OFFSET: 0x0048 */ 49*4882a593Smuzhiyun u32 reserved004c; /* ADDRESS OFFSET: 0x004c */ 50*4882a593Smuzhiyun u32 int_status; /* ADDRESS OFFSET: 0x0050 */ 51*4882a593Smuzhiyun u32 reserved0054; /* ADDRESS OFFSET: 0x0054 */ 52*4882a593Smuzhiyun u32 int_rawstatus; /* ADDRESS OFFSET: 0x0058 */ 53*4882a593Smuzhiyun u32 reserved005c; /* ADDRESS OFFSET: 0x005c */ 54*4882a593Smuzhiyun u32 port_eoi_l; /* ADDRESS OFFSET: 0x0060 */ 55*4882a593Smuzhiyun u32 port_eoi_h; /* ADDRESS OFFSET: 0x0064 */ 56*4882a593Smuzhiyun u32 reserved0068[2]; /* ADDRESS OFFSET: 0x0068 */ 57*4882a593Smuzhiyun u32 ext_port; /* ADDRESS OFFSET: 0x0070 */ 58*4882a593Smuzhiyun u32 reserved0074; /* ADDRESS OFFSET: 0x0074 */ 59*4882a593Smuzhiyun u32 ver_id; /* ADDRESS OFFSET: 0x0078 */ 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun check_member(rockchip_gpio_regs, ver_id, 0x0078); 62*4882a593Smuzhiyun #endif 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #endif 65