xref: /OK3568_Linux_fs/u-boot/arch/arm/dts/include/dt-bindings/clock/rk3528-cru.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
4*4882a593Smuzhiyun  * Author: Joseph Chen <chenjh@rock-chips.com>
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H
8*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun /* cru-clocks indices */
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun /* core clocks */
13*4882a593Smuzhiyun #define PLL_APLL                       1
14*4882a593Smuzhiyun #define PLL_CPLL                       2
15*4882a593Smuzhiyun #define PLL_GPLL                       3
16*4882a593Smuzhiyun #define PLL_PPLL                       4
17*4882a593Smuzhiyun #define PLL_DPLL                       5
18*4882a593Smuzhiyun #define ARMCLK                         6
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #define XIN_OSC0_HALF                  8
21*4882a593Smuzhiyun #define CLK_MATRIX_50M_SRC             9
22*4882a593Smuzhiyun #define CLK_MATRIX_100M_SRC            10
23*4882a593Smuzhiyun #define CLK_MATRIX_150M_SRC            11
24*4882a593Smuzhiyun #define CLK_MATRIX_200M_SRC            12
25*4882a593Smuzhiyun #define CLK_MATRIX_250M_SRC            13
26*4882a593Smuzhiyun #define CLK_MATRIX_300M_SRC            14
27*4882a593Smuzhiyun #define CLK_MATRIX_339M_SRC            15
28*4882a593Smuzhiyun #define CLK_MATRIX_400M_SRC            16
29*4882a593Smuzhiyun #define CLK_MATRIX_500M_SRC            17
30*4882a593Smuzhiyun #define CLK_MATRIX_600M_SRC            18
31*4882a593Smuzhiyun #define CLK_UART0_SRC                  19
32*4882a593Smuzhiyun #define CLK_UART0_FRAC                 20
33*4882a593Smuzhiyun #define SCLK_UART0                     21
34*4882a593Smuzhiyun #define CLK_UART1_SRC                  22
35*4882a593Smuzhiyun #define CLK_UART1_FRAC                 23
36*4882a593Smuzhiyun #define SCLK_UART1                     24
37*4882a593Smuzhiyun #define CLK_UART2_SRC                  25
38*4882a593Smuzhiyun #define CLK_UART2_FRAC                 26
39*4882a593Smuzhiyun #define SCLK_UART2                     27
40*4882a593Smuzhiyun #define CLK_UART3_SRC                  28
41*4882a593Smuzhiyun #define CLK_UART3_FRAC                 29
42*4882a593Smuzhiyun #define SCLK_UART3                     30
43*4882a593Smuzhiyun #define CLK_UART4_SRC                  31
44*4882a593Smuzhiyun #define CLK_UART4_FRAC                 32
45*4882a593Smuzhiyun #define SCLK_UART4                     33
46*4882a593Smuzhiyun #define CLK_UART5_SRC                  34
47*4882a593Smuzhiyun #define CLK_UART5_FRAC                 35
48*4882a593Smuzhiyun #define SCLK_UART5                     36
49*4882a593Smuzhiyun #define CLK_UART6_SRC                  37
50*4882a593Smuzhiyun #define CLK_UART6_FRAC                 38
51*4882a593Smuzhiyun #define SCLK_UART6                     39
52*4882a593Smuzhiyun #define CLK_UART7_SRC                  40
53*4882a593Smuzhiyun #define CLK_UART7_FRAC                 41
54*4882a593Smuzhiyun #define SCLK_UART7                     42
55*4882a593Smuzhiyun #define CLK_I2S0_2CH_SRC               43
56*4882a593Smuzhiyun #define CLK_I2S0_2CH_FRAC              44
57*4882a593Smuzhiyun #define MCLK_I2S0_2CH_SAI_SRC          45
58*4882a593Smuzhiyun #define CLK_I2S3_8CH_SRC               46
59*4882a593Smuzhiyun #define CLK_I2S3_8CH_FRAC              47
60*4882a593Smuzhiyun #define MCLK_I2S3_8CH_SAI_SRC          48
61*4882a593Smuzhiyun #define CLK_I2S1_8CH_SRC               49
62*4882a593Smuzhiyun #define CLK_I2S1_8CH_FRAC              50
63*4882a593Smuzhiyun #define MCLK_I2S1_8CH_SAI_SRC          51
64*4882a593Smuzhiyun #define CLK_I2S2_2CH_SRC               52
65*4882a593Smuzhiyun #define CLK_I2S2_2CH_FRAC              53
66*4882a593Smuzhiyun #define MCLK_I2S2_2CH_SAI_SRC          54
67*4882a593Smuzhiyun #define CLK_SPDIF_SRC                  55
68*4882a593Smuzhiyun #define CLK_SPDIF_FRAC                 56
69*4882a593Smuzhiyun #define MCLK_SPDIF_SRC                 57
70*4882a593Smuzhiyun #define DCLK_VOP_SRC0                  58
71*4882a593Smuzhiyun #define DCLK_VOP_SRC1                  59
72*4882a593Smuzhiyun #define CLK_HSM                        60
73*4882a593Smuzhiyun #define CLK_CORE_SRC_ACS               63
74*4882a593Smuzhiyun #define CLK_CORE_SRC_PVTMUX            65
75*4882a593Smuzhiyun #define CLK_CORE_SRC                   66
76*4882a593Smuzhiyun #define CLK_CORE                       67
77*4882a593Smuzhiyun #define ACLK_M_CORE_BIU                68
78*4882a593Smuzhiyun #define CLK_CORE_PVTPLL_SRC            69
79*4882a593Smuzhiyun #define PCLK_DBG                       70
80*4882a593Smuzhiyun #define SWCLKTCK                       71
81*4882a593Smuzhiyun #define CLK_SCANHS_CORE                72
82*4882a593Smuzhiyun #define CLK_SCANHS_ACLKM_CORE          73
83*4882a593Smuzhiyun #define CLK_SCANHS_PCLK_DBG            74
84*4882a593Smuzhiyun #define CLK_SCANHS_PCLK_CPU_BIU        76
85*4882a593Smuzhiyun #define PCLK_CPU_ROOT                  77
86*4882a593Smuzhiyun #define PCLK_CORE_GRF                  78
87*4882a593Smuzhiyun #define PCLK_DAPLITE_BIU               79
88*4882a593Smuzhiyun #define PCLK_CPU_BIU                   80
89*4882a593Smuzhiyun #define CLK_REF_PVTPLL_CORE            81
90*4882a593Smuzhiyun #define ACLK_BUS_VOPGL_ROOT            85
91*4882a593Smuzhiyun #define ACLK_BUS_VOPGL_BIU             86
92*4882a593Smuzhiyun #define ACLK_BUS_H_ROOT                87
93*4882a593Smuzhiyun #define ACLK_BUS_H_BIU                 88
94*4882a593Smuzhiyun #define ACLK_BUS_ROOT                  89
95*4882a593Smuzhiyun #define HCLK_BUS_ROOT                  90
96*4882a593Smuzhiyun #define PCLK_BUS_ROOT                  91
97*4882a593Smuzhiyun #define ACLK_BUS_M_ROOT                92
98*4882a593Smuzhiyun #define ACLK_SYSMEM_BIU                93
99*4882a593Smuzhiyun #define CLK_TIMER_ROOT                 95
100*4882a593Smuzhiyun #define ACLK_BUS_BIU                   96
101*4882a593Smuzhiyun #define HCLK_BUS_BIU                   97
102*4882a593Smuzhiyun #define PCLK_BUS_BIU                   98
103*4882a593Smuzhiyun #define PCLK_DFT2APB                   99
104*4882a593Smuzhiyun #define PCLK_BUS_GRF                   100
105*4882a593Smuzhiyun #define ACLK_BUS_M_BIU                 101
106*4882a593Smuzhiyun #define ACLK_GIC                       102
107*4882a593Smuzhiyun #define ACLK_SPINLOCK                  103
108*4882a593Smuzhiyun #define ACLK_DMAC                      104
109*4882a593Smuzhiyun #define PCLK_TIMER                     105
110*4882a593Smuzhiyun #define CLK_TIMER0                     106
111*4882a593Smuzhiyun #define CLK_TIMER1                     107
112*4882a593Smuzhiyun #define CLK_TIMER2                     108
113*4882a593Smuzhiyun #define CLK_TIMER3                     109
114*4882a593Smuzhiyun #define CLK_TIMER4                     110
115*4882a593Smuzhiyun #define CLK_TIMER5                     111
116*4882a593Smuzhiyun #define PCLK_JDBCK_DAP                 112
117*4882a593Smuzhiyun #define CLK_JDBCK_DAP                  113
118*4882a593Smuzhiyun #define PCLK_WDT_NS                    114
119*4882a593Smuzhiyun #define TCLK_WDT_NS                    115
120*4882a593Smuzhiyun #define HCLK_TRNG_NS                   116
121*4882a593Smuzhiyun #define PCLK_UART0                     117
122*4882a593Smuzhiyun #define CLK_CORE_CRYPTO                119
123*4882a593Smuzhiyun #define CLK_PKA_CRYPTO                 120
124*4882a593Smuzhiyun #define ACLK_CRYPTO                    121
125*4882a593Smuzhiyun #define HCLK_CRYPTO                    122
126*4882a593Smuzhiyun #define PCLK_DMA2DDR                   123
127*4882a593Smuzhiyun #define ACLK_DMA2DDR                   124
128*4882a593Smuzhiyun #define PCLK_PWM0                      126
129*4882a593Smuzhiyun #define CLK_PWM0                       127
130*4882a593Smuzhiyun #define CLK_CAPTURE_PWM0               128
131*4882a593Smuzhiyun #define PCLK_PWM1                      129
132*4882a593Smuzhiyun #define CLK_PWM1                       130
133*4882a593Smuzhiyun #define CLK_CAPTURE_PWM1               131
134*4882a593Smuzhiyun #define PCLK_SCR                       134
135*4882a593Smuzhiyun #define ACLK_DCF                       135
136*4882a593Smuzhiyun #define PCLK_INTMUX                    138
137*4882a593Smuzhiyun #define CLK_PPLL_I                     141
138*4882a593Smuzhiyun #define CLK_PPLL_MUX                   142
139*4882a593Smuzhiyun #define CLK_PPLL_100M_MATRIX           143
140*4882a593Smuzhiyun #define CLK_PPLL_50M_MATRIX            144
141*4882a593Smuzhiyun #define CLK_REF_PCIE_INNER_PHY         145
142*4882a593Smuzhiyun #define CLK_REF_PCIE_100M_PHY          146
143*4882a593Smuzhiyun #define ACLK_VPU_L_ROOT                147
144*4882a593Smuzhiyun #define CLK_GMAC1_VPU_25M              148
145*4882a593Smuzhiyun #define CLK_PPLL_125M_MATRIX           149
146*4882a593Smuzhiyun #define ACLK_VPU_ROOT                  150
147*4882a593Smuzhiyun #define HCLK_VPU_ROOT                  151
148*4882a593Smuzhiyun #define PCLK_VPU_ROOT                  152
149*4882a593Smuzhiyun #define ACLK_VPU_BIU                   153
150*4882a593Smuzhiyun #define HCLK_VPU_BIU                   154
151*4882a593Smuzhiyun #define PCLK_VPU_BIU                   155
152*4882a593Smuzhiyun #define ACLK_VPU                       156
153*4882a593Smuzhiyun #define HCLK_VPU                       157
154*4882a593Smuzhiyun #define PCLK_CRU_PCIE                  158
155*4882a593Smuzhiyun #define PCLK_VPU_GRF                   159
156*4882a593Smuzhiyun #define HCLK_SFC                       160
157*4882a593Smuzhiyun #define SCLK_SFC                       161
158*4882a593Smuzhiyun #define CCLK_SRC_EMMC                  163
159*4882a593Smuzhiyun #define HCLK_EMMC                      164
160*4882a593Smuzhiyun #define ACLK_EMMC                      165
161*4882a593Smuzhiyun #define BCLK_EMMC                      166
162*4882a593Smuzhiyun #define TCLK_EMMC                      167
163*4882a593Smuzhiyun #define PCLK_GPIO1                     168
164*4882a593Smuzhiyun #define DBCLK_GPIO1                    169
165*4882a593Smuzhiyun #define ACLK_VPU_L_BIU                 172
166*4882a593Smuzhiyun #define PCLK_VPU_IOC                   173
167*4882a593Smuzhiyun #define HCLK_SAI_I2S0                  174
168*4882a593Smuzhiyun #define MCLK_SAI_I2S0                  175
169*4882a593Smuzhiyun #define HCLK_SAI_I2S2                  176
170*4882a593Smuzhiyun #define MCLK_SAI_I2S2                  177
171*4882a593Smuzhiyun #define PCLK_ACODEC                    178
172*4882a593Smuzhiyun #define MCLK_ACODEC_TX                 179
173*4882a593Smuzhiyun #define PCLK_GPIO3                     186
174*4882a593Smuzhiyun #define DBCLK_GPIO3                    187
175*4882a593Smuzhiyun #define PCLK_SPI1                      189
176*4882a593Smuzhiyun #define CLK_SPI1                       190
177*4882a593Smuzhiyun #define SCLK_IN_SPI1                   191
178*4882a593Smuzhiyun #define PCLK_UART2                     192
179*4882a593Smuzhiyun #define PCLK_UART5                     194
180*4882a593Smuzhiyun #define PCLK_UART6                     196
181*4882a593Smuzhiyun #define PCLK_UART7                     198
182*4882a593Smuzhiyun #define PCLK_I2C3                      200
183*4882a593Smuzhiyun #define CLK_I2C3                       201
184*4882a593Smuzhiyun #define PCLK_I2C5                      202
185*4882a593Smuzhiyun #define CLK_I2C5                       203
186*4882a593Smuzhiyun #define PCLK_I2C6                      204
187*4882a593Smuzhiyun #define CLK_I2C6                       205
188*4882a593Smuzhiyun #define ACLK_MAC_VPU                   206
189*4882a593Smuzhiyun #define PCLK_MAC_VPU                   207
190*4882a593Smuzhiyun #define CLK_GMAC1_RMII_VPU             209
191*4882a593Smuzhiyun #define CLK_GMAC1_SRC_VPU              210
192*4882a593Smuzhiyun #define PCLK_PCIE                      215
193*4882a593Smuzhiyun #define CLK_PCIE_AUX                   216
194*4882a593Smuzhiyun #define ACLK_PCIE                      217
195*4882a593Smuzhiyun #define HCLK_PCIE_SLV                  218
196*4882a593Smuzhiyun #define HCLK_PCIE_DBI                  219
197*4882a593Smuzhiyun #define PCLK_PCIE_PHY                  220
198*4882a593Smuzhiyun #define PCLK_PIPE_GRF                  221
199*4882a593Smuzhiyun #define CLK_PIPE_USB3OTG_COMBO         230
200*4882a593Smuzhiyun #define CLK_UTMI_USB3OTG               232
201*4882a593Smuzhiyun #define CLK_PCIE_PIPE_PHY              235
202*4882a593Smuzhiyun #define CCLK_SRC_SDIO0                 240
203*4882a593Smuzhiyun #define HCLK_SDIO0                     241
204*4882a593Smuzhiyun #define CCLK_SRC_SDIO1                 244
205*4882a593Smuzhiyun #define HCLK_SDIO1                     245
206*4882a593Smuzhiyun #define CLK_TS_0                       246
207*4882a593Smuzhiyun #define CLK_TS_1                       247
208*4882a593Smuzhiyun #define PCLK_CAN2                      250
209*4882a593Smuzhiyun #define CLK_CAN2                       251
210*4882a593Smuzhiyun #define PCLK_CAN3                      252
211*4882a593Smuzhiyun #define CLK_CAN3                       253
212*4882a593Smuzhiyun #define PCLK_SARADC                    256
213*4882a593Smuzhiyun #define CLK_SARADC                     257
214*4882a593Smuzhiyun #define PCLK_TSADC                     258
215*4882a593Smuzhiyun #define CLK_TSADC                      259
216*4882a593Smuzhiyun #define CLK_TSADC_TSEN                 260
217*4882a593Smuzhiyun #define ACLK_USB3OTG                   261
218*4882a593Smuzhiyun #define CLK_REF_USB3OTG                262
219*4882a593Smuzhiyun #define CLK_SUSPEND_USB3OTG            263
220*4882a593Smuzhiyun #define ACLK_GPU_ROOT                  269
221*4882a593Smuzhiyun #define PCLK_GPU_ROOT                  270
222*4882a593Smuzhiyun #define ACLK_GPU_BIU                   271
223*4882a593Smuzhiyun #define PCLK_GPU_BIU                   272
224*4882a593Smuzhiyun #define ACLK_GPU                       273
225*4882a593Smuzhiyun #define CLK_GPU_PVTPLL_SRC             274
226*4882a593Smuzhiyun #define ACLK_GPU_MALI                  275
227*4882a593Smuzhiyun #define HCLK_RKVENC_ROOT               281
228*4882a593Smuzhiyun #define ACLK_RKVENC_ROOT               282
229*4882a593Smuzhiyun #define PCLK_RKVENC_ROOT               283
230*4882a593Smuzhiyun #define HCLK_RKVENC_BIU                284
231*4882a593Smuzhiyun #define ACLK_RKVENC_BIU                285
232*4882a593Smuzhiyun #define PCLK_RKVENC_BIU                286
233*4882a593Smuzhiyun #define HCLK_RKVENC                    287
234*4882a593Smuzhiyun #define ACLK_RKVENC                    288
235*4882a593Smuzhiyun #define CLK_CORE_RKVENC                289
236*4882a593Smuzhiyun #define HCLK_SAI_I2S1                  290
237*4882a593Smuzhiyun #define MCLK_SAI_I2S1                  291
238*4882a593Smuzhiyun #define PCLK_I2C1                      292
239*4882a593Smuzhiyun #define CLK_I2C1                       293
240*4882a593Smuzhiyun #define PCLK_I2C0                      294
241*4882a593Smuzhiyun #define CLK_I2C0                       295
242*4882a593Smuzhiyun #define CLK_UART_JTAG                  296
243*4882a593Smuzhiyun #define PCLK_SPI0                      297
244*4882a593Smuzhiyun #define CLK_SPI0                       298
245*4882a593Smuzhiyun #define SCLK_IN_SPI0                   299
246*4882a593Smuzhiyun #define PCLK_GPIO4                     300
247*4882a593Smuzhiyun #define DBCLK_GPIO4                    301
248*4882a593Smuzhiyun #define PCLK_RKVENC_IOC                302
249*4882a593Smuzhiyun #define HCLK_SPDIF                     308
250*4882a593Smuzhiyun #define MCLK_SPDIF                     309
251*4882a593Smuzhiyun #define HCLK_PDM                       310
252*4882a593Smuzhiyun #define MCLK_PDM                       311
253*4882a593Smuzhiyun #define PCLK_UART1                     315
254*4882a593Smuzhiyun #define PCLK_UART3                     317
255*4882a593Smuzhiyun #define PCLK_RKVENC_GRF                319
256*4882a593Smuzhiyun #define PCLK_CAN0                      320
257*4882a593Smuzhiyun #define CLK_CAN0                       321
258*4882a593Smuzhiyun #define PCLK_CAN1                      322
259*4882a593Smuzhiyun #define CLK_CAN1                       323
260*4882a593Smuzhiyun #define ACLK_VO_ROOT                   324
261*4882a593Smuzhiyun #define HCLK_VO_ROOT                   325
262*4882a593Smuzhiyun #define PCLK_VO_ROOT                   326
263*4882a593Smuzhiyun #define ACLK_VO_BIU                    327
264*4882a593Smuzhiyun #define HCLK_VO_BIU                    328
265*4882a593Smuzhiyun #define PCLK_VO_BIU                    329
266*4882a593Smuzhiyun #define HCLK_RGA2E                     330
267*4882a593Smuzhiyun #define ACLK_RGA2E                     331
268*4882a593Smuzhiyun #define CLK_CORE_RGA2E                 332
269*4882a593Smuzhiyun #define HCLK_VDPP                      333
270*4882a593Smuzhiyun #define ACLK_VDPP                      334
271*4882a593Smuzhiyun #define CLK_CORE_VDPP                  335
272*4882a593Smuzhiyun #define PCLK_VO_GRF                    336
273*4882a593Smuzhiyun #define PCLK_CRU                       337
274*4882a593Smuzhiyun #define ACLK_VOP_ROOT                  338
275*4882a593Smuzhiyun #define ACLK_VOP_BIU                   339
276*4882a593Smuzhiyun #define HCLK_VOP                       340
277*4882a593Smuzhiyun #define DCLK_VOP0                      341
278*4882a593Smuzhiyun #define DCLK_VOP1                      342
279*4882a593Smuzhiyun #define ACLK_VOP                       343
280*4882a593Smuzhiyun #define PCLK_HDMI                      344
281*4882a593Smuzhiyun #define CLK_SFR_HDMI                   345
282*4882a593Smuzhiyun #define CLK_CEC_HDMI                   346
283*4882a593Smuzhiyun #define CLK_SPDIF_HDMI                 347
284*4882a593Smuzhiyun #define CLK_HDMIPHY_TMDSSRC            348
285*4882a593Smuzhiyun #define CLK_HDMIPHY_PREP               349
286*4882a593Smuzhiyun #define PCLK_HDMIPHY                   352
287*4882a593Smuzhiyun #define HCLK_HDCP_KEY                  354
288*4882a593Smuzhiyun #define ACLK_HDCP                      355
289*4882a593Smuzhiyun #define HCLK_HDCP                      356
290*4882a593Smuzhiyun #define PCLK_HDCP                      357
291*4882a593Smuzhiyun #define HCLK_CVBS                      358
292*4882a593Smuzhiyun #define DCLK_CVBS                      359
293*4882a593Smuzhiyun #define DCLK_4X_CVBS                   360
294*4882a593Smuzhiyun #define ACLK_JPEG_DECODER              361
295*4882a593Smuzhiyun #define HCLK_JPEG_DECODER              362
296*4882a593Smuzhiyun #define ACLK_VO_L_ROOT                 375
297*4882a593Smuzhiyun #define ACLK_VO_L_BIU                  376
298*4882a593Smuzhiyun #define ACLK_MAC_VO                    377
299*4882a593Smuzhiyun #define PCLK_MAC_VO                    378
300*4882a593Smuzhiyun #define CLK_GMAC0_SRC                  379
301*4882a593Smuzhiyun #define CLK_GMAC0_RMII_50M             380
302*4882a593Smuzhiyun #define CLK_GMAC0_TX                   381
303*4882a593Smuzhiyun #define CLK_GMAC0_RX                   382
304*4882a593Smuzhiyun #define ACLK_JPEG_ROOT                 385
305*4882a593Smuzhiyun #define ACLK_JPEG_BIU                  386
306*4882a593Smuzhiyun #define HCLK_SAI_I2S3                  387
307*4882a593Smuzhiyun #define MCLK_SAI_I2S3                  388
308*4882a593Smuzhiyun #define CLK_MACPHY                     398
309*4882a593Smuzhiyun #define PCLK_VCDCPHY                   399
310*4882a593Smuzhiyun #define PCLK_GPIO2                     404
311*4882a593Smuzhiyun #define DBCLK_GPIO2                    405
312*4882a593Smuzhiyun #define PCLK_VO_IOC                    406
313*4882a593Smuzhiyun #define CCLK_SRC_SDMMC0                407
314*4882a593Smuzhiyun #define HCLK_SDMMC0                    408
315*4882a593Smuzhiyun #define PCLK_OTPC_NS                   411
316*4882a593Smuzhiyun #define CLK_SBPI_OTPC_NS               412
317*4882a593Smuzhiyun #define CLK_USER_OTPC_NS               413
318*4882a593Smuzhiyun #define CLK_HDMIHDP0                   415
319*4882a593Smuzhiyun #define HCLK_USBHOST                   416
320*4882a593Smuzhiyun #define HCLK_USBHOST_ARB               417
321*4882a593Smuzhiyun #define CLK_USBHOST_OHCI               418
322*4882a593Smuzhiyun #define CLK_USBHOST_UTMI               419
323*4882a593Smuzhiyun #define PCLK_UART4                     420
324*4882a593Smuzhiyun #define PCLK_I2C4                      422
325*4882a593Smuzhiyun #define CLK_I2C4                       423
326*4882a593Smuzhiyun #define PCLK_I2C7                      424
327*4882a593Smuzhiyun #define CLK_I2C7                       425
328*4882a593Smuzhiyun #define PCLK_USBPHY                    426
329*4882a593Smuzhiyun #define CLK_REF_USBPHY                 427
330*4882a593Smuzhiyun #define HCLK_RKVDEC_ROOT               433
331*4882a593Smuzhiyun #define ACLK_RKVDEC_ROOT_NDFT          434
332*4882a593Smuzhiyun #define PCLK_DDRPHY_CRU                435
333*4882a593Smuzhiyun #define HCLK_RKVDEC_BIU                436
334*4882a593Smuzhiyun #define ACLK_RKVDEC_BIU                437
335*4882a593Smuzhiyun #define ACLK_RKVDEC                    439
336*4882a593Smuzhiyun #define HCLK_RKVDEC                    440
337*4882a593Smuzhiyun #define CLK_HEVC_CA_RKVDEC             441
338*4882a593Smuzhiyun #define ACLK_RKVDEC_PVTMUX_ROOT        442
339*4882a593Smuzhiyun #define CLK_RKVDEC_PVTPLL_SRC          443
340*4882a593Smuzhiyun #define PCLK_DDR_ROOT                  449
341*4882a593Smuzhiyun #define PCLK_DDR_BIU                   450
342*4882a593Smuzhiyun #define PCLK_DDRC                      451
343*4882a593Smuzhiyun #define PCLK_DDRMON                    452
344*4882a593Smuzhiyun #define CLK_TIMER_DDRMON               453
345*4882a593Smuzhiyun #define PCLK_MSCH_BIU                  454
346*4882a593Smuzhiyun #define PCLK_DDR_GRF                   455
347*4882a593Smuzhiyun #define PCLK_DDR_HWLP                  456
348*4882a593Smuzhiyun #define PCLK_DDRPHY                    457
349*4882a593Smuzhiyun #define CLK_MSCH_BIU                   463
350*4882a593Smuzhiyun #define ACLK_DDR_UPCTL                 464
351*4882a593Smuzhiyun #define CLK_DDR_UPCTL                  465
352*4882a593Smuzhiyun #define CLK_DDRMON                     466
353*4882a593Smuzhiyun #define ACLK_DDR_SCRAMBLE              467
354*4882a593Smuzhiyun #define ACLK_SPLIT                     468
355*4882a593Smuzhiyun #define CLK_DDRC_SRC                   470
356*4882a593Smuzhiyun #define CLK_DDR_PHY                    471
357*4882a593Smuzhiyun #define PCLK_OTPC_S                    472
358*4882a593Smuzhiyun #define CLK_SBPI_OTPC_S                473
359*4882a593Smuzhiyun #define CLK_USER_OTPC_S                474
360*4882a593Smuzhiyun #define PCLK_KEYREADER                 475
361*4882a593Smuzhiyun #define PCLK_BUS_SGRF                  476
362*4882a593Smuzhiyun #define PCLK_STIMER                    477
363*4882a593Smuzhiyun #define CLK_STIMER0                    478
364*4882a593Smuzhiyun #define CLK_STIMER1                    479
365*4882a593Smuzhiyun #define PCLK_WDT_S                     480
366*4882a593Smuzhiyun #define TCLK_WDT_S                     481
367*4882a593Smuzhiyun #define HCLK_TRNG_S                    482
368*4882a593Smuzhiyun #define PCLK_KLAD                      483
369*4882a593Smuzhiyun #define HCLK_CRYPTO_S                  484
370*4882a593Smuzhiyun #define HCLK_KLAD                      485
371*4882a593Smuzhiyun #define HCLK_BOOTROM                   486
372*4882a593Smuzhiyun #define PCLK_DCF                       487
373*4882a593Smuzhiyun #define ACLK_SYSMEM                    488
374*4882a593Smuzhiyun #define HCLK_TSP                       489
375*4882a593Smuzhiyun #define ACLK_TSP                       490
376*4882a593Smuzhiyun #define CLK_CORE_TSP                   491
377*4882a593Smuzhiyun #define CLK_OTPC_ARB                   492
378*4882a593Smuzhiyun #define PCLK_OTP_MASK                  493
379*4882a593Smuzhiyun #define CLK_PMC_OTP                    494
380*4882a593Smuzhiyun #define PCLK_PMU_ROOT                  495
381*4882a593Smuzhiyun #define HCLK_PMU_ROOT                  496
382*4882a593Smuzhiyun #define PCLK_I2C2                      497
383*4882a593Smuzhiyun #define CLK_I2C2                       498
384*4882a593Smuzhiyun #define HCLK_PMU_BIU                   500
385*4882a593Smuzhiyun #define PCLK_PMU_BIU                   501
386*4882a593Smuzhiyun #define FCLK_MCU                       502
387*4882a593Smuzhiyun #define RTC_CLK_MCU                    504
388*4882a593Smuzhiyun #define PCLK_OSCCHK                    505
389*4882a593Smuzhiyun #define CLK_PMU_MCU_JTAG               506
390*4882a593Smuzhiyun #define PCLK_PMU                       508
391*4882a593Smuzhiyun #define PCLK_GPIO0                     509
392*4882a593Smuzhiyun #define DBCLK_GPIO0                    510
393*4882a593Smuzhiyun #define XIN_OSC0_DIV                   511
394*4882a593Smuzhiyun #define CLK_DEEPSLOW                   512
395*4882a593Smuzhiyun #define CLK_DDR_FAIL_SAFE              513
396*4882a593Smuzhiyun #define PCLK_PMU_HP_TIMER              514
397*4882a593Smuzhiyun #define CLK_PMU_HP_TIMER               515
398*4882a593Smuzhiyun #define CLK_PMU_32K_HP_TIMER           516
399*4882a593Smuzhiyun #define PCLK_PMU_IOC                   517
400*4882a593Smuzhiyun #define PCLK_PMU_CRU                   518
401*4882a593Smuzhiyun #define PCLK_PMU_GRF                   519
402*4882a593Smuzhiyun #define PCLK_PMU_WDT                   520
403*4882a593Smuzhiyun #define TCLK_PMU_WDT                   521
404*4882a593Smuzhiyun #define PCLK_PMU_MAILBOX               522
405*4882a593Smuzhiyun #define PCLK_SCRKEYGEN                 524
406*4882a593Smuzhiyun #define CLK_SCRKEYGEN                  525
407*4882a593Smuzhiyun #define CLK_PVTM_OSCCHK                526
408*4882a593Smuzhiyun #define CLK_REFOUT                     530
409*4882a593Smuzhiyun #define CLK_PVTM_PMU                   532
410*4882a593Smuzhiyun #define PCLK_PVTM_PMU                  533
411*4882a593Smuzhiyun #define PCLK_PMU_SGRF                  534
412*4882a593Smuzhiyun #define HCLK_PMU_SRAM                  535
413*4882a593Smuzhiyun #define CLK_UART0                      536
414*4882a593Smuzhiyun #define CLK_UART1                      537
415*4882a593Smuzhiyun #define CLK_UART2                      538
416*4882a593Smuzhiyun #define CLK_UART3                      539
417*4882a593Smuzhiyun #define CLK_UART4                      540
418*4882a593Smuzhiyun #define CLK_UART5                      541
419*4882a593Smuzhiyun #define CLK_UART6                      542
420*4882a593Smuzhiyun #define CLK_UART7                      543
421*4882a593Smuzhiyun #define MCLK_I2S0_2CH_SAI_SRC_PRE      544
422*4882a593Smuzhiyun #define MCLK_I2S1_8CH_SAI_SRC_PRE      545
423*4882a593Smuzhiyun #define MCLK_I2S2_2CH_SAI_SRC_PRE      546
424*4882a593Smuzhiyun #define MCLK_I2S3_8CH_SAI_SRC_PRE      547
425*4882a593Smuzhiyun #define MCLK_SDPDIF_SRC_PRE            548
426*4882a593Smuzhiyun #define CLK_NR_CLKS                    (MCLK_SDPDIF_SRC_PRE + 1)
427*4882a593Smuzhiyun 
428*4882a593Smuzhiyun /* grf-clocks indices */
429*4882a593Smuzhiyun #define SCLK_SDMMC_DRV                 1
430*4882a593Smuzhiyun #define SCLK_SDMMC_SAMPLE              2
431*4882a593Smuzhiyun #define SCLK_SDIO0_DRV                 3
432*4882a593Smuzhiyun #define SCLK_SDIO0_SAMPLE              4
433*4882a593Smuzhiyun #define SCLK_SDIO1_DRV                 5
434*4882a593Smuzhiyun #define SCLK_SDIO1_SAMPLE              6
435*4882a593Smuzhiyun #define CLK_NR_GRF_CLKS                (SCLK_SDIO1_SAMPLE + 1)
436*4882a593Smuzhiyun 
437*4882a593Smuzhiyun /* scmi-clocks indices */
438*4882a593Smuzhiyun #define SCMI_PCLK_KEYREADER            0
439*4882a593Smuzhiyun #define SCMI_HCLK_KLAD                 1
440*4882a593Smuzhiyun #define SCMI_PCLK_KLAD                 2
441*4882a593Smuzhiyun #define SCMI_HCLK_TRNG_S               3
442*4882a593Smuzhiyun #define SCMI_HCLK_CRYPTO_S             4
443*4882a593Smuzhiyun #define SCMI_PCLK_WDT_S                5
444*4882a593Smuzhiyun #define SCMI_TCLK_WDT_S                6
445*4882a593Smuzhiyun #define SCMI_PCLK_STIMER               7
446*4882a593Smuzhiyun #define SCMI_CLK_STIMER0               8
447*4882a593Smuzhiyun #define SCMI_CLK_STIMER1               9
448*4882a593Smuzhiyun #define SCMI_PCLK_OTP_MASK             10
449*4882a593Smuzhiyun #define SCMI_PCLK_OTPC_S               11
450*4882a593Smuzhiyun #define SCMI_CLK_SBPI_OTPC_S           12
451*4882a593Smuzhiyun #define SCMI_CLK_USER_OTPC_S           13
452*4882a593Smuzhiyun #define SCMI_CLK_PMC_OTP               14
453*4882a593Smuzhiyun #define SCMI_CLK_OTPC_ARB              15
454*4882a593Smuzhiyun #define SCMI_CLK_CORE_TSP              16
455*4882a593Smuzhiyun #define SCMI_ACLK_TSP                  17
456*4882a593Smuzhiyun #define SCMI_HCLK_TSP                  18
457*4882a593Smuzhiyun #define SCMI_PCLK_DCF                  19
458*4882a593Smuzhiyun #define SCMI_CLK_DDR                   20
459*4882a593Smuzhiyun #define SCMI_CLK_CPU                   21
460*4882a593Smuzhiyun #define SCMI_CLK_GPU                   22
461*4882a593Smuzhiyun #define SCMI_CORE_CRYPTO               23
462*4882a593Smuzhiyun #define SCMI_ACLK_CRYPTO               24
463*4882a593Smuzhiyun #define SCMI_PKA_CRYPTO                25
464*4882a593Smuzhiyun #define SCMI_HCLK_CRYPTO               26
465*4882a593Smuzhiyun #define SCMI_CORE_CRYPTO_S             27
466*4882a593Smuzhiyun #define SCMI_ACLK_CRYPTO_S             28
467*4882a593Smuzhiyun #define SCMI_PKA_CRYPTO_S              29
468*4882a593Smuzhiyun #define SCMI_CORE_KLAD                 30
469*4882a593Smuzhiyun #define SCMI_ACLK_KLAD                 31
470*4882a593Smuzhiyun #define SCMI_HCLK_TRNG                 32
471*4882a593Smuzhiyun 
472*4882a593Smuzhiyun // CRU_SOFTRST_CON03(Offset:0xA0C)
473*4882a593Smuzhiyun #define SRST_NCOREPORESET0             0x00000030
474*4882a593Smuzhiyun #define SRST_NCOREPORESET1             0x00000031
475*4882a593Smuzhiyun #define SRST_NCOREPORESET2             0x00000032
476*4882a593Smuzhiyun #define SRST_NCOREPORESET3             0x00000033
477*4882a593Smuzhiyun #define SRST_NCORESET0                 0x00000034
478*4882a593Smuzhiyun #define SRST_NCORESET1                 0x00000035
479*4882a593Smuzhiyun #define SRST_NCORESET2                 0x00000036
480*4882a593Smuzhiyun #define SRST_NCORESET3                 0x00000037
481*4882a593Smuzhiyun #define SRST_NL2RESET                  0x00000038
482*4882a593Smuzhiyun #define SRST_ARESETN_M_CORE_BIU        0x00000039
483*4882a593Smuzhiyun #define SRST_RESETN_CORE_CRYPTO        0x0000003A
484*4882a593Smuzhiyun 
485*4882a593Smuzhiyun // CRU_SOFTRST_CON05(Offset:0xA14)
486*4882a593Smuzhiyun #define SRST_PRESETN_DBG               0x0000005D
487*4882a593Smuzhiyun #define SRST_POTRESETN_DBG             0x0000005E
488*4882a593Smuzhiyun #define SRST_NTRESETN_DBG              0x0000005F
489*4882a593Smuzhiyun 
490*4882a593Smuzhiyun // CRU_SOFTRST_CON06(Offset:0xA18)
491*4882a593Smuzhiyun #define SRST_PRESETN_CORE_GRF          0x00000062
492*4882a593Smuzhiyun #define SRST_PRESETN_DAPLITE_BIU       0x00000063
493*4882a593Smuzhiyun #define SRST_PRESETN_CPU_BIU           0x00000064
494*4882a593Smuzhiyun #define SRST_RESETN_REF_PVTPLL_CORE    0x00000067
495*4882a593Smuzhiyun 
496*4882a593Smuzhiyun // CRU_SOFTRST_CON08(Offset:0xA20)
497*4882a593Smuzhiyun #define SRST_ARESETN_BUS_VOPGL_BIU     0x00000081
498*4882a593Smuzhiyun #define SRST_ARESETN_BUS_H_BIU         0x00000083
499*4882a593Smuzhiyun #define SRST_ARESETN_SYSMEM_BIU        0x00000088
500*4882a593Smuzhiyun #define SRST_ARESETN_BUS_BIU           0x0000008A
501*4882a593Smuzhiyun #define SRST_HRESETN_BUS_BIU           0x0000008B
502*4882a593Smuzhiyun #define SRST_PRESETN_BUS_BIU           0x0000008C
503*4882a593Smuzhiyun #define SRST_PRESETN_DFT2APB           0x0000008D
504*4882a593Smuzhiyun #define SRST_PRESETN_BUS_GRF           0x0000008F
505*4882a593Smuzhiyun 
506*4882a593Smuzhiyun // CRU_SOFTRST_CON09(Offset:0xA24)
507*4882a593Smuzhiyun #define SRST_ARESETN_BUS_M_BIU         0x00000090
508*4882a593Smuzhiyun #define SRST_ARESETN_GIC               0x00000091
509*4882a593Smuzhiyun #define SRST_ARESETN_SPINLOCK          0x00000092
510*4882a593Smuzhiyun #define SRST_ARESETN_DMAC              0x00000094
511*4882a593Smuzhiyun #define SRST_PRESETN_TIMER             0x00000095
512*4882a593Smuzhiyun #define SRST_RESETN_TIMER0             0x00000096
513*4882a593Smuzhiyun #define SRST_RESETN_TIMER1             0x00000097
514*4882a593Smuzhiyun #define SRST_RESETN_TIMER2             0x00000098
515*4882a593Smuzhiyun #define SRST_RESETN_TIMER3             0x00000099
516*4882a593Smuzhiyun #define SRST_RESETN_TIMER4             0x0000009A
517*4882a593Smuzhiyun #define SRST_RESETN_TIMER5             0x0000009B
518*4882a593Smuzhiyun #define SRST_PRESETN_JDBCK_DAP         0x0000009C
519*4882a593Smuzhiyun #define SRST_RESETN_JDBCK_DAP          0x0000009D
520*4882a593Smuzhiyun #define SRST_PRESETN_WDT_NS            0x0000009F
521*4882a593Smuzhiyun 
522*4882a593Smuzhiyun // CRU_SOFTRST_CON10(Offset:0xA28)
523*4882a593Smuzhiyun #define SRST_TRESETN_WDT_NS            0x000000A0
524*4882a593Smuzhiyun #define SRST_HRESETN_TRNG_NS           0x000000A3
525*4882a593Smuzhiyun #define SRST_PRESETN_UART0             0x000000A7
526*4882a593Smuzhiyun #define SRST_SRESETN_UART0             0x000000A8
527*4882a593Smuzhiyun #define SRST_RESETN_PKA_CRYPTO         0x000000AA
528*4882a593Smuzhiyun #define SRST_ARESETN_CRYPTO            0x000000AB
529*4882a593Smuzhiyun #define SRST_HRESETN_CRYPTO            0x000000AC
530*4882a593Smuzhiyun #define SRST_PRESETN_DMA2DDR           0x000000AD
531*4882a593Smuzhiyun #define SRST_ARESETN_DMA2DDR           0x000000AE
532*4882a593Smuzhiyun 
533*4882a593Smuzhiyun // CRU_SOFTRST_CON11(Offset:0xA2C)
534*4882a593Smuzhiyun #define SRST_PRESETN_PWM0              0x000000B4
535*4882a593Smuzhiyun #define SRST_RESETN_PWM0               0x000000B5
536*4882a593Smuzhiyun #define SRST_PRESETN_PWM1              0x000000B7
537*4882a593Smuzhiyun #define SRST_RESETN_PWM1               0x000000B8
538*4882a593Smuzhiyun #define SRST_PRESETN_SCR               0x000000BA
539*4882a593Smuzhiyun #define SRST_ARESETN_DCF               0x000000BB
540*4882a593Smuzhiyun #define SRST_PRESETN_INTMUX            0x000000BC
541*4882a593Smuzhiyun 
542*4882a593Smuzhiyun // CRU_SOFTRST_CON25(Offset:0xA64)
543*4882a593Smuzhiyun #define SRST_ARESETN_VPU_BIU           0x00000196
544*4882a593Smuzhiyun #define SRST_HRESETN_VPU_BIU           0x00000197
545*4882a593Smuzhiyun #define SRST_PRESETN_VPU_BIU           0x00000198
546*4882a593Smuzhiyun #define SRST_ARESETN_VPU               0x00000199
547*4882a593Smuzhiyun #define SRST_HRESETN_VPU               0x0000019A
548*4882a593Smuzhiyun #define SRST_PRESETN_CRU_PCIE          0x0000019B
549*4882a593Smuzhiyun #define SRST_PRESETN_VPU_GRF           0x0000019C
550*4882a593Smuzhiyun #define SRST_HRESETN_SFC               0x0000019D
551*4882a593Smuzhiyun #define SRST_SRESETN_SFC               0x0000019E
552*4882a593Smuzhiyun #define SRST_CRESETN_EMMC              0x0000019F
553*4882a593Smuzhiyun 
554*4882a593Smuzhiyun // CRU_SOFTRST_CON26(Offset:0xA68)
555*4882a593Smuzhiyun #define SRST_HRESETN_EMMC              0x000001A0
556*4882a593Smuzhiyun #define SRST_ARESETN_EMMC              0x000001A1
557*4882a593Smuzhiyun #define SRST_BRESETN_EMMC              0x000001A2
558*4882a593Smuzhiyun #define SRST_TRESETN_EMMC              0x000001A3
559*4882a593Smuzhiyun #define SRST_PRESETN_GPIO1             0x000001A4
560*4882a593Smuzhiyun #define SRST_DBRESETN_GPIO1            0x000001A5
561*4882a593Smuzhiyun #define SRST_ARESETN_VPU_L_BIU         0x000001A6
562*4882a593Smuzhiyun #define SRST_PRESETN_VPU_IOC           0x000001A8
563*4882a593Smuzhiyun #define SRST_HRESETN_SAI_I2S0          0x000001A9
564*4882a593Smuzhiyun #define SRST_MRESETN_SAI_I2S0          0x000001AA
565*4882a593Smuzhiyun #define SRST_HRESETN_SAI_I2S2          0x000001AB
566*4882a593Smuzhiyun #define SRST_MRESETN_SAI_I2S2          0x000001AC
567*4882a593Smuzhiyun #define SRST_PRESETN_ACODEC            0x000001AD
568*4882a593Smuzhiyun 
569*4882a593Smuzhiyun // CRU_SOFTRST_CON27(Offset:0xA6C)
570*4882a593Smuzhiyun #define SRST_PRESETN_GPIO3             0x000001B0
571*4882a593Smuzhiyun #define SRST_DBRESETN_GPIO3            0x000001B1
572*4882a593Smuzhiyun #define SRST_PRESETN_SPI1              0x000001B4
573*4882a593Smuzhiyun #define SRST_RESETN_SPI1               0x000001B5
574*4882a593Smuzhiyun #define SRST_PRESETN_UART2             0x000001B7
575*4882a593Smuzhiyun #define SRST_SRESETN_UART2             0x000001B8
576*4882a593Smuzhiyun #define SRST_PRESETN_UART5             0x000001B9
577*4882a593Smuzhiyun #define SRST_SRESETN_UART5             0x000001BA
578*4882a593Smuzhiyun #define SRST_PRESETN_UART6             0x000001BB
579*4882a593Smuzhiyun #define SRST_SRESETN_UART6             0x000001BC
580*4882a593Smuzhiyun #define SRST_PRESETN_UART7             0x000001BD
581*4882a593Smuzhiyun #define SRST_SRESETN_UART7             0x000001BE
582*4882a593Smuzhiyun #define SRST_PRESETN_I2C3              0x000001BF
583*4882a593Smuzhiyun 
584*4882a593Smuzhiyun // CRU_SOFTRST_CON28(Offset:0xA70)
585*4882a593Smuzhiyun #define SRST_RESETN_I2C3               0x000001C0
586*4882a593Smuzhiyun #define SRST_PRESETN_I2C5              0x000001C1
587*4882a593Smuzhiyun #define SRST_RESETN_I2C5               0x000001C2
588*4882a593Smuzhiyun #define SRST_PRESETN_I2C6              0x000001C3
589*4882a593Smuzhiyun #define SRST_RESETN_I2C6               0x000001C4
590*4882a593Smuzhiyun #define SRST_ARESETN_MAC               0x000001C5
591*4882a593Smuzhiyun 
592*4882a593Smuzhiyun // CRU_SOFTRST_CON30(Offset:0xA78)
593*4882a593Smuzhiyun #define SRST_PRESETN_PCIE              0x000001E1
594*4882a593Smuzhiyun #define SRST_RESETN_PCIE_PIPE_PHY      0x000001E2
595*4882a593Smuzhiyun #define SRST_RESETN_PCIE_POWER_UP      0x000001E3
596*4882a593Smuzhiyun #define SRST_PRESETN_PCIE_PHY          0x000001E6
597*4882a593Smuzhiyun #define SRST_PRESETN_PIPE_GRF          0x000001E7
598*4882a593Smuzhiyun 
599*4882a593Smuzhiyun // CRU_SOFTRST_CON32(Offset:0xA80)
600*4882a593Smuzhiyun #define SRST_HRESETN_SDIO0             0x00000202
601*4882a593Smuzhiyun #define SRST_HRESETN_SDIO1             0x00000204
602*4882a593Smuzhiyun #define SRST_RESETN_TS_0               0x00000205
603*4882a593Smuzhiyun #define SRST_RESETN_TS_1               0x00000206
604*4882a593Smuzhiyun #define SRST_PRESETN_CAN2              0x00000207
605*4882a593Smuzhiyun #define SRST_RESETN_CAN2               0x00000208
606*4882a593Smuzhiyun #define SRST_PRESETN_CAN3              0x00000209
607*4882a593Smuzhiyun #define SRST_RESETN_CAN3               0x0000020A
608*4882a593Smuzhiyun #define SRST_PRESETN_SARADC            0x0000020B
609*4882a593Smuzhiyun #define SRST_RESETN_SARADC             0x0000020C
610*4882a593Smuzhiyun #define SRST_RESETN_SARADC_PHY         0x0000020D
611*4882a593Smuzhiyun #define SRST_PRESETN_TSADC             0x0000020E
612*4882a593Smuzhiyun #define SRST_RESETN_TSADC              0x0000020F
613*4882a593Smuzhiyun 
614*4882a593Smuzhiyun // CRU_SOFTRST_CON33(Offset:0xA84)
615*4882a593Smuzhiyun #define SRST_ARESETN_USB3OTG           0x00000211
616*4882a593Smuzhiyun 
617*4882a593Smuzhiyun // CRU_SOFTRST_CON34(Offset:0xA88)
618*4882a593Smuzhiyun #define SRST_ARESETN_GPU_BIU           0x00000223
619*4882a593Smuzhiyun #define SRST_PRESETN_GPU_BIU           0x00000225
620*4882a593Smuzhiyun #define SRST_ARESETN_GPU               0x00000228
621*4882a593Smuzhiyun #define SRST_RESETN_REF_PVTPLL_GPU     0x00000229
622*4882a593Smuzhiyun 
623*4882a593Smuzhiyun // CRU_SOFTRST_CON36(Offset:0xA90)
624*4882a593Smuzhiyun #define SRST_HRESETN_RKVENC_BIU        0x00000243
625*4882a593Smuzhiyun #define SRST_ARESETN_RKVENC_BIU        0x00000244
626*4882a593Smuzhiyun #define SRST_PRESETN_RKVENC_BIU        0x00000245
627*4882a593Smuzhiyun #define SRST_HRESETN_RKVENC            0x00000246
628*4882a593Smuzhiyun #define SRST_ARESETN_RKVENC            0x00000247
629*4882a593Smuzhiyun #define SRST_RESETN_CORE_RKVENC        0x00000248
630*4882a593Smuzhiyun #define SRST_HRESETN_SAI_I2S1          0x00000249
631*4882a593Smuzhiyun #define SRST_MRESETN_SAI_I2S1          0x0000024A
632*4882a593Smuzhiyun #define SRST_PRESETN_I2C1              0x0000024B
633*4882a593Smuzhiyun #define SRST_RESETN_I2C1               0x0000024C
634*4882a593Smuzhiyun #define SRST_PRESETN_I2C0              0x0000024D
635*4882a593Smuzhiyun #define SRST_RESETN_I2C0               0x0000024E
636*4882a593Smuzhiyun 
637*4882a593Smuzhiyun // CRU_SOFTRST_CON37(Offset:0xA94)
638*4882a593Smuzhiyun #define SRST_PRESETN_SPI0              0x00000252
639*4882a593Smuzhiyun #define SRST_RESETN_SPI0               0x00000253
640*4882a593Smuzhiyun #define SRST_PRESETN_GPIO4             0x00000258
641*4882a593Smuzhiyun #define SRST_DBRESETN_GPIO4            0x00000259
642*4882a593Smuzhiyun #define SRST_PRESETN_RKVENC_IOC        0x0000025A
643*4882a593Smuzhiyun #define SRST_HRESETN_SPDIF             0x0000025E
644*4882a593Smuzhiyun #define SRST_MRESETN_SPDIF             0x0000025F
645*4882a593Smuzhiyun 
646*4882a593Smuzhiyun // CRU_SOFTRST_CON38(Offset:0xA98)
647*4882a593Smuzhiyun #define SRST_HRESETN_PDM               0x00000260
648*4882a593Smuzhiyun #define SRST_MRESETN_PDM               0x00000261
649*4882a593Smuzhiyun #define SRST_PRESETN_UART1             0x00000262
650*4882a593Smuzhiyun #define SRST_SRESETN_UART1             0x00000263
651*4882a593Smuzhiyun #define SRST_PRESETN_UART3             0x00000264
652*4882a593Smuzhiyun #define SRST_SRESETN_UART3             0x00000265
653*4882a593Smuzhiyun #define SRST_PRESETN_RKVENC_GRF        0x00000266
654*4882a593Smuzhiyun #define SRST_PRESETN_CAN0              0x00000267
655*4882a593Smuzhiyun #define SRST_RESETN_CAN0               0x00000268
656*4882a593Smuzhiyun #define SRST_PRESETN_CAN1              0x00000269
657*4882a593Smuzhiyun #define SRST_RESETN_CAN1               0x0000026A
658*4882a593Smuzhiyun 
659*4882a593Smuzhiyun // CRU_SOFTRST_CON39(Offset:0xA9C)
660*4882a593Smuzhiyun #define SRST_ARESETN_VO_BIU            0x00000273
661*4882a593Smuzhiyun #define SRST_HRESETN_VO_BIU            0x00000274
662*4882a593Smuzhiyun #define SRST_PRESETN_VO_BIU            0x00000275
663*4882a593Smuzhiyun #define SRST_HRESETN_RGA2E             0x00000277
664*4882a593Smuzhiyun #define SRST_ARESETN_RGA2E             0x00000278
665*4882a593Smuzhiyun #define SRST_RESETN_CORE_RGA2E         0x00000279
666*4882a593Smuzhiyun #define SRST_HRESETN_VDPP              0x0000027A
667*4882a593Smuzhiyun #define SRST_ARESETN_VDPP              0x0000027B
668*4882a593Smuzhiyun #define SRST_RESETN_CORE_VDPP          0x0000027C
669*4882a593Smuzhiyun #define SRST_PRESETN_VO_GRF            0x0000027D
670*4882a593Smuzhiyun #define SRST_PRESETN_CRU               0x0000027F
671*4882a593Smuzhiyun 
672*4882a593Smuzhiyun // CRU_SOFTRST_CON40(Offset:0xAA0)
673*4882a593Smuzhiyun #define SRST_ARESETN_VOP_BIU           0x00000281
674*4882a593Smuzhiyun #define SRST_HRESETN_VOP               0x00000282
675*4882a593Smuzhiyun #define SRST_DRESETN_VOP0              0x00000283
676*4882a593Smuzhiyun #define SRST_DRESETN_VOP1              0x00000284
677*4882a593Smuzhiyun #define SRST_ARESETN_VOP               0x00000285
678*4882a593Smuzhiyun #define SRST_PRESETN_HDMI              0x00000286
679*4882a593Smuzhiyun #define SRST_HDMI_RESETN               0x00000287
680*4882a593Smuzhiyun #define SRST_PRESETN_HDMIPHY           0x0000028E
681*4882a593Smuzhiyun #define SRST_HRESETN_HDCP_KEY          0x0000028F
682*4882a593Smuzhiyun 
683*4882a593Smuzhiyun // CRU_SOFTRST_CON41(Offset:0xAA4)
684*4882a593Smuzhiyun #define SRST_ARESETN_HDCP              0x00000290
685*4882a593Smuzhiyun #define SRST_HRESETN_HDCP              0x00000291
686*4882a593Smuzhiyun #define SRST_PRESETN_HDCP              0x00000292
687*4882a593Smuzhiyun #define SRST_HRESETN_CVBS              0x00000293
688*4882a593Smuzhiyun #define SRST_DRESETN_CVBS_VOP          0x00000294
689*4882a593Smuzhiyun #define SRST_DRESETN_4X_CVBS_VOP       0x00000295
690*4882a593Smuzhiyun #define SRST_ARESETN_JPEG_DECODER      0x00000296
691*4882a593Smuzhiyun #define SRST_HRESETN_JPEG_DECODER      0x00000297
692*4882a593Smuzhiyun #define SRST_ARESETN_VO_L_BIU          0x00000299
693*4882a593Smuzhiyun #define SRST_ARESETN_MAC_VO            0x0000029A
694*4882a593Smuzhiyun 
695*4882a593Smuzhiyun // CRU_SOFTRST_CON42(Offset:0xAA8)
696*4882a593Smuzhiyun #define SRST_ARESETN_JPEG_BIU          0x000002A0
697*4882a593Smuzhiyun #define SRST_HRESETN_SAI_I2S3          0x000002A1
698*4882a593Smuzhiyun #define SRST_MRESETN_SAI_I2S3          0x000002A2
699*4882a593Smuzhiyun #define SRST_RESETN_MACPHY             0x000002A3
700*4882a593Smuzhiyun #define SRST_PRESETN_VCDCPHY           0x000002A4
701*4882a593Smuzhiyun #define SRST_PRESETN_GPIO2             0x000002A5
702*4882a593Smuzhiyun #define SRST_DBRESETN_GPIO2            0x000002A6
703*4882a593Smuzhiyun #define SRST_PRESETN_VO_IOC            0x000002A7
704*4882a593Smuzhiyun #define SRST_HRESETN_SDMMC0            0x000002A9
705*4882a593Smuzhiyun #define SRST_PRESETN_OTPC_NS           0x000002AB
706*4882a593Smuzhiyun #define SRST_RESETN_SBPI_OTPC_NS       0x000002AC
707*4882a593Smuzhiyun #define SRST_RESETN_USER_OTPC_NS       0x000002AD
708*4882a593Smuzhiyun 
709*4882a593Smuzhiyun // CRU_SOFTRST_CON43(Offset:0xAAC)
710*4882a593Smuzhiyun #define SRST_RESETN_HDMIHDP0           0x000002B2
711*4882a593Smuzhiyun #define SRST_HRESETN_USBHOST           0x000002B3
712*4882a593Smuzhiyun #define SRST_HRESETN_USBHOST_ARB       0x000002B4
713*4882a593Smuzhiyun #define SRST_RESETN_HOST_UTMI          0x000002B6
714*4882a593Smuzhiyun #define SRST_PRESETN_UART4             0x000002B7
715*4882a593Smuzhiyun #define SRST_SRESETN_UART4             0x000002B8
716*4882a593Smuzhiyun #define SRST_PRESETN_I2C4              0x000002B9
717*4882a593Smuzhiyun #define SRST_RESETN_I2C4               0x000002BA
718*4882a593Smuzhiyun #define SRST_PRESETN_I2C7              0x000002BB
719*4882a593Smuzhiyun #define SRST_RESETN_I2C7               0x000002BC
720*4882a593Smuzhiyun #define SRST_PRESETN_USBPHY            0x000002BD
721*4882a593Smuzhiyun #define SRST_RESETN_USBPHY_POR         0x000002BE
722*4882a593Smuzhiyun #define SRST_RESETN_USBPHY_OTG         0x000002BF
723*4882a593Smuzhiyun 
724*4882a593Smuzhiyun // CRU_SOFTRST_CON44(Offset:0xAB0)
725*4882a593Smuzhiyun #define SRST_RESETN_USBPHY_HOST        0x000002C0
726*4882a593Smuzhiyun #define SRST_PRESETN_DDRPHY_CRU        0x000002C4
727*4882a593Smuzhiyun #define SRST_HRESETN_RKVDEC_BIU        0x000002C6
728*4882a593Smuzhiyun #define SRST_ARESETN_RKVDEC_BIU        0x000002C7
729*4882a593Smuzhiyun #define SRST_ARESETN_RKVDEC            0x000002C8
730*4882a593Smuzhiyun #define SRST_HRESETN_RKVDEC            0x000002C9
731*4882a593Smuzhiyun #define SRST_RESETN_HEVC_CA_RKVDEC     0x000002CB
732*4882a593Smuzhiyun #define SRST_RESETN_REF_PVTPLL_RKVDEC  0x000002CC
733*4882a593Smuzhiyun 
734*4882a593Smuzhiyun // CRU_SOFTRST_CON45(Offset:0xAB4)
735*4882a593Smuzhiyun #define SRST_PRESETN_DDR_BIU           0x000002D1
736*4882a593Smuzhiyun #define SRST_PRESETN_DDRC              0x000002D2
737*4882a593Smuzhiyun #define SRST_PRESETN_DDRMON            0x000002D3
738*4882a593Smuzhiyun #define SRST_RESETN_TIMER_DDRMON       0x000002D4
739*4882a593Smuzhiyun #define SRST_PRESETN_MSCH_BIU          0x000002D5
740*4882a593Smuzhiyun #define SRST_PRESETN_DDR_GRF           0x000002D6
741*4882a593Smuzhiyun #define SRST_PRESETN_DDR_HWLP          0x000002D8
742*4882a593Smuzhiyun #define SRST_PRESETN_DDRPHY            0x000002D9
743*4882a593Smuzhiyun #define SRST_RESETN_MSCH_BIU           0x000002DA
744*4882a593Smuzhiyun #define SRST_ARESETN_DDR_UPCTL         0x000002DB
745*4882a593Smuzhiyun #define SRST_RESETN_DDR_UPCTL          0x000002DC
746*4882a593Smuzhiyun #define SRST_RESETN_DDRMON             0x000002DD
747*4882a593Smuzhiyun #define SRST_ARESETN_DDR_SCRAMBLE      0x000002DE
748*4882a593Smuzhiyun #define SRST_ARESETN_SPLIT             0x000002DF
749*4882a593Smuzhiyun 
750*4882a593Smuzhiyun // CRU_SOFTRST_CON46(Offset:0xAB8)
751*4882a593Smuzhiyun #define SRST_RESETN_DDR_PHY            0x000002E0
752*4882a593Smuzhiyun 
753*4882a593Smuzhiyun #endif
754*4882a593Smuzhiyun 
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