1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 /* 3 * Copyright (c) 2022 Rockchip Electronics Co. Ltd. 4 * Author: Joseph Chen <chenjh@rock-chips.com> 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H 8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H 9 10 /* cru-clocks indices */ 11 12 /* core clocks */ 13 #define PLL_APLL 1 14 #define PLL_CPLL 2 15 #define PLL_GPLL 3 16 #define PLL_PPLL 4 17 #define PLL_DPLL 5 18 #define ARMCLK 6 19 20 #define XIN_OSC0_HALF 8 21 #define CLK_MATRIX_50M_SRC 9 22 #define CLK_MATRIX_100M_SRC 10 23 #define CLK_MATRIX_150M_SRC 11 24 #define CLK_MATRIX_200M_SRC 12 25 #define CLK_MATRIX_250M_SRC 13 26 #define CLK_MATRIX_300M_SRC 14 27 #define CLK_MATRIX_339M_SRC 15 28 #define CLK_MATRIX_400M_SRC 16 29 #define CLK_MATRIX_500M_SRC 17 30 #define CLK_MATRIX_600M_SRC 18 31 #define CLK_UART0_SRC 19 32 #define CLK_UART0_FRAC 20 33 #define SCLK_UART0 21 34 #define CLK_UART1_SRC 22 35 #define CLK_UART1_FRAC 23 36 #define SCLK_UART1 24 37 #define CLK_UART2_SRC 25 38 #define CLK_UART2_FRAC 26 39 #define SCLK_UART2 27 40 #define CLK_UART3_SRC 28 41 #define CLK_UART3_FRAC 29 42 #define SCLK_UART3 30 43 #define CLK_UART4_SRC 31 44 #define CLK_UART4_FRAC 32 45 #define SCLK_UART4 33 46 #define CLK_UART5_SRC 34 47 #define CLK_UART5_FRAC 35 48 #define SCLK_UART5 36 49 #define CLK_UART6_SRC 37 50 #define CLK_UART6_FRAC 38 51 #define SCLK_UART6 39 52 #define CLK_UART7_SRC 40 53 #define CLK_UART7_FRAC 41 54 #define SCLK_UART7 42 55 #define CLK_I2S0_2CH_SRC 43 56 #define CLK_I2S0_2CH_FRAC 44 57 #define MCLK_I2S0_2CH_SAI_SRC 45 58 #define CLK_I2S3_8CH_SRC 46 59 #define CLK_I2S3_8CH_FRAC 47 60 #define MCLK_I2S3_8CH_SAI_SRC 48 61 #define CLK_I2S1_8CH_SRC 49 62 #define CLK_I2S1_8CH_FRAC 50 63 #define MCLK_I2S1_8CH_SAI_SRC 51 64 #define CLK_I2S2_2CH_SRC 52 65 #define CLK_I2S2_2CH_FRAC 53 66 #define MCLK_I2S2_2CH_SAI_SRC 54 67 #define CLK_SPDIF_SRC 55 68 #define CLK_SPDIF_FRAC 56 69 #define MCLK_SPDIF_SRC 57 70 #define DCLK_VOP_SRC0 58 71 #define DCLK_VOP_SRC1 59 72 #define CLK_HSM 60 73 #define CLK_CORE_SRC_ACS 63 74 #define CLK_CORE_SRC_PVTMUX 65 75 #define CLK_CORE_SRC 66 76 #define CLK_CORE 67 77 #define ACLK_M_CORE_BIU 68 78 #define CLK_CORE_PVTPLL_SRC 69 79 #define PCLK_DBG 70 80 #define SWCLKTCK 71 81 #define CLK_SCANHS_CORE 72 82 #define CLK_SCANHS_ACLKM_CORE 73 83 #define CLK_SCANHS_PCLK_DBG 74 84 #define CLK_SCANHS_PCLK_CPU_BIU 76 85 #define PCLK_CPU_ROOT 77 86 #define PCLK_CORE_GRF 78 87 #define PCLK_DAPLITE_BIU 79 88 #define PCLK_CPU_BIU 80 89 #define CLK_REF_PVTPLL_CORE 81 90 #define ACLK_BUS_VOPGL_ROOT 85 91 #define ACLK_BUS_VOPGL_BIU 86 92 #define ACLK_BUS_H_ROOT 87 93 #define ACLK_BUS_H_BIU 88 94 #define ACLK_BUS_ROOT 89 95 #define HCLK_BUS_ROOT 90 96 #define PCLK_BUS_ROOT 91 97 #define ACLK_BUS_M_ROOT 92 98 #define ACLK_SYSMEM_BIU 93 99 #define CLK_TIMER_ROOT 95 100 #define ACLK_BUS_BIU 96 101 #define HCLK_BUS_BIU 97 102 #define PCLK_BUS_BIU 98 103 #define PCLK_DFT2APB 99 104 #define PCLK_BUS_GRF 100 105 #define ACLK_BUS_M_BIU 101 106 #define ACLK_GIC 102 107 #define ACLK_SPINLOCK 103 108 #define ACLK_DMAC 104 109 #define PCLK_TIMER 105 110 #define CLK_TIMER0 106 111 #define CLK_TIMER1 107 112 #define CLK_TIMER2 108 113 #define CLK_TIMER3 109 114 #define CLK_TIMER4 110 115 #define CLK_TIMER5 111 116 #define PCLK_JDBCK_DAP 112 117 #define CLK_JDBCK_DAP 113 118 #define PCLK_WDT_NS 114 119 #define TCLK_WDT_NS 115 120 #define HCLK_TRNG_NS 116 121 #define PCLK_UART0 117 122 #define CLK_CORE_CRYPTO 119 123 #define CLK_PKA_CRYPTO 120 124 #define ACLK_CRYPTO 121 125 #define HCLK_CRYPTO 122 126 #define PCLK_DMA2DDR 123 127 #define ACLK_DMA2DDR 124 128 #define PCLK_PWM0 126 129 #define CLK_PWM0 127 130 #define CLK_CAPTURE_PWM0 128 131 #define PCLK_PWM1 129 132 #define CLK_PWM1 130 133 #define CLK_CAPTURE_PWM1 131 134 #define PCLK_SCR 134 135 #define ACLK_DCF 135 136 #define PCLK_INTMUX 138 137 #define CLK_PPLL_I 141 138 #define CLK_PPLL_MUX 142 139 #define CLK_PPLL_100M_MATRIX 143 140 #define CLK_PPLL_50M_MATRIX 144 141 #define CLK_REF_PCIE_INNER_PHY 145 142 #define CLK_REF_PCIE_100M_PHY 146 143 #define ACLK_VPU_L_ROOT 147 144 #define CLK_GMAC1_VPU_25M 148 145 #define CLK_PPLL_125M_MATRIX 149 146 #define ACLK_VPU_ROOT 150 147 #define HCLK_VPU_ROOT 151 148 #define PCLK_VPU_ROOT 152 149 #define ACLK_VPU_BIU 153 150 #define HCLK_VPU_BIU 154 151 #define PCLK_VPU_BIU 155 152 #define ACLK_VPU 156 153 #define HCLK_VPU 157 154 #define PCLK_CRU_PCIE 158 155 #define PCLK_VPU_GRF 159 156 #define HCLK_SFC 160 157 #define SCLK_SFC 161 158 #define CCLK_SRC_EMMC 163 159 #define HCLK_EMMC 164 160 #define ACLK_EMMC 165 161 #define BCLK_EMMC 166 162 #define TCLK_EMMC 167 163 #define PCLK_GPIO1 168 164 #define DBCLK_GPIO1 169 165 #define ACLK_VPU_L_BIU 172 166 #define PCLK_VPU_IOC 173 167 #define HCLK_SAI_I2S0 174 168 #define MCLK_SAI_I2S0 175 169 #define HCLK_SAI_I2S2 176 170 #define MCLK_SAI_I2S2 177 171 #define PCLK_ACODEC 178 172 #define MCLK_ACODEC_TX 179 173 #define PCLK_GPIO3 186 174 #define DBCLK_GPIO3 187 175 #define PCLK_SPI1 189 176 #define CLK_SPI1 190 177 #define SCLK_IN_SPI1 191 178 #define PCLK_UART2 192 179 #define PCLK_UART5 194 180 #define PCLK_UART6 196 181 #define PCLK_UART7 198 182 #define PCLK_I2C3 200 183 #define CLK_I2C3 201 184 #define PCLK_I2C5 202 185 #define CLK_I2C5 203 186 #define PCLK_I2C6 204 187 #define CLK_I2C6 205 188 #define ACLK_MAC_VPU 206 189 #define PCLK_MAC_VPU 207 190 #define CLK_GMAC1_RMII_VPU 209 191 #define CLK_GMAC1_SRC_VPU 210 192 #define PCLK_PCIE 215 193 #define CLK_PCIE_AUX 216 194 #define ACLK_PCIE 217 195 #define HCLK_PCIE_SLV 218 196 #define HCLK_PCIE_DBI 219 197 #define PCLK_PCIE_PHY 220 198 #define PCLK_PIPE_GRF 221 199 #define CLK_PIPE_USB3OTG_COMBO 230 200 #define CLK_UTMI_USB3OTG 232 201 #define CLK_PCIE_PIPE_PHY 235 202 #define CCLK_SRC_SDIO0 240 203 #define HCLK_SDIO0 241 204 #define CCLK_SRC_SDIO1 244 205 #define HCLK_SDIO1 245 206 #define CLK_TS_0 246 207 #define CLK_TS_1 247 208 #define PCLK_CAN2 250 209 #define CLK_CAN2 251 210 #define PCLK_CAN3 252 211 #define CLK_CAN3 253 212 #define PCLK_SARADC 256 213 #define CLK_SARADC 257 214 #define PCLK_TSADC 258 215 #define CLK_TSADC 259 216 #define CLK_TSADC_TSEN 260 217 #define ACLK_USB3OTG 261 218 #define CLK_REF_USB3OTG 262 219 #define CLK_SUSPEND_USB3OTG 263 220 #define ACLK_GPU_ROOT 269 221 #define PCLK_GPU_ROOT 270 222 #define ACLK_GPU_BIU 271 223 #define PCLK_GPU_BIU 272 224 #define ACLK_GPU 273 225 #define CLK_GPU_PVTPLL_SRC 274 226 #define ACLK_GPU_MALI 275 227 #define HCLK_RKVENC_ROOT 281 228 #define ACLK_RKVENC_ROOT 282 229 #define PCLK_RKVENC_ROOT 283 230 #define HCLK_RKVENC_BIU 284 231 #define ACLK_RKVENC_BIU 285 232 #define PCLK_RKVENC_BIU 286 233 #define HCLK_RKVENC 287 234 #define ACLK_RKVENC 288 235 #define CLK_CORE_RKVENC 289 236 #define HCLK_SAI_I2S1 290 237 #define MCLK_SAI_I2S1 291 238 #define PCLK_I2C1 292 239 #define CLK_I2C1 293 240 #define PCLK_I2C0 294 241 #define CLK_I2C0 295 242 #define CLK_UART_JTAG 296 243 #define PCLK_SPI0 297 244 #define CLK_SPI0 298 245 #define SCLK_IN_SPI0 299 246 #define PCLK_GPIO4 300 247 #define DBCLK_GPIO4 301 248 #define PCLK_RKVENC_IOC 302 249 #define HCLK_SPDIF 308 250 #define MCLK_SPDIF 309 251 #define HCLK_PDM 310 252 #define MCLK_PDM 311 253 #define PCLK_UART1 315 254 #define PCLK_UART3 317 255 #define PCLK_RKVENC_GRF 319 256 #define PCLK_CAN0 320 257 #define CLK_CAN0 321 258 #define PCLK_CAN1 322 259 #define CLK_CAN1 323 260 #define ACLK_VO_ROOT 324 261 #define HCLK_VO_ROOT 325 262 #define PCLK_VO_ROOT 326 263 #define ACLK_VO_BIU 327 264 #define HCLK_VO_BIU 328 265 #define PCLK_VO_BIU 329 266 #define HCLK_RGA2E 330 267 #define ACLK_RGA2E 331 268 #define CLK_CORE_RGA2E 332 269 #define HCLK_VDPP 333 270 #define ACLK_VDPP 334 271 #define CLK_CORE_VDPP 335 272 #define PCLK_VO_GRF 336 273 #define PCLK_CRU 337 274 #define ACLK_VOP_ROOT 338 275 #define ACLK_VOP_BIU 339 276 #define HCLK_VOP 340 277 #define DCLK_VOP0 341 278 #define DCLK_VOP1 342 279 #define ACLK_VOP 343 280 #define PCLK_HDMI 344 281 #define CLK_SFR_HDMI 345 282 #define CLK_CEC_HDMI 346 283 #define CLK_SPDIF_HDMI 347 284 #define CLK_HDMIPHY_TMDSSRC 348 285 #define CLK_HDMIPHY_PREP 349 286 #define PCLK_HDMIPHY 352 287 #define HCLK_HDCP_KEY 354 288 #define ACLK_HDCP 355 289 #define HCLK_HDCP 356 290 #define PCLK_HDCP 357 291 #define HCLK_CVBS 358 292 #define DCLK_CVBS 359 293 #define DCLK_4X_CVBS 360 294 #define ACLK_JPEG_DECODER 361 295 #define HCLK_JPEG_DECODER 362 296 #define ACLK_VO_L_ROOT 375 297 #define ACLK_VO_L_BIU 376 298 #define ACLK_MAC_VO 377 299 #define PCLK_MAC_VO 378 300 #define CLK_GMAC0_SRC 379 301 #define CLK_GMAC0_RMII_50M 380 302 #define CLK_GMAC0_TX 381 303 #define CLK_GMAC0_RX 382 304 #define ACLK_JPEG_ROOT 385 305 #define ACLK_JPEG_BIU 386 306 #define HCLK_SAI_I2S3 387 307 #define MCLK_SAI_I2S3 388 308 #define CLK_MACPHY 398 309 #define PCLK_VCDCPHY 399 310 #define PCLK_GPIO2 404 311 #define DBCLK_GPIO2 405 312 #define PCLK_VO_IOC 406 313 #define CCLK_SRC_SDMMC0 407 314 #define HCLK_SDMMC0 408 315 #define PCLK_OTPC_NS 411 316 #define CLK_SBPI_OTPC_NS 412 317 #define CLK_USER_OTPC_NS 413 318 #define CLK_HDMIHDP0 415 319 #define HCLK_USBHOST 416 320 #define HCLK_USBHOST_ARB 417 321 #define CLK_USBHOST_OHCI 418 322 #define CLK_USBHOST_UTMI 419 323 #define PCLK_UART4 420 324 #define PCLK_I2C4 422 325 #define CLK_I2C4 423 326 #define PCLK_I2C7 424 327 #define CLK_I2C7 425 328 #define PCLK_USBPHY 426 329 #define CLK_REF_USBPHY 427 330 #define HCLK_RKVDEC_ROOT 433 331 #define ACLK_RKVDEC_ROOT_NDFT 434 332 #define PCLK_DDRPHY_CRU 435 333 #define HCLK_RKVDEC_BIU 436 334 #define ACLK_RKVDEC_BIU 437 335 #define ACLK_RKVDEC 439 336 #define HCLK_RKVDEC 440 337 #define CLK_HEVC_CA_RKVDEC 441 338 #define ACLK_RKVDEC_PVTMUX_ROOT 442 339 #define CLK_RKVDEC_PVTPLL_SRC 443 340 #define PCLK_DDR_ROOT 449 341 #define PCLK_DDR_BIU 450 342 #define PCLK_DDRC 451 343 #define PCLK_DDRMON 452 344 #define CLK_TIMER_DDRMON 453 345 #define PCLK_MSCH_BIU 454 346 #define PCLK_DDR_GRF 455 347 #define PCLK_DDR_HWLP 456 348 #define PCLK_DDRPHY 457 349 #define CLK_MSCH_BIU 463 350 #define ACLK_DDR_UPCTL 464 351 #define CLK_DDR_UPCTL 465 352 #define CLK_DDRMON 466 353 #define ACLK_DDR_SCRAMBLE 467 354 #define ACLK_SPLIT 468 355 #define CLK_DDRC_SRC 470 356 #define CLK_DDR_PHY 471 357 #define PCLK_OTPC_S 472 358 #define CLK_SBPI_OTPC_S 473 359 #define CLK_USER_OTPC_S 474 360 #define PCLK_KEYREADER 475 361 #define PCLK_BUS_SGRF 476 362 #define PCLK_STIMER 477 363 #define CLK_STIMER0 478 364 #define CLK_STIMER1 479 365 #define PCLK_WDT_S 480 366 #define TCLK_WDT_S 481 367 #define HCLK_TRNG_S 482 368 #define PCLK_KLAD 483 369 #define HCLK_CRYPTO_S 484 370 #define HCLK_KLAD 485 371 #define HCLK_BOOTROM 486 372 #define PCLK_DCF 487 373 #define ACLK_SYSMEM 488 374 #define HCLK_TSP 489 375 #define ACLK_TSP 490 376 #define CLK_CORE_TSP 491 377 #define CLK_OTPC_ARB 492 378 #define PCLK_OTP_MASK 493 379 #define CLK_PMC_OTP 494 380 #define PCLK_PMU_ROOT 495 381 #define HCLK_PMU_ROOT 496 382 #define PCLK_I2C2 497 383 #define CLK_I2C2 498 384 #define HCLK_PMU_BIU 500 385 #define PCLK_PMU_BIU 501 386 #define FCLK_MCU 502 387 #define RTC_CLK_MCU 504 388 #define PCLK_OSCCHK 505 389 #define CLK_PMU_MCU_JTAG 506 390 #define PCLK_PMU 508 391 #define PCLK_GPIO0 509 392 #define DBCLK_GPIO0 510 393 #define XIN_OSC0_DIV 511 394 #define CLK_DEEPSLOW 512 395 #define CLK_DDR_FAIL_SAFE 513 396 #define PCLK_PMU_HP_TIMER 514 397 #define CLK_PMU_HP_TIMER 515 398 #define CLK_PMU_32K_HP_TIMER 516 399 #define PCLK_PMU_IOC 517 400 #define PCLK_PMU_CRU 518 401 #define PCLK_PMU_GRF 519 402 #define PCLK_PMU_WDT 520 403 #define TCLK_PMU_WDT 521 404 #define PCLK_PMU_MAILBOX 522 405 #define PCLK_SCRKEYGEN 524 406 #define CLK_SCRKEYGEN 525 407 #define CLK_PVTM_OSCCHK 526 408 #define CLK_REFOUT 530 409 #define CLK_PVTM_PMU 532 410 #define PCLK_PVTM_PMU 533 411 #define PCLK_PMU_SGRF 534 412 #define HCLK_PMU_SRAM 535 413 #define CLK_UART0 536 414 #define CLK_UART1 537 415 #define CLK_UART2 538 416 #define CLK_UART3 539 417 #define CLK_UART4 540 418 #define CLK_UART5 541 419 #define CLK_UART6 542 420 #define CLK_UART7 543 421 #define MCLK_I2S0_2CH_SAI_SRC_PRE 544 422 #define MCLK_I2S1_8CH_SAI_SRC_PRE 545 423 #define MCLK_I2S2_2CH_SAI_SRC_PRE 546 424 #define MCLK_I2S3_8CH_SAI_SRC_PRE 547 425 #define MCLK_SDPDIF_SRC_PRE 548 426 #define CLK_NR_CLKS (MCLK_SDPDIF_SRC_PRE + 1) 427 428 /* grf-clocks indices */ 429 #define SCLK_SDMMC_DRV 1 430 #define SCLK_SDMMC_SAMPLE 2 431 #define SCLK_SDIO0_DRV 3 432 #define SCLK_SDIO0_SAMPLE 4 433 #define SCLK_SDIO1_DRV 5 434 #define SCLK_SDIO1_SAMPLE 6 435 #define CLK_NR_GRF_CLKS (SCLK_SDIO1_SAMPLE + 1) 436 437 /* scmi-clocks indices */ 438 #define SCMI_PCLK_KEYREADER 0 439 #define SCMI_HCLK_KLAD 1 440 #define SCMI_PCLK_KLAD 2 441 #define SCMI_HCLK_TRNG_S 3 442 #define SCMI_HCLK_CRYPTO_S 4 443 #define SCMI_PCLK_WDT_S 5 444 #define SCMI_TCLK_WDT_S 6 445 #define SCMI_PCLK_STIMER 7 446 #define SCMI_CLK_STIMER0 8 447 #define SCMI_CLK_STIMER1 9 448 #define SCMI_PCLK_OTP_MASK 10 449 #define SCMI_PCLK_OTPC_S 11 450 #define SCMI_CLK_SBPI_OTPC_S 12 451 #define SCMI_CLK_USER_OTPC_S 13 452 #define SCMI_CLK_PMC_OTP 14 453 #define SCMI_CLK_OTPC_ARB 15 454 #define SCMI_CLK_CORE_TSP 16 455 #define SCMI_ACLK_TSP 17 456 #define SCMI_HCLK_TSP 18 457 #define SCMI_PCLK_DCF 19 458 #define SCMI_CLK_DDR 20 459 #define SCMI_CLK_CPU 21 460 #define SCMI_CLK_GPU 22 461 #define SCMI_CORE_CRYPTO 23 462 #define SCMI_ACLK_CRYPTO 24 463 #define SCMI_PKA_CRYPTO 25 464 #define SCMI_HCLK_CRYPTO 26 465 #define SCMI_CORE_CRYPTO_S 27 466 #define SCMI_ACLK_CRYPTO_S 28 467 #define SCMI_PKA_CRYPTO_S 29 468 #define SCMI_CORE_KLAD 30 469 #define SCMI_ACLK_KLAD 31 470 #define SCMI_HCLK_TRNG 32 471 472 // CRU_SOFTRST_CON03(Offset:0xA0C) 473 #define SRST_NCOREPORESET0 0x00000030 474 #define SRST_NCOREPORESET1 0x00000031 475 #define SRST_NCOREPORESET2 0x00000032 476 #define SRST_NCOREPORESET3 0x00000033 477 #define SRST_NCORESET0 0x00000034 478 #define SRST_NCORESET1 0x00000035 479 #define SRST_NCORESET2 0x00000036 480 #define SRST_NCORESET3 0x00000037 481 #define SRST_NL2RESET 0x00000038 482 #define SRST_ARESETN_M_CORE_BIU 0x00000039 483 #define SRST_RESETN_CORE_CRYPTO 0x0000003A 484 485 // CRU_SOFTRST_CON05(Offset:0xA14) 486 #define SRST_PRESETN_DBG 0x0000005D 487 #define SRST_POTRESETN_DBG 0x0000005E 488 #define SRST_NTRESETN_DBG 0x0000005F 489 490 // CRU_SOFTRST_CON06(Offset:0xA18) 491 #define SRST_PRESETN_CORE_GRF 0x00000062 492 #define SRST_PRESETN_DAPLITE_BIU 0x00000063 493 #define SRST_PRESETN_CPU_BIU 0x00000064 494 #define SRST_RESETN_REF_PVTPLL_CORE 0x00000067 495 496 // CRU_SOFTRST_CON08(Offset:0xA20) 497 #define SRST_ARESETN_BUS_VOPGL_BIU 0x00000081 498 #define SRST_ARESETN_BUS_H_BIU 0x00000083 499 #define SRST_ARESETN_SYSMEM_BIU 0x00000088 500 #define SRST_ARESETN_BUS_BIU 0x0000008A 501 #define SRST_HRESETN_BUS_BIU 0x0000008B 502 #define SRST_PRESETN_BUS_BIU 0x0000008C 503 #define SRST_PRESETN_DFT2APB 0x0000008D 504 #define SRST_PRESETN_BUS_GRF 0x0000008F 505 506 // CRU_SOFTRST_CON09(Offset:0xA24) 507 #define SRST_ARESETN_BUS_M_BIU 0x00000090 508 #define SRST_ARESETN_GIC 0x00000091 509 #define SRST_ARESETN_SPINLOCK 0x00000092 510 #define SRST_ARESETN_DMAC 0x00000094 511 #define SRST_PRESETN_TIMER 0x00000095 512 #define SRST_RESETN_TIMER0 0x00000096 513 #define SRST_RESETN_TIMER1 0x00000097 514 #define SRST_RESETN_TIMER2 0x00000098 515 #define SRST_RESETN_TIMER3 0x00000099 516 #define SRST_RESETN_TIMER4 0x0000009A 517 #define SRST_RESETN_TIMER5 0x0000009B 518 #define SRST_PRESETN_JDBCK_DAP 0x0000009C 519 #define SRST_RESETN_JDBCK_DAP 0x0000009D 520 #define SRST_PRESETN_WDT_NS 0x0000009F 521 522 // CRU_SOFTRST_CON10(Offset:0xA28) 523 #define SRST_TRESETN_WDT_NS 0x000000A0 524 #define SRST_HRESETN_TRNG_NS 0x000000A3 525 #define SRST_PRESETN_UART0 0x000000A7 526 #define SRST_SRESETN_UART0 0x000000A8 527 #define SRST_RESETN_PKA_CRYPTO 0x000000AA 528 #define SRST_ARESETN_CRYPTO 0x000000AB 529 #define SRST_HRESETN_CRYPTO 0x000000AC 530 #define SRST_PRESETN_DMA2DDR 0x000000AD 531 #define SRST_ARESETN_DMA2DDR 0x000000AE 532 533 // CRU_SOFTRST_CON11(Offset:0xA2C) 534 #define SRST_PRESETN_PWM0 0x000000B4 535 #define SRST_RESETN_PWM0 0x000000B5 536 #define SRST_PRESETN_PWM1 0x000000B7 537 #define SRST_RESETN_PWM1 0x000000B8 538 #define SRST_PRESETN_SCR 0x000000BA 539 #define SRST_ARESETN_DCF 0x000000BB 540 #define SRST_PRESETN_INTMUX 0x000000BC 541 542 // CRU_SOFTRST_CON25(Offset:0xA64) 543 #define SRST_ARESETN_VPU_BIU 0x00000196 544 #define SRST_HRESETN_VPU_BIU 0x00000197 545 #define SRST_PRESETN_VPU_BIU 0x00000198 546 #define SRST_ARESETN_VPU 0x00000199 547 #define SRST_HRESETN_VPU 0x0000019A 548 #define SRST_PRESETN_CRU_PCIE 0x0000019B 549 #define SRST_PRESETN_VPU_GRF 0x0000019C 550 #define SRST_HRESETN_SFC 0x0000019D 551 #define SRST_SRESETN_SFC 0x0000019E 552 #define SRST_CRESETN_EMMC 0x0000019F 553 554 // CRU_SOFTRST_CON26(Offset:0xA68) 555 #define SRST_HRESETN_EMMC 0x000001A0 556 #define SRST_ARESETN_EMMC 0x000001A1 557 #define SRST_BRESETN_EMMC 0x000001A2 558 #define SRST_TRESETN_EMMC 0x000001A3 559 #define SRST_PRESETN_GPIO1 0x000001A4 560 #define SRST_DBRESETN_GPIO1 0x000001A5 561 #define SRST_ARESETN_VPU_L_BIU 0x000001A6 562 #define SRST_PRESETN_VPU_IOC 0x000001A8 563 #define SRST_HRESETN_SAI_I2S0 0x000001A9 564 #define SRST_MRESETN_SAI_I2S0 0x000001AA 565 #define SRST_HRESETN_SAI_I2S2 0x000001AB 566 #define SRST_MRESETN_SAI_I2S2 0x000001AC 567 #define SRST_PRESETN_ACODEC 0x000001AD 568 569 // CRU_SOFTRST_CON27(Offset:0xA6C) 570 #define SRST_PRESETN_GPIO3 0x000001B0 571 #define SRST_DBRESETN_GPIO3 0x000001B1 572 #define SRST_PRESETN_SPI1 0x000001B4 573 #define SRST_RESETN_SPI1 0x000001B5 574 #define SRST_PRESETN_UART2 0x000001B7 575 #define SRST_SRESETN_UART2 0x000001B8 576 #define SRST_PRESETN_UART5 0x000001B9 577 #define SRST_SRESETN_UART5 0x000001BA 578 #define SRST_PRESETN_UART6 0x000001BB 579 #define SRST_SRESETN_UART6 0x000001BC 580 #define SRST_PRESETN_UART7 0x000001BD 581 #define SRST_SRESETN_UART7 0x000001BE 582 #define SRST_PRESETN_I2C3 0x000001BF 583 584 // CRU_SOFTRST_CON28(Offset:0xA70) 585 #define SRST_RESETN_I2C3 0x000001C0 586 #define SRST_PRESETN_I2C5 0x000001C1 587 #define SRST_RESETN_I2C5 0x000001C2 588 #define SRST_PRESETN_I2C6 0x000001C3 589 #define SRST_RESETN_I2C6 0x000001C4 590 #define SRST_ARESETN_MAC 0x000001C5 591 592 // CRU_SOFTRST_CON30(Offset:0xA78) 593 #define SRST_PRESETN_PCIE 0x000001E1 594 #define SRST_RESETN_PCIE_PIPE_PHY 0x000001E2 595 #define SRST_RESETN_PCIE_POWER_UP 0x000001E3 596 #define SRST_PRESETN_PCIE_PHY 0x000001E6 597 #define SRST_PRESETN_PIPE_GRF 0x000001E7 598 599 // CRU_SOFTRST_CON32(Offset:0xA80) 600 #define SRST_HRESETN_SDIO0 0x00000202 601 #define SRST_HRESETN_SDIO1 0x00000204 602 #define SRST_RESETN_TS_0 0x00000205 603 #define SRST_RESETN_TS_1 0x00000206 604 #define SRST_PRESETN_CAN2 0x00000207 605 #define SRST_RESETN_CAN2 0x00000208 606 #define SRST_PRESETN_CAN3 0x00000209 607 #define SRST_RESETN_CAN3 0x0000020A 608 #define SRST_PRESETN_SARADC 0x0000020B 609 #define SRST_RESETN_SARADC 0x0000020C 610 #define SRST_RESETN_SARADC_PHY 0x0000020D 611 #define SRST_PRESETN_TSADC 0x0000020E 612 #define SRST_RESETN_TSADC 0x0000020F 613 614 // CRU_SOFTRST_CON33(Offset:0xA84) 615 #define SRST_ARESETN_USB3OTG 0x00000211 616 617 // CRU_SOFTRST_CON34(Offset:0xA88) 618 #define SRST_ARESETN_GPU_BIU 0x00000223 619 #define SRST_PRESETN_GPU_BIU 0x00000225 620 #define SRST_ARESETN_GPU 0x00000228 621 #define SRST_RESETN_REF_PVTPLL_GPU 0x00000229 622 623 // CRU_SOFTRST_CON36(Offset:0xA90) 624 #define SRST_HRESETN_RKVENC_BIU 0x00000243 625 #define SRST_ARESETN_RKVENC_BIU 0x00000244 626 #define SRST_PRESETN_RKVENC_BIU 0x00000245 627 #define SRST_HRESETN_RKVENC 0x00000246 628 #define SRST_ARESETN_RKVENC 0x00000247 629 #define SRST_RESETN_CORE_RKVENC 0x00000248 630 #define SRST_HRESETN_SAI_I2S1 0x00000249 631 #define SRST_MRESETN_SAI_I2S1 0x0000024A 632 #define SRST_PRESETN_I2C1 0x0000024B 633 #define SRST_RESETN_I2C1 0x0000024C 634 #define SRST_PRESETN_I2C0 0x0000024D 635 #define SRST_RESETN_I2C0 0x0000024E 636 637 // CRU_SOFTRST_CON37(Offset:0xA94) 638 #define SRST_PRESETN_SPI0 0x00000252 639 #define SRST_RESETN_SPI0 0x00000253 640 #define SRST_PRESETN_GPIO4 0x00000258 641 #define SRST_DBRESETN_GPIO4 0x00000259 642 #define SRST_PRESETN_RKVENC_IOC 0x0000025A 643 #define SRST_HRESETN_SPDIF 0x0000025E 644 #define SRST_MRESETN_SPDIF 0x0000025F 645 646 // CRU_SOFTRST_CON38(Offset:0xA98) 647 #define SRST_HRESETN_PDM 0x00000260 648 #define SRST_MRESETN_PDM 0x00000261 649 #define SRST_PRESETN_UART1 0x00000262 650 #define SRST_SRESETN_UART1 0x00000263 651 #define SRST_PRESETN_UART3 0x00000264 652 #define SRST_SRESETN_UART3 0x00000265 653 #define SRST_PRESETN_RKVENC_GRF 0x00000266 654 #define SRST_PRESETN_CAN0 0x00000267 655 #define SRST_RESETN_CAN0 0x00000268 656 #define SRST_PRESETN_CAN1 0x00000269 657 #define SRST_RESETN_CAN1 0x0000026A 658 659 // CRU_SOFTRST_CON39(Offset:0xA9C) 660 #define SRST_ARESETN_VO_BIU 0x00000273 661 #define SRST_HRESETN_VO_BIU 0x00000274 662 #define SRST_PRESETN_VO_BIU 0x00000275 663 #define SRST_HRESETN_RGA2E 0x00000277 664 #define SRST_ARESETN_RGA2E 0x00000278 665 #define SRST_RESETN_CORE_RGA2E 0x00000279 666 #define SRST_HRESETN_VDPP 0x0000027A 667 #define SRST_ARESETN_VDPP 0x0000027B 668 #define SRST_RESETN_CORE_VDPP 0x0000027C 669 #define SRST_PRESETN_VO_GRF 0x0000027D 670 #define SRST_PRESETN_CRU 0x0000027F 671 672 // CRU_SOFTRST_CON40(Offset:0xAA0) 673 #define SRST_ARESETN_VOP_BIU 0x00000281 674 #define SRST_HRESETN_VOP 0x00000282 675 #define SRST_DRESETN_VOP0 0x00000283 676 #define SRST_DRESETN_VOP1 0x00000284 677 #define SRST_ARESETN_VOP 0x00000285 678 #define SRST_PRESETN_HDMI 0x00000286 679 #define SRST_HDMI_RESETN 0x00000287 680 #define SRST_PRESETN_HDMIPHY 0x0000028E 681 #define SRST_HRESETN_HDCP_KEY 0x0000028F 682 683 // CRU_SOFTRST_CON41(Offset:0xAA4) 684 #define SRST_ARESETN_HDCP 0x00000290 685 #define SRST_HRESETN_HDCP 0x00000291 686 #define SRST_PRESETN_HDCP 0x00000292 687 #define SRST_HRESETN_CVBS 0x00000293 688 #define SRST_DRESETN_CVBS_VOP 0x00000294 689 #define SRST_DRESETN_4X_CVBS_VOP 0x00000295 690 #define SRST_ARESETN_JPEG_DECODER 0x00000296 691 #define SRST_HRESETN_JPEG_DECODER 0x00000297 692 #define SRST_ARESETN_VO_L_BIU 0x00000299 693 #define SRST_ARESETN_MAC_VO 0x0000029A 694 695 // CRU_SOFTRST_CON42(Offset:0xAA8) 696 #define SRST_ARESETN_JPEG_BIU 0x000002A0 697 #define SRST_HRESETN_SAI_I2S3 0x000002A1 698 #define SRST_MRESETN_SAI_I2S3 0x000002A2 699 #define SRST_RESETN_MACPHY 0x000002A3 700 #define SRST_PRESETN_VCDCPHY 0x000002A4 701 #define SRST_PRESETN_GPIO2 0x000002A5 702 #define SRST_DBRESETN_GPIO2 0x000002A6 703 #define SRST_PRESETN_VO_IOC 0x000002A7 704 #define SRST_HRESETN_SDMMC0 0x000002A9 705 #define SRST_PRESETN_OTPC_NS 0x000002AB 706 #define SRST_RESETN_SBPI_OTPC_NS 0x000002AC 707 #define SRST_RESETN_USER_OTPC_NS 0x000002AD 708 709 // CRU_SOFTRST_CON43(Offset:0xAAC) 710 #define SRST_RESETN_HDMIHDP0 0x000002B2 711 #define SRST_HRESETN_USBHOST 0x000002B3 712 #define SRST_HRESETN_USBHOST_ARB 0x000002B4 713 #define SRST_RESETN_HOST_UTMI 0x000002B6 714 #define SRST_PRESETN_UART4 0x000002B7 715 #define SRST_SRESETN_UART4 0x000002B8 716 #define SRST_PRESETN_I2C4 0x000002B9 717 #define SRST_RESETN_I2C4 0x000002BA 718 #define SRST_PRESETN_I2C7 0x000002BB 719 #define SRST_RESETN_I2C7 0x000002BC 720 #define SRST_PRESETN_USBPHY 0x000002BD 721 #define SRST_RESETN_USBPHY_POR 0x000002BE 722 #define SRST_RESETN_USBPHY_OTG 0x000002BF 723 724 // CRU_SOFTRST_CON44(Offset:0xAB0) 725 #define SRST_RESETN_USBPHY_HOST 0x000002C0 726 #define SRST_PRESETN_DDRPHY_CRU 0x000002C4 727 #define SRST_HRESETN_RKVDEC_BIU 0x000002C6 728 #define SRST_ARESETN_RKVDEC_BIU 0x000002C7 729 #define SRST_ARESETN_RKVDEC 0x000002C8 730 #define SRST_HRESETN_RKVDEC 0x000002C9 731 #define SRST_RESETN_HEVC_CA_RKVDEC 0x000002CB 732 #define SRST_RESETN_REF_PVTPLL_RKVDEC 0x000002CC 733 734 // CRU_SOFTRST_CON45(Offset:0xAB4) 735 #define SRST_PRESETN_DDR_BIU 0x000002D1 736 #define SRST_PRESETN_DDRC 0x000002D2 737 #define SRST_PRESETN_DDRMON 0x000002D3 738 #define SRST_RESETN_TIMER_DDRMON 0x000002D4 739 #define SRST_PRESETN_MSCH_BIU 0x000002D5 740 #define SRST_PRESETN_DDR_GRF 0x000002D6 741 #define SRST_PRESETN_DDR_HWLP 0x000002D8 742 #define SRST_PRESETN_DDRPHY 0x000002D9 743 #define SRST_RESETN_MSCH_BIU 0x000002DA 744 #define SRST_ARESETN_DDR_UPCTL 0x000002DB 745 #define SRST_RESETN_DDR_UPCTL 0x000002DC 746 #define SRST_RESETN_DDRMON 0x000002DD 747 #define SRST_ARESETN_DDR_SCRAMBLE 0x000002DE 748 #define SRST_ARESETN_SPLIT 0x000002DF 749 750 // CRU_SOFTRST_CON46(Offset:0xAB8) 751 #define SRST_RESETN_DDR_PHY 0x000002E0 752 753 #endif 754 755