1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H 8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H 9 10 /* core clocks */ 11 #define PLL_APLL 1 12 #define PLL_DPLL 2 13 #define PLL_CPLL 3 14 #define PLL_GPLL 4 15 #define ARMCLK 5 16 #define PLL_GPLL_DIV2 6 17 #define PLL_GPLL_DIV3 7 18 19 /* sclk gates (special clocks) */ 20 #define SCLK_SPI0 65 21 #define SCLK_NANDC 67 22 #define SCLK_SDMMC 68 23 #define SCLK_SDIO 69 24 #define SCLK_EMMC 71 25 #define SCLK_UART0 77 26 #define SCLK_UART1 78 27 #define SCLK_UART2 79 28 #define SCLK_I2S0 80 29 #define SCLK_I2S1 81 30 #define SCLK_SPDIF 83 31 #define SCLK_TIMER0 85 32 #define SCLK_TIMER1 86 33 #define SCLK_TIMER2 87 34 #define SCLK_TIMER3 88 35 #define SCLK_TIMER4 89 36 #define SCLK_TIMER5 90 37 #define SCLK_SARADC 91 38 #define SCLK_I2S_OUT 113 39 #define SCLK_SDMMC_DRV 114 40 #define SCLK_SDIO_DRV 115 41 #define SCLK_EMMC_DRV 117 42 #define SCLK_SDMMC_SAMPLE 118 43 #define SCLK_SDIO_SAMPLE 119 44 #define SCLK_EMMC_SAMPLE 121 45 #define SCLK_VOP 122 46 #define SCLK_MAC_SRC 124 47 #define SCLK_MAC 126 48 #define SCLK_MAC_REFOUT 127 49 #define SCLK_MAC_REF 128 50 #define SCLK_MAC_RX 129 51 #define SCLK_MAC_TX 130 52 #define SCLK_HEVC_CORE 134 53 #define SCLK_RGA 135 54 #define SCLK_CRYPTO 138 55 #define SCLK_TSP 139 56 #define SCLK_OTGPHY0 142 57 #define SCLK_OTGPHY1 143 58 #define SCLK_DDRC 144 59 #define SCLK_PVTM_FUNC 145 60 #define SCLK_PVTM_CORE 146 61 #define SCLK_PVTM_GPU 147 62 #define SCLK_MIPI_24M 148 63 #define SCLK_PVTM 149 64 #define SCLK_CIF_SRC 150 65 #define SCLK_CIF_OUT_SRC 151 66 #define SCLK_CIF_OUT 152 67 #define SCLK_SFC 153 68 #define SCLK_USB480M 154 69 #define SCLK_HSADC_TSP 155 70 71 /* dclk gates */ 72 #define DCLK_VOP 190 73 #define DCLK_EBC 191 74 75 /* aclk gates */ 76 #define ACLK_VIO0 192 77 #define ACLK_VIO1 193 78 #define ACLK_DMAC 194 79 #define ACLK_CPU 195 80 #define ACLK_VEPU 196 81 #define ACLK_VDPU 197 82 #define ACLK_CIF 198 83 #define ACLK_IEP 199 84 #define ACLK_LCDC0 204 85 #define ACLK_RGA 205 86 #define ACLK_PERI 210 87 #define ACLK_VOP 211 88 #define ACLK_GMAC 212 89 #define ACLK_GPU 213 90 91 /* pclk gates */ 92 #define PCLK_SARADC 318 93 #define PCLK_WDT 319 94 #define PCLK_GPIO0 320 95 #define PCLK_GPIO1 321 96 #define PCLK_GPIO2 322 97 #define PCLK_GPIO3 323 98 #define PCLK_VIO_H2P 324 99 #define PCLK_MIPI 325 100 #define PCLK_EFUSE 326 101 #define PCLK_HDMI 327 102 #define PCLK_ACODEC 328 103 #define PCLK_GRF 329 104 #define PCLK_I2C0 332 105 #define PCLK_I2C1 333 106 #define PCLK_I2C2 334 107 #define PCLK_I2C3 335 108 #define PCLK_SPI0 338 109 #define PCLK_UART0 341 110 #define PCLK_UART1 342 111 #define PCLK_UART2 343 112 #define PCLK_TSADC 344 113 #define PCLK_PWM 350 114 #define PCLK_TIMER 353 115 #define PCLK_CPU 354 116 #define PCLK_PERI 363 117 #define PCLK_GMAC 367 118 #define PCLK_PMU_PRE 368 119 #define PCLK_SIM_CARD 369 120 #define PCLK_MIPIPHY 370 121 122 /* hclk gates */ 123 #define HCLK_SFC 439 124 #define HCLK_SPDIF 440 125 #define HCLK_GPS 441 126 #define HCLK_USBHOST 442 127 #define HCLK_I2S_8CH 443 128 #define HCLK_I2S_2CH 444 129 #define HCLK_VOP 452 130 #define HCLK_NANDC 453 131 #define HCLK_SDMMC 456 132 #define HCLK_SDIO 457 133 #define HCLK_EMMC 459 134 #define HCLK_CPU 460 135 #define HCLK_VEPU 461 136 #define HCLK_VDPU 462 137 #define HCLK_LCDC0 463 138 #define HCLK_EBC 465 139 #define HCLK_VIO 466 140 #define HCLK_RGA 467 141 #define HCLK_IEP 468 142 #define HCLK_VIO_H2P 469 143 #define HCLK_CIF 470 144 #define HCLK_HOST2 473 145 #define HCLK_OTG 474 146 #define HCLK_TSP 475 147 #define HCLK_CRYPTO 476 148 #define HCLK_PERI 478 149 150 #define CLK_NR_CLKS (HCLK_PERI + 1) 151 152 /* soft-reset indices */ 153 #define SRST_CORE0_PO 0 154 #define SRST_CORE1_PO 1 155 #define SRST_CORE2_PO 2 156 #define SRST_CORE3_PO 3 157 #define SRST_CORE0 4 158 #define SRST_CORE1 5 159 #define SRST_CORE2 6 160 #define SRST_CORE3 7 161 #define SRST_CORE0_DBG 8 162 #define SRST_CORE1_DBG 9 163 #define SRST_CORE2_DBG 10 164 #define SRST_CORE3_DBG 11 165 #define SRST_TOPDBG 12 166 #define SRST_ACLK_CORE 13 167 #define SRST_STRC_SYS_A 14 168 #define SRST_L2C 15 169 170 #define SRST_CPUSYS_H 18 171 #define SRST_AHB2APBSYS_H 19 172 #define SRST_SPDIF 20 173 #define SRST_INTMEM 21 174 #define SRST_ROM 22 175 #define SRST_PERI_NIU 23 176 #define SRST_I2S_2CH 24 177 #define SRST_I2S_8CH 25 178 #define SRST_GPU_PVTM 26 179 #define SRST_FUNC_PVTM 27 180 #define SRST_CORE_PVTM 29 181 #define SRST_EFUSE_P 30 182 #define SRST_ACODEC_P 31 183 184 #define SRST_GPIO0 32 185 #define SRST_GPIO1 33 186 #define SRST_GPIO2 34 187 #define SRST_GPIO3 35 188 #define SRST_MIPIPHY_P 36 189 #define SRST_UART0 39 190 #define SRST_UART1 40 191 #define SRST_UART2 41 192 #define SRST_I2C0 43 193 #define SRST_I2C1 44 194 #define SRST_I2C2 45 195 #define SRST_I2C3 46 196 #define SRST_SFC 47 197 198 #define SRST_PWM 48 199 #define SRST_DAP_PO 50 200 #define SRST_DAP 51 201 #define SRST_DAP_SYS 52 202 #define SRST_CRYPTO 53 203 #define SRST_GRF 55 204 #define SRST_GMAC 56 205 #define SRST_PERIPH_SYS_A 57 206 #define SRST_PERIPH_SYS_H 58 207 #define SRST_PERIPH_SYS_P 59 208 #define SRST_SMART_CARD 60 209 #define SRST_CPU_PERI 61 210 #define SRST_EMEM_PERI 62 211 #define SRST_USB_PERI 63 212 213 #define SRST_DMA 64 214 #define SRST_GPS 67 215 #define SRST_NANDC 68 216 #define SRST_USBOTG0 69 217 #define SRST_OTGC0 71 218 #define SRST_USBOTG1 72 219 #define SRST_OTGC1 74 220 #define SRST_DDRMSCH 79 221 222 #define SRST_SDMMC 81 223 #define SRST_SDIO 82 224 #define SRST_EMMC 83 225 #define SRST_SPI 84 226 #define SRST_WDT 86 227 #define SRST_SARADC 87 228 #define SRST_DDRPHY 88 229 #define SRST_DDRPHY_P 89 230 #define SRST_DDRCTRL 90 231 #define SRST_DDRCTRL_P 91 232 #define SRST_TSP 92 233 #define SRST_TSP_CLKIN 93 234 #define SRST_HOST0_ECHI 94 235 236 #define SRST_HDMI_P 96 237 #define SRST_VIO_ARBI_H 97 238 #define SRST_VIO0_A 98 239 #define SRST_VIO_BUS_H 99 240 #define SRST_VOP_A 100 241 #define SRST_VOP_H 101 242 #define SRST_VOP_D 102 243 #define SRST_UTMI0 103 244 #define SRST_UTMI1 104 245 #define SRST_USBPOR 105 246 #define SRST_IEP_A 106 247 #define SRST_IEP_H 107 248 #define SRST_RGA_A 108 249 #define SRST_RGA_H 109 250 #define SRST_CIF0 110 251 #define SRST_PMU 111 252 253 #define SRST_VCODEC_A 112 254 #define SRST_VCODEC_H 113 255 #define SRST_VIO1_A 114 256 #define SRST_HEVC_CORE 115 257 #define SRST_VCODEC_NIU_A 116 258 #define SRST_PMU_NIU_P 117 259 #define SRST_LCDC0_S 119 260 #define SRST_GPU 120 261 #define SRST_GPU_NIU_A 122 262 #define SRST_EBC_A 123 263 #define SRST_EBC_H 124 264 265 #define SRST_CORE_DBG 128 266 #define SRST_DBG_P 129 267 #define SRST_TIMER0 130 268 #define SRST_TIMER1 131 269 #define SRST_TIMER2 132 270 #define SRST_TIMER3 133 271 #define SRST_TIMER4 134 272 #define SRST_TIMER5 135 273 #define SRST_VIO_H2P 136 274 #define SRST_VIO_MIPI_DSI 137 275 276 #endif 277