1 /* 2 * Copyright (c) 2017 Rockchip Electronics Co. Ltd. 3 * Author: Elaine <zhangqing@rock-chips.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_PX30_H 17 #define _DT_BINDINGS_CLK_ROCKCHIP_PX30_H 18 19 /* core clocks */ 20 #define PLL_APLL 1 21 #define PLL_DPLL 2 22 #define PLL_CPLL 3 23 #define PLL_NPLL 4 24 #define APLL_BOOST_H 5 25 #define APLL_BOOST_L 6 26 #define ARMCLK 7 27 28 /* sclk gates (special clocks) */ 29 #define USB480M 14 30 #define SCLK_PDM 15 31 #define SCLK_I2S0_TX 16 32 #define SCLK_I2S0_TX_OUT 17 33 #define SCLK_I2S0_RX 18 34 #define SCLK_I2S0_RX_OUT 19 35 #define SCLK_I2S1 20 36 #define SCLK_I2S1_OUT 21 37 #define SCLK_I2S2 22 38 #define SCLK_I2S2_OUT 23 39 #define SCLK_UART1 24 40 #define SCLK_UART2 25 41 #define SCLK_UART3 26 42 #define SCLK_UART4 27 43 #define SCLK_UART5 28 44 #define SCLK_I2C0 29 45 #define SCLK_I2C1 30 46 #define SCLK_I2C2 31 47 #define SCLK_I2C3 32 48 #define SCLK_I2C4 33 49 #define SCLK_PWM0 34 50 #define SCLK_PWM1 35 51 #define SCLK_SPI0 36 52 #define SCLK_SPI1 37 53 #define SCLK_TIMER0 38 54 #define SCLK_TIMER1 39 55 #define SCLK_TIMER2 40 56 #define SCLK_TIMER3 41 57 #define SCLK_TIMER4 42 58 #define SCLK_TIMER5 43 59 #define SCLK_TSADC 44 60 #define SCLK_SARADC 45 61 #define SCLK_OTP 46 62 #define SCLK_OTP_USR 47 63 #define SCLK_CRYPTO 48 64 #define SCLK_CRYPTO_APK 49 65 #define SCLK_DDRC 50 66 #define SCLK_ISP 51 67 #define SCLK_CIF_OUT 52 68 #define SCLK_RGA_CORE 53 69 #define SCLK_VOPB_PWM 54 70 #define SCLK_NANDC 55 71 #define SCLK_SDIO 56 72 #define SCLK_EMMC 57 73 #define SCLK_SFC 58 74 #define SCLK_SDMMC 59 75 #define SCLK_OTG_ADP 60 76 #define SCLK_GMAC_SRC 61 77 #define SCLK_GMAC 62 78 #define SCLK_GMAC_RX_TX 63 79 #define SCLK_MAC_REF 64 80 #define SCLK_MAC_REFOUT 65 81 #define SCLK_MAC_OUT 66 82 #define SCLK_SDMMC_DRV 67 83 #define SCLK_SDMMC_SAMPLE 68 84 #define SCLK_SDIO_DRV 69 85 #define SCLK_SDIO_SAMPLE 70 86 #define SCLK_EMMC_DRV 71 87 #define SCLK_EMMC_SAMPLE 72 88 #define SCLK_GPU 73 89 #define SCLK_PVTM 74 90 #define SCLK_CORE_VPU 75 91 #define SCLK_GMAC_RMII 76 92 #define SCLK_UART2_SRC 77 93 #define SCLK_NANDC_DIV 78 94 #define SCLK_NANDC_DIV50 79 95 #define SCLK_SDIO_DIV 80 96 #define SCLK_SDIO_DIV50 81 97 #define SCLK_EMMC_DIV 82 98 #define SCLK_EMMC_DIV50 83 99 100 /* dclk gates */ 101 #define DCLK_VOPB 150 102 #define DCLK_VOPL 151 103 104 /* aclk gates */ 105 #define ACLK_GPU 170 106 #define ACLK_BUS_PRE 171 107 #define ACLK_CRYPTO 172 108 #define ACLK_VI_PRE 173 109 #define ACLK_VO_PRE 174 110 #define ACLK_VPU 175 111 #define ACLK_PERI_PRE 176 112 #define ACLK_GMAC 178 113 #define ACLK_CIF 179 114 #define ACLK_ISP 180 115 #define ACLK_VOPB 181 116 #define ACLK_VOPL 182 117 #define ACLK_RGA 183 118 #define ACLK_GIC 184 119 #define ACLK_DCF 186 120 #define ACLK_DMAC 187 121 122 /* hclk gates */ 123 #define HCLK_BUS_PRE 240 124 #define HCLK_CRYPTO 241 125 #define HCLK_VI_PRE 242 126 #define HCLK_VO_PRE 243 127 #define HCLK_VPU 244 128 #define HCLK_PERI_PRE 245 129 #define HCLK_MMC_NAND 246 130 #define HCLK_SDMMC 247 131 #define HCLK_USB 248 132 #define HCLK_CIF 249 133 #define HCLK_ISP 250 134 #define HCLK_VOPB 251 135 #define HCLK_VOPL 252 136 #define HCLK_RGA 253 137 #define HCLK_NANDC 254 138 #define HCLK_SDIO 255 139 #define HCLK_EMMC 256 140 #define HCLK_SFC 257 141 #define HCLK_OTG 258 142 #define HCLK_HOST 259 143 #define HCLK_HOST_ARB 260 144 #define HCLK_PDM 261 145 #define HCLK_I2S0 262 146 #define HCLK_I2S1 263 147 #define HCLK_I2S2 264 148 149 /* pclk gates */ 150 #define PCLK_BUS_PRE 320 151 #define PCLK_DDR 321 152 #define PCLK_VO_PRE 322 153 #define PCLK_GMAC 323 154 #define PCLK_MIPI_DSI 324 155 #define PCLK_MIPIDSIPHY 325 156 #define PCLK_MIPICSIPHY 326 157 #define PCLK_USB_GRF 327 158 #define PCLK_DCF 328 159 #define PCLK_UART1 329 160 #define PCLK_UART2 330 161 #define PCLK_UART3 331 162 #define PCLK_UART4 332 163 #define PCLK_UART5 333 164 #define PCLK_I2C0 334 165 #define PCLK_I2C1 335 166 #define PCLK_I2C2 336 167 #define PCLK_I2C3 337 168 #define PCLK_I2C4 338 169 #define PCLK_PWM0 339 170 #define PCLK_PWM1 340 171 #define PCLK_SPI0 341 172 #define PCLK_SPI1 342 173 #define PCLK_SARADC 343 174 #define PCLK_TSADC 344 175 #define PCLK_TIMER 345 176 #define PCLK_OTP_NS 346 177 #define PCLK_WDT_NS 347 178 #define PCLK_GPIO1 348 179 #define PCLK_GPIO2 349 180 #define PCLK_GPIO3 350 181 #define PCLK_ISP 351 182 #define PCLK_CIF 352 183 #define PCLK_OTP_PHY 353 184 185 #define CLK_NR_CLKS (PCLK_OTP_PHY + 1) 186 187 /* pmu-clocks indices */ 188 189 #define PLL_GPLL 1 190 191 #define SCLK_RTC32K_PMU 4 192 #define SCLK_WIFI_PMU 5 193 #define SCLK_UART0_PMU 6 194 #define SCLK_PVTM_PMU 7 195 #define PCLK_PMU_PRE 8 196 #define SCLK_REF24M_PMU 9 197 #define SCLK_USBPHY_REF 10 198 #define SCLK_MIPIDSIPHY_REF 11 199 200 #define XIN24M_DIV 12 201 202 #define PCLK_GPIO0_PMU 20 203 #define PCLK_UART0_PMU 21 204 205 #define CLKPMU_NR_CLKS (PCLK_UART0_PMU + 1) 206 207 /* soft-reset indices */ 208 #define SRST_CORE0_PO 0 209 #define SRST_CORE1_PO 1 210 #define SRST_CORE2_PO 2 211 #define SRST_CORE3_PO 3 212 #define SRST_CORE0 4 213 #define SRST_CORE1 5 214 #define SRST_CORE2 6 215 #define SRST_CORE3 7 216 #define SRST_CORE0_DBG 8 217 #define SRST_CORE1_DBG 9 218 #define SRST_CORE2_DBG 10 219 #define SRST_CORE3_DBG 11 220 #define SRST_TOPDBG 12 221 #define SRST_CORE_NOC 13 222 #define SRST_STRC_A 14 223 #define SRST_L2C 15 224 225 #define SRST_DAP 16 226 #define SRST_CORE_PVTM 17 227 #define SRST_GPU 18 228 #define SRST_GPU_NIU 19 229 #define SRST_UPCTL2 20 230 #define SRST_UPCTL2_A 21 231 #define SRST_UPCTL2_P 22 232 #define SRST_MSCH 23 233 #define SRST_MSCH_P 24 234 #define SRST_DDRMON_P 25 235 #define SRST_DDRSTDBY_P 26 236 #define SRST_DDRSTDBY 27 237 #define SRST_DDRGRF_p 28 238 #define SRST_AXI_SPLIT_A 29 239 #define SRST_AXI_CMD_A 30 240 #define SRST_AXI_CMD_P 31 241 242 #define SRST_DDRPHY 32 243 #define SRST_DDRPHYDIV 33 244 #define SRST_DDRPHY_P 34 245 #define SRST_VPU_A 36 246 #define SRST_VPU_NIU_A 37 247 #define SRST_VPU_H 38 248 #define SRST_VPU_NIU_H 39 249 #define SRST_VI_NIU_A 40 250 #define SRST_VI_NIU_H 41 251 #define SRST_ISP_H 42 252 #define SRST_ISP 43 253 #define SRST_CIF_A 44 254 #define SRST_CIF_H 45 255 #define SRST_CIF_PCLKIN 46 256 #define SRST_MIPICSIPHY_P 47 257 258 #define SRST_VO_NIU_A 48 259 #define SRST_VO_NIU_H 49 260 #define SRST_VO_NIU_P 50 261 #define SRST_VOPB_A 51 262 #define SRST_VOPB_H 52 263 #define SRST_VOPB 53 264 #define SRST_PWM_VOPB 54 265 #define SRST_VOPL_A 55 266 #define SRST_VOPL_H 56 267 #define SRST_VOPL 57 268 #define SRST_RGA_A 58 269 #define SRST_RGA_H 59 270 #define SRST_RGA 60 271 #define SRST_MIPIDSI_HOST_P 61 272 #define SRST_MIPIDSIPHY_P 62 273 #define SRST_VPU_CORE 63 274 275 #define SRST_PERI_NIU_A 64 276 #define SRST_USB_NIU_H 65 277 #define SRST_USB2OTG_H 66 278 #define SRST_USB2OTG 67 279 #define SRST_USB2OTG_ADP 68 280 #define SRST_USB2HOST_H 69 281 #define SRST_USB2HOST_ARB_H 70 282 #define SRST_USB2HOST_AUX_H 71 283 #define SRST_USB2HOST_EHCI 72 284 #define SRST_USB2HOST 73 285 #define SRST_USBPHYPOR 74 286 #define SRST_USBPHY_OTG_PORT 75 287 #define SRST_USBPHY_HOST_PORT 76 288 #define SRST_USBPHY_GRF 77 289 #define SRST_CPU_BOOST_P 78 290 #define SRST_CPU_BOOST 79 291 292 #define SRST_MMC_NAND_NIU_H 80 293 #define SRST_SDIO_H 81 294 #define SRST_EMMC_H 82 295 #define SRST_SFC_H 83 296 #define SRST_SFC 84 297 #define SRST_SDCARD_NIU_H 85 298 #define SRST_SDMMC_H 86 299 #define SRST_NANDC_H 89 300 #define SRST_NANDC 90 301 #define SRST_GMAC_NIU_A 92 302 #define SRST_GMAC_NIU_P 93 303 #define SRST_GMAC_A 94 304 305 #define SRST_PMU_NIU_P 96 306 #define SRST_PMU_SGRF_P 97 307 #define SRST_PMU_GRF_P 98 308 #define SRST_PMU 99 309 #define SRST_PMU_MEM_P 100 310 #define SRST_PMU_GPIO0_P 101 311 #define SRST_PMU_UART0_P 102 312 #define SRST_PMU_CRU_P 103 313 #define SRST_PMU_PVTM 104 314 #define SRST_PMU_UART 105 315 #define SRST_PMU_NIU_H 106 316 #define SRST_PMU_DDR_FAIL_SAVE 107 317 #define SRST_PMU_CORE_PERF_A 108 318 #define SRST_PMU_CORE_GRF_P 109 319 #define SRST_PMU_GPU_PERF_A 110 320 #define SRST_PMU_GPU_GRF_P 111 321 322 #define SRST_CRYPTO_NIU_A 112 323 #define SRST_CRYPTO_NIU_H 113 324 #define SRST_CRYPTO_A 114 325 #define SRST_CRYPTO_H 115 326 #define SRST_CRYPTO 116 327 #define SRST_CRYPTO_APK 117 328 #define SRST_BUS_NIU_H 120 329 #define SRST_USB_NIU_P 121 330 #define SRST_BUS_TOP_NIU_P 122 331 #define SRST_INTMEM_A 123 332 #define SRST_GIC_A 124 333 #define SRST_ROM_H 126 334 #define SRST_DCF_A 127 335 336 #define SRST_DCF_P 128 337 #define SRST_PDM_H 129 338 #define SRST_PDM 130 339 #define SRST_I2S0_H 131 340 #define SRST_I2S0_TX 132 341 #define SRST_I2S1_H 133 342 #define SRST_I2S1 134 343 #define SRST_I2S2_H 135 344 #define SRST_I2S2 136 345 #define SRST_UART1_P 137 346 #define SRST_UART1 138 347 #define SRST_UART2_P 139 348 #define SRST_UART2 140 349 #define SRST_UART3_P 141 350 #define SRST_UART3 142 351 #define SRST_UART4_P 143 352 353 #define SRST_UART4 144 354 #define SRST_UART5_P 145 355 #define SRST_UART5 146 356 #define SRST_I2C0_P 147 357 #define SRST_I2C0 148 358 #define SRST_I2C1_P 149 359 #define SRST_I2C1 150 360 #define SRST_I2C2_P 151 361 #define SRST_I2C2 152 362 #define SRST_I2C3_P 153 363 #define SRST_I2C3 154 364 #define SRST_PWM0_P 157 365 #define SRST_PWM0 158 366 #define SRST_PWM1_P 159 367 368 #define SRST_PWM1 160 369 #define SRST_SPI0_P 161 370 #define SRST_SPI0 162 371 #define SRST_SPI1_P 163 372 #define SRST_SPI1 164 373 #define SRST_SARADC_P 165 374 #define SRST_SARADC 166 375 #define SRST_TSADC_P 167 376 #define SRST_TSADC 168 377 #define SRST_TIMER_P 169 378 #define SRST_TIMER0 170 379 #define SRST_TIMER1 171 380 #define SRST_TIMER2 172 381 #define SRST_TIMER3 173 382 #define SRST_TIMER4 174 383 #define SRST_TIMER5 175 384 385 #define SRST_OTP_NS_P 176 386 #define SRST_OTP_NS_SBPI 177 387 #define SRST_OTP_NS_USR 178 388 #define SRST_OTP_PHY_P 179 389 #define SRST_OTP_PHY 180 390 #define SRST_WDT_NS_P 181 391 #define SRST_GPIO1_P 182 392 #define SRST_GPIO2_P 183 393 #define SRST_GPIO3_P 184 394 #define SRST_SGRF_P 185 395 #define SRST_GRF_P 186 396 #define SRST_I2S0_RX 191 397 398 #endif 399