1 /* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <asm/io.h> 8 #include <asm/arch/immap_ls102xa.h> 9 #include <ahci.h> 10 #include <scsi.h> 11 12 /* port register default value */ 13 #define AHCI_PORT_PHY_1_CFG 0xa003fffe 14 #define AHCI_PORT_PHY_2_CFG 0x28183414 15 #define AHCI_PORT_PHY_3_CFG 0x0e080e06 16 #define AHCI_PORT_PHY_4_CFG 0x064a080b 17 #define AHCI_PORT_PHY_5_CFG 0x2aa86470 18 #define AHCI_PORT_TRANS_CFG 0x08000029 19 20 #define SATA_ECC_REG_ADDR 0x20220520 21 #define SATA_ECC_DISABLE 0x00020000 22 ls1021a_sata_init(void)23int ls1021a_sata_init(void) 24 { 25 struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR; 26 27 #ifdef CONFIG_SYS_FSL_ERRATUM_A008407 28 out_le32((void *)SATA_ECC_REG_ADDR, SATA_ECC_DISABLE); 29 #endif 30 31 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); 32 out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG); 33 out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG); 34 out_le32(&ccsr_ahci->pp4c, AHCI_PORT_PHY_4_CFG); 35 out_le32(&ccsr_ahci->pp5c, AHCI_PORT_PHY_5_CFG); 36 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); 37 38 ahci_init((void __iomem *)AHCI_BASE_ADDR); 39 scsi_scan(false); 40 41 return 0; 42 } 43