1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2011
3*4882a593Smuzhiyun * Ilya Yanok, EmCraft Systems
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #include <linux/types.h>
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #ifndef CONFIG_SYS_DCACHE_OFF
invalidate_dcache_all(void)11*4882a593Smuzhiyun void invalidate_dcache_all(void)
12*4882a593Smuzhiyun {
13*4882a593Smuzhiyun asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
14*4882a593Smuzhiyun }
15*4882a593Smuzhiyun
flush_dcache_all(void)16*4882a593Smuzhiyun void flush_dcache_all(void)
17*4882a593Smuzhiyun {
18*4882a593Smuzhiyun asm volatile(
19*4882a593Smuzhiyun "0:"
20*4882a593Smuzhiyun "mrc p15, 0, r15, c7, c14, 3\n"
21*4882a593Smuzhiyun "bne 0b\n"
22*4882a593Smuzhiyun "mcr p15, 0, %0, c7, c10, 4\n"
23*4882a593Smuzhiyun : : "r"(0) : "memory"
24*4882a593Smuzhiyun );
25*4882a593Smuzhiyun }
26*4882a593Smuzhiyun
invalidate_dcache_range(unsigned long start,unsigned long stop)27*4882a593Smuzhiyun void invalidate_dcache_range(unsigned long start, unsigned long stop)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun if (!check_cache_range(start, stop))
30*4882a593Smuzhiyun return;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun while (start < stop) {
33*4882a593Smuzhiyun asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start));
34*4882a593Smuzhiyun start += CONFIG_SYS_CACHELINE_SIZE;
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun
flush_dcache_range(unsigned long start,unsigned long stop)38*4882a593Smuzhiyun void flush_dcache_range(unsigned long start, unsigned long stop)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun if (!check_cache_range(start, stop))
41*4882a593Smuzhiyun return;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun while (start < stop) {
44*4882a593Smuzhiyun asm volatile("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(start));
45*4882a593Smuzhiyun start += CONFIG_SYS_CACHELINE_SIZE;
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun #else /* #ifndef CONFIG_SYS_DCACHE_OFF */
invalidate_dcache_all(void)51*4882a593Smuzhiyun void invalidate_dcache_all(void)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
flush_dcache_all(void)55*4882a593Smuzhiyun void flush_dcache_all(void)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /*
61*4882a593Smuzhiyun * Stub implementations for l2 cache operations
62*4882a593Smuzhiyun */
63*4882a593Smuzhiyun
l2_cache_disable(void)64*4882a593Smuzhiyun __weak void l2_cache_disable(void) {}
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun #if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
invalidate_l2_cache(void)67*4882a593Smuzhiyun __weak void invalidate_l2_cache(void) {}
68*4882a593Smuzhiyun #endif
69