1<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd"> 2<html> 3<!-- This file documents the GNU linker LD 4(GNU Toolchain for the A-profile Architecture 10.3-2021.07 (arm-10.29)) 5version 2.36.1. 6 7Copyright (C) 1991-2021 Free Software Foundation, Inc. 8 9Permission is granted to copy, distribute and/or modify this document 10under the terms of the GNU Free Documentation License, Version 1.3 11or any later version published by the Free Software Foundation; 12with no Invariant Sections, with no Front-Cover Texts, and with no 13Back-Cover Texts. A copy of the license is included in the 14section entitled "GNU Free Documentation License". --> 15<!-- Created by GNU Texinfo 5.1, http://www.gnu.org/software/texinfo/ --> 16<head> 17<title>LD: ARM</title> 18 19<meta name="description" content="LD: ARM"> 20<meta name="keywords" content="LD: ARM"> 21<meta name="resource-type" content="document"> 22<meta name="distribution" content="global"> 23<meta name="Generator" content="makeinfo"> 24<meta http-equiv="Content-Type" content="text/html; charset=utf-8"> 25<link href="index.html#Top" rel="start" title="Top"> 26<link href="LD-Index.html#LD-Index" rel="index" title="LD Index"> 27<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents"> 28<link href="Machine-Dependent.html#Machine-Dependent" rel="up" title="Machine Dependent"> 29<link href="HPPA-ELF32.html#HPPA-ELF32" rel="next" title="HPPA ELF32"> 30<link href="M68HC11_002f68HC12.html#M68HC11_002f68HC12" rel="previous" title="M68HC11/68HC12"> 31<style type="text/css"> 32<!-- 33a.summary-letter {text-decoration: none} 34blockquote.smallquotation {font-size: smaller} 35div.display {margin-left: 3.2em} 36div.example {margin-left: 3.2em} 37div.indentedblock {margin-left: 3.2em} 38div.lisp {margin-left: 3.2em} 39div.smalldisplay {margin-left: 3.2em} 40div.smallexample {margin-left: 3.2em} 41div.smallindentedblock {margin-left: 3.2em; font-size: smaller} 42div.smalllisp {margin-left: 3.2em} 43kbd {font-style:oblique} 44pre.display {font-family: inherit} 45pre.format {font-family: inherit} 46pre.menu-comment {font-family: serif} 47pre.menu-preformatted {font-family: serif} 48pre.smalldisplay {font-family: inherit; font-size: smaller} 49pre.smallexample {font-size: smaller} 50pre.smallformat {font-family: inherit; font-size: smaller} 51pre.smalllisp {font-size: smaller} 52span.nocodebreak {white-space:nowrap} 53span.nolinebreak {white-space:nowrap} 54span.roman {font-family:serif; font-weight:normal} 55span.sansserif {font-family:sans-serif; font-weight:normal} 56ul.no-bullet {list-style: none} 57--> 58</style> 59 60 61</head> 62 63<body lang="en" bgcolor="#FFFFFF" text="#000000" link="#0000FF" vlink="#800080" alink="#FF0000"> 64<a name="ARM"></a> 65<div class="header"> 66<p> 67Next: <a href="HPPA-ELF32.html#HPPA-ELF32" accesskey="n" rel="next">HPPA ELF32</a>, Previous: <a href="M68HC11_002f68HC12.html#M68HC11_002f68HC12" accesskey="p" rel="previous">M68HC11/68HC12</a>, Up: <a href="Machine-Dependent.html#Machine-Dependent" accesskey="u" rel="up">Machine Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="LD-Index.html#LD-Index" title="Index" rel="index">Index</a>]</p> 68</div> 69<hr> 70<a name="ld-and-the-ARM-family"></a> 71<h3 class="section">5.3 <code>ld</code> and the ARM family</h3> 72 73<a name="index-ARM-interworking-support"></a> 74<a name="index-_002d_002dsupport_002dold_002dcode"></a> 75<p>For the ARM, <code>ld</code> will generate code stubs to allow functions calls 76between ARM and Thumb code. These stubs only work with code that has 77been compiled and assembled with the ‘<samp>-mthumb-interwork</samp>’ command 78line option. If it is necessary to link with old ARM object files or 79libraries, which have not been compiled with the -mthumb-interwork 80option then the ‘<samp>--support-old-code</samp>’ command-line switch should be 81given to the linker. This will make it generate larger stub functions 82which will work with non-interworking aware ARM code. Note, however, 83the linker does not support generating stubs for function calls to 84non-interworking aware Thumb code. 85</p> 86<a name="index-thumb-entry-point"></a> 87<a name="index-entry-point_002c-thumb"></a> 88<a name="index-_002d_002dthumb_002dentry_003dentry"></a> 89<p>The ‘<samp>--thumb-entry</samp>’ switch is a duplicate of the generic 90‘<samp>--entry</samp>’ switch, in that it sets the program’s starting address. 91But it also sets the bottom bit of the address, so that it can be 92branched to using a BX instruction, and the program will start 93executing in Thumb mode straight away. 94</p> 95<a name="index-PE-import-table-prefixing"></a> 96<a name="index-_002d_002duse_002dnul_002dprefixed_002dimport_002dtables"></a> 97<p>The ‘<samp>--use-nul-prefixed-import-tables</samp>’ switch is specifying, that 98the import tables idata4 and idata5 have to be generated with a zero 99element prefix for import libraries. This is the old style to generate 100import tables. By default this option is turned off. 101</p> 102<a name="index-BE8"></a> 103<a name="index-_002d_002dbe8"></a> 104<p>The ‘<samp>--be8</samp>’ switch instructs <code>ld</code> to generate BE8 format 105executables. This option is only valid when linking big-endian 106objects - ie ones which have been assembled with the <samp>-EB</samp> 107option. The resulting image will contain big-endian data and 108little-endian code. 109</p> 110<a name="index-TARGET1"></a> 111<a name="index-_002d_002dtarget1_002drel"></a> 112<a name="index-_002d_002dtarget1_002dabs"></a> 113<p>The ‘<samp>R_ARM_TARGET1</samp>’ relocation is typically used for entries in the 114‘<samp>.init_array</samp>’ section. It is interpreted as either ‘<samp>R_ARM_REL32</samp>’ 115or ‘<samp>R_ARM_ABS32</samp>’, depending on the target. The ‘<samp>--target1-rel</samp>’ 116and ‘<samp>--target1-abs</samp>’ switches override the default. 117</p> 118<a name="index-TARGET2"></a> 119<a name="index-_002d_002dtarget2_003dtype"></a> 120<p>The ‘<samp>--target2=type</samp>’ switch overrides the default definition of the 121‘<samp>R_ARM_TARGET2</samp>’ relocation. Valid values for ‘<samp>type</samp>’, their 122meanings, and target defaults are as follows: 123</p><dl compact="compact"> 124<dt>‘<samp>rel</samp>’</dt> 125<dd><p>‘<samp>R_ARM_REL32</samp>’ (arm*-*-elf, arm*-*-eabi) 126</p></dd> 127<dt>‘<samp>abs</samp>’</dt> 128<dd><p>‘<samp>R_ARM_ABS32</samp>’ (arm*-*-symbianelf) 129</p></dd> 130<dt>‘<samp>got-rel</samp>’</dt> 131<dd><p>‘<samp>R_ARM_GOT_PREL</samp>’ (arm*-*-linux, arm*-*-*bsd) 132</p></dd> 133</dl> 134 135<a name="index-FIX_005fV4BX"></a> 136<a name="index-_002d_002dfix_002dv4bx"></a> 137<p>The ‘<samp>R_ARM_V4BX</samp>’ relocation (defined by the ARM AAELF 138specification) enables objects compiled for the ARMv4 architecture to be 139interworking-safe when linked with other objects compiled for ARMv4t, but 140also allows pure ARMv4 binaries to be built from the same ARMv4 objects. 141</p> 142<p>In the latter case, the switch <samp>--fix-v4bx</samp> must be passed to the 143linker, which causes v4t <code>BX rM</code> instructions to be rewritten as 144<code>MOV PC,rM</code>, since v4 processors do not have a <code>BX</code> instruction. 145</p> 146<p>In the former case, the switch should not be used, and ‘<samp>R_ARM_V4BX</samp>’ 147relocations are ignored. 148</p> 149<a name="index-FIX_005fV4BX_005fINTERWORKING"></a> 150<a name="index-_002d_002dfix_002dv4bx_002dinterworking"></a> 151<p>Replace <code>BX rM</code> instructions identified by ‘<samp>R_ARM_V4BX</samp>’ 152relocations with a branch to the following veneer: 153</p> 154<div class="smallexample"> 155<pre class="smallexample">TST rM, #1 156MOVEQ PC, rM 157BX Rn 158</pre></div> 159 160<p>This allows generation of libraries/applications that work on ARMv4 cores 161and are still interworking safe. Note that the above veneer clobbers the 162condition flags, so may cause incorrect program behavior in rare cases. 163</p> 164<a name="index-USE_005fBLX"></a> 165<a name="index-_002d_002duse_002dblx"></a> 166<p>The ‘<samp>--use-blx</samp>’ switch enables the linker to use ARM/Thumb 167BLX instructions (available on ARMv5t and above) in various 168situations. Currently it is used to perform calls via the PLT from Thumb 169code using BLX rather than using BX and a mode-switching stub before 170each PLT entry. This should lead to such calls executing slightly faster. 171</p> 172<p>This option is enabled implicitly for SymbianOS, so there is no need to 173specify it if you are using that target. 174</p> 175<a name="index-VFP11_005fDENORM_005fFIX"></a> 176<a name="index-_002d_002dvfp11_002ddenorm_002dfix"></a> 177<p>The ‘<samp>--vfp11-denorm-fix</samp>’ switch enables a link-time workaround for a 178bug in certain VFP11 coprocessor hardware, which sometimes allows 179instructions with denorm operands (which must be handled by support code) 180to have those operands overwritten by subsequent instructions before 181the support code can read the intended values. 182</p> 183<p>The bug may be avoided in scalar mode if you allow at least one 184intervening instruction between a VFP11 instruction which uses a register 185and another instruction which writes to the same register, or at least two 186intervening instructions if vector mode is in use. The bug only affects 187full-compliance floating-point mode: you do not need this workaround if 188you are using "runfast" mode. Please contact ARM for further details. 189</p> 190<p>If you know you are using buggy VFP11 hardware, you can 191enable this workaround by specifying the linker option 192‘<samp>--vfp-denorm-fix=scalar</samp>’ if you are using the VFP11 scalar 193mode only, or ‘<samp>--vfp-denorm-fix=vector</samp>’ if you are using 194vector mode (the latter also works for scalar code). The default is 195‘<samp>--vfp-denorm-fix=none</samp>’. 196</p> 197<p>If the workaround is enabled, instructions are scanned for 198potentially-troublesome sequences, and a veneer is created for each 199such sequence which may trigger the erratum. The veneer consists of the 200first instruction of the sequence and a branch back to the subsequent 201instruction. The original instruction is then replaced with a branch to 202the veneer. The extra cycles required to call and return from the veneer 203are sufficient to avoid the erratum in both the scalar and vector cases. 204</p> 205<a name="index-ARM1176-erratum-workaround"></a> 206<a name="index-_002d_002dfix_002darm1176"></a> 207<a name="index-_002d_002dno_002dfix_002darm1176"></a> 208<p>The ‘<samp>--fix-arm1176</samp>’ switch enables a link-time workaround for an erratum 209in certain ARM1176 processors. The workaround is enabled by default if you 210are targeting ARM v6 (excluding ARM v6T2) or earlier. It can be disabled 211unconditionally by specifying ‘<samp>--no-fix-arm1176</samp>’. 212</p> 213<p>Further information is available in the “ARM1176JZ-S and ARM1176JZF-S 214Programmer Advice Notice” available on the ARM documentation website at: 215http://infocenter.arm.com/. 216</p> 217<a name="index-STM32L4xx-erratum-workaround"></a> 218<a name="index-_002d_002dfix_002dstm32l4xx_002d629360"></a> 219 220<p>The ‘<samp>--fix-stm32l4xx-629360</samp>’ switch enables a link-time 221workaround for a bug in the bus matrix / memory controller for some of 222the STM32 Cortex-M4 based products (STM32L4xx). When accessing 223off-chip memory via the affected bus for bus reads of 9 words or more, 224the bus can generate corrupt data and/or abort. These are only 225core-initiated accesses (not DMA), and might affect any access: 226integer loads such as LDM, POP and floating-point loads such as VLDM, 227VPOP. Stores are not affected. 228</p> 229<p>The bug can be avoided by splitting memory accesses into the 230necessary chunks to keep bus reads below 8 words. 231</p> 232<p>The workaround is not enabled by default, this is equivalent to use 233‘<samp>--fix-stm32l4xx-629360=none</samp>’. If you know you are using buggy 234STM32L4xx hardware, you can enable the workaround by specifying the 235linker option ‘<samp>--fix-stm32l4xx-629360</samp>’, or the equivalent 236‘<samp>--fix-stm32l4xx-629360=default</samp>’. 237</p> 238<p>If the workaround is enabled, instructions are scanned for 239potentially-troublesome sequences, and a veneer is created for each 240such sequence which may trigger the erratum. The veneer consists in a 241replacement sequence emulating the behaviour of the original one and a 242branch back to the subsequent instruction. The original instruction is 243then replaced with a branch to the veneer. 244</p> 245<p>The workaround does not always preserve the memory access order for 246the LDMDB instruction, when the instruction loads the PC. 247</p> 248<p>The workaround is not able to handle problematic instructions when 249they are in the middle of an IT block, since a branch is not allowed 250there. In that case, the linker reports a warning and no replacement 251occurs. 252</p> 253<p>The workaround is not able to replace problematic instructions with a 254PC-relative branch instruction if the ‘<samp>.text</samp>’ section is too 255large. In that case, when the branch that replaces the original code 256cannot be encoded, the linker reports a warning and no replacement 257occurs. 258</p> 259<a name="index-NO_005fENUM_005fSIZE_005fWARNING"></a> 260<a name="index-_002d_002dno_002denum_002dsize_002dwarning"></a> 261<p>The <samp>--no-enum-size-warning</samp> switch prevents the linker from 262warning when linking object files that specify incompatible EABI 263enumeration size attributes. For example, with this switch enabled, 264linking of an object file using 32-bit enumeration values with another 265using enumeration values fitted into the smallest possible space will 266not be diagnosed. 267</p> 268<a name="index-NO_005fWCHAR_005fSIZE_005fWARNING"></a> 269<a name="index-_002d_002dno_002dwchar_002dsize_002dwarning"></a> 270<p>The <samp>--no-wchar-size-warning</samp> switch prevents the linker from 271warning when linking object files that specify incompatible EABI 272<code>wchar_t</code> size attributes. For example, with this switch enabled, 273linking of an object file using 32-bit <code>wchar_t</code> values with another 274using 16-bit <code>wchar_t</code> values will not be diagnosed. 275</p> 276<a name="index-PIC_005fVENEER"></a> 277<a name="index-_002d_002dpic_002dveneer"></a> 278<p>The ‘<samp>--pic-veneer</samp>’ switch makes the linker use PIC sequences for 279ARM/Thumb interworking veneers, even if the rest of the binary 280is not PIC. This avoids problems on uClinux targets where 281‘<samp>--emit-relocs</samp>’ is used to generate relocatable binaries. 282</p> 283<a name="index-STUB_005fGROUP_005fSIZE"></a> 284<a name="index-_002d_002dstub_002dgroup_002dsize_003dN"></a> 285<p>The linker will automatically generate and insert small sequences of 286code into a linked ARM ELF executable whenever an attempt is made to 287perform a function call to a symbol that is too far away. The 288placement of these sequences of instructions - called stubs - is 289controlled by the command-line option <samp>--stub-group-size=N</samp>. 290The placement is important because a poor choice can create a need for 291duplicate stubs, increasing the code size. The linker will try to 292group stubs together in order to reduce interruptions to the flow of 293code, but it needs guidance as to how big these groups should be and 294where they should be placed. 295</p> 296<p>The value of ‘<samp>N</samp>’, the parameter to the 297<samp>--stub-group-size=</samp> option controls where the stub groups are 298placed. If it is negative then all stubs are placed after the first 299branch that needs them. If it is positive then the stubs can be 300placed either before or after the branches that need them. If the 301value of ‘<samp>N</samp>’ is 1 (either +1 or -1) then the linker will choose 302exactly where to place groups of stubs, using its built in heuristics. 303A value of ‘<samp>N</samp>’ greater than 1 (or smaller than -1) tells the 304linker that a single group of stubs can service at most ‘<samp>N</samp>’ bytes 305from the input sections. 306</p> 307<p>The default, if <samp>--stub-group-size=</samp> is not specified, is 308‘<samp>N = +1</samp>’. 309</p> 310<p>Farcalls stubs insertion is fully supported for the ARM-EABI target 311only, because it relies on object files properties not present 312otherwise. 313</p> 314<a name="index-Cortex_002dA8-erratum-workaround"></a> 315<a name="index-_002d_002dfix_002dcortex_002da8"></a> 316<a name="index-_002d_002dno_002dfix_002dcortex_002da8"></a> 317<p>The ‘<samp>--fix-cortex-a8</samp>’ switch enables a link-time workaround for an erratum in certain Cortex-A8 processors. The workaround is enabled by default if you are targeting the ARM v7-A architecture profile. It can be enabled otherwise by specifying ‘<samp>--fix-cortex-a8</samp>’, or disabled unconditionally by specifying ‘<samp>--no-fix-cortex-a8</samp>’. 318</p> 319<p>The erratum only affects Thumb-2 code. Please contact ARM for further details. 320</p> 321<a name="index-Cortex_002dA53-erratum-835769-workaround"></a> 322<a name="index-_002d_002dfix_002dcortex_002da53_002d835769"></a> 323<a name="index-_002d_002dno_002dfix_002dcortex_002da53_002d835769"></a> 324<p>The ‘<samp>--fix-cortex-a53-835769</samp>’ switch enables a link-time workaround for erratum 835769 present on certain early revisions of Cortex-A53 processors. The workaround is disabled by default. It can be enabled by specifying ‘<samp>--fix-cortex-a53-835769</samp>’, or disabled unconditionally by specifying ‘<samp>--no-fix-cortex-a53-835769</samp>’. 325</p> 326<p>Please contact ARM for further details. 327</p> 328<a name="index-_002d_002dmerge_002dexidx_002dentries"></a> 329<a name="index-_002d_002dno_002dmerge_002dexidx_002dentries-1"></a> 330<a name="index-Merging-exidx-entries"></a> 331<p>The ‘<samp>--no-merge-exidx-entries</samp>’ switch disables the merging of adjacent exidx entries in debuginfo. 332</p> 333<a name="index-_002d_002dlong_002dplt"></a> 334<a name="index-32_002dbit-PLT-entries"></a> 335<p>The ‘<samp>--long-plt</samp>’ option enables the use of 16 byte PLT entries 336which support up to 4Gb of code. The default is to use 12 byte PLT 337entries which only support 512Mb of code. 338</p> 339<a name="index-_002d_002dno_002dapply_002ddynamic_002drelocs"></a> 340<a name="index-AArch64-rela-addend"></a> 341<p>The ‘<samp>--no-apply-dynamic-relocs</samp>’ option makes AArch64 linker do not apply 342link-time values for dynamic relocations. 343</p> 344<a name="index-Placement-of-SG-veneers"></a> 345<p>All SG veneers are placed in the special output section <code>.gnu.sgstubs</code>. 346Its start address must be set, either with the command-line option 347‘<samp>--section-start</samp>’ or in a linker script, to indicate where to place these 348veneers in memory. 349</p> 350<a name="index-_002d_002dcmse_002dimplib"></a> 351<a name="index-Secure-gateway-import-library"></a> 352<p>The ‘<samp>--cmse-implib</samp>’ option requests that the import libraries 353specified by the ‘<samp>--out-implib</samp>’ and ‘<samp>--in-implib</samp>’ options are 354secure gateway import libraries, suitable for linking a non-secure 355executable against secure code as per ARMv8-M Security Extensions. 356</p> 357<a name="index-_002d_002din_002dimplib_003dfile"></a> 358<a name="index-Input-import-library"></a> 359<p>The ‘<samp>--in-implib=file</samp>’ specifies an input import library whose symbols 360must keep the same address in the executable being produced. A warning is 361given if no ‘<samp>--out-implib</samp>’ is given but new symbols have been introduced 362in the executable that should be listed in its import library. Otherwise, if 363‘<samp>--out-implib</samp>’ is specified, the symbols are added to the output import 364library. A warning is also given if some symbols present in the input import 365library have disappeared from the executable. This option is only effective 366for Secure Gateway import libraries, ie. when ‘<samp>--cmse-implib</samp>’ is 367specified. 368</p> 369 370 371<hr> 372<div class="header"> 373<p> 374Next: <a href="HPPA-ELF32.html#HPPA-ELF32" accesskey="n" rel="next">HPPA ELF32</a>, Previous: <a href="M68HC11_002f68HC12.html#M68HC11_002f68HC12" accesskey="p" rel="previous">M68HC11/68HC12</a>, Up: <a href="Machine-Dependent.html#Machine-Dependent" accesskey="u" rel="up">Machine Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="LD-Index.html#LD-Index" title="Index" rel="index">Index</a>]</p> 375</div> 376 377 378 379</body> 380</html> 381