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A copy of the license is included in the 12section entitled "GNU Free Documentation License". 13 --> 14<!-- Created by GNU Texinfo 5.1, http://www.gnu.org/software/texinfo/ --> 15<head> 16<title>Using as: S12Z Addressing Modes</title> 17 18<meta name="description" content="Using as: S12Z Addressing Modes"> 19<meta name="keywords" content="Using as: S12Z Addressing Modes"> 20<meta name="resource-type" content="document"> 21<meta name="distribution" content="global"> 22<meta name="Generator" content="makeinfo"> 23<meta http-equiv="Content-Type" content="text/html; charset=utf-8"> 24<link href="index.html#Top" rel="start" title="Top"> 25<link href="AS-Index.html#AS-Index" rel="index" title="AS Index"> 26<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents"> 27<link href="S12Z-Syntax.html#S12Z-Syntax" rel="up" title="S12Z Syntax"> 28<link href="S12Z-Register-Notation.html#S12Z-Register-Notation" rel="next" title="S12Z Register Notation"> 29<link href="S12Z-Syntax-Overview.html#S12Z-Syntax-Overview" rel="previous" title="S12Z Syntax Overview"> 30<style type="text/css"> 31<!-- 32a.summary-letter {text-decoration: none} 33blockquote.smallquotation {font-size: smaller} 34div.display {margin-left: 3.2em} 35div.example {margin-left: 3.2em} 36div.indentedblock {margin-left: 3.2em} 37div.lisp {margin-left: 3.2em} 38div.smalldisplay {margin-left: 3.2em} 39div.smallexample {margin-left: 3.2em} 40div.smallindentedblock {margin-left: 3.2em; font-size: smaller} 41div.smalllisp {margin-left: 3.2em} 42kbd {font-style:oblique} 43pre.display {font-family: inherit} 44pre.format {font-family: inherit} 45pre.menu-comment {font-family: serif} 46pre.menu-preformatted {font-family: serif} 47pre.smalldisplay {font-family: inherit; font-size: smaller} 48pre.smallexample {font-size: smaller} 49pre.smallformat {font-family: inherit; font-size: smaller} 50pre.smalllisp {font-size: smaller} 51span.nocodebreak {white-space:nowrap} 52span.nolinebreak {white-space:nowrap} 53span.roman {font-family:serif; font-weight:normal} 54span.sansserif {font-family:sans-serif; font-weight:normal} 55ul.no-bullet {list-style: none} 56--> 57</style> 58 59 60</head> 61 62<body lang="en" bgcolor="#FFFFFF" text="#000000" link="#0000FF" vlink="#800080" alink="#FF0000"> 63<a name="S12Z-Addressing-Modes"></a> 64<div class="header"> 65<p> 66Next: <a href="S12Z-Register-Notation.html#S12Z-Register-Notation" accesskey="n" rel="next">S12Z Register Notation</a>, Previous: <a href="S12Z-Syntax-Overview.html#S12Z-Syntax-Overview" accesskey="p" rel="previous">S12Z Syntax Overview</a>, Up: <a href="S12Z-Syntax.html#S12Z-Syntax" accesskey="u" rel="up">S12Z Syntax</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p> 67</div> 68<hr> 69<a name="Addressing-Modes-3"></a> 70<h4 class="subsubsection">9.24.2.2 Addressing Modes</h4> 71<a name="index-S12Z-addressing-modes"></a> 72<a name="index-addressing-modes_002c-S12Z"></a> 73 74<p>The following addressing modes are understood for the S12Z. 75</p><dl compact="compact"> 76<dt><em>Immediate</em></dt> 77<dd><p>‘<samp>#<var>number</var></samp>’ 78</p> 79</dd> 80<dt><em>Immediate Bit Field</em></dt> 81<dd><p>‘<samp>#<var>width</var>:<var>offset</var></samp>’ 82</p> 83<p>Bit field instructions in the immediate mode require the width and offset to 84be specified. 85The <var>width</var> parameter specifies the number of bits in the field. 86It should be a number in the range [1,32]. 87<var>Offset</var> determines the position within the field where the operation 88should start. 89It should be a number in the range [0,31]. 90</p> 91</dd> 92<dt><em>Relative</em></dt> 93<dd><p>‘<samp>*<var>symbol</var></samp>’, or ‘<samp>*[+-]<var>digits</var></samp>’ 94</p> 95<p>Program counter relative addresses have a width of 15 bits. 96Thus, they must be within the range [-32768, 32767]. 97</p> 98</dd> 99<dt><em>Register</em></dt> 100<dd><p>‘<samp><var>reg</var></samp>’ 101</p> 102<a name="index-register-names_002c-S12Z"></a> 103<p>Some instructions accept a register as an operand. 104In general, <var>reg</var> may be a 105data register (‘<samp>D0</samp>’, ‘<samp>D1</samp>’ … ‘<samp>D7</samp>’), 106the ‘<samp>X</samp>’ register or the ‘<samp>Y</samp>’ register. 107</p> 108<p>A few instructions accept as an argument the stack pointer 109register (‘<samp>S</samp>’), and/or the program counter (‘<samp>P</samp>’). 110</p> 111<p>Some very special instructions accept arguments which refer to the 112condition code register. For these arguments the syntax is 113‘<samp>CCR</samp>’, ‘<samp>CCH</samp>’ or ‘<samp>CCL</samp>’ which refer to the complete 114condition code register, the condition code register high byte 115and the condition code register low byte respectively. 116</p> 117 118</dd> 119<dt><em>Absolute Direct</em></dt> 120<dd><p>‘<samp><var>symbol</var></samp>’, or ‘<samp><var>digits</var></samp>’ 121</p> 122</dd> 123<dt><em>Absolute Indirect</em></dt> 124<dd><p>‘<samp>[<var>symbol</var></samp>’, or ‘<samp><var>digits</var>]</samp>’ 125</p> 126 127</dd> 128<dt><em>Constant Offset Indexed</em></dt> 129<dd><p>‘<samp>(<var>number</var>,<var>reg</var>)</samp>’ 130</p> 131<p><var>Reg</var> may be either ‘<samp>X</samp>’, ‘<samp>Y</samp>’, ‘<samp>S</samp>’ or 132‘<samp>P</samp>’ or one of the data registers ‘<samp>D0</samp>’, ‘<samp>D1</samp>’ … 133‘<samp>D7</samp>’. 134If any of the registers ‘<samp>D2</samp>’ … ‘<samp>D5</samp>’ are specified, then the 135register value is treated as a signed value. 136Otherwise it is treated as unsigned. 137<var>Number</var> may be any integer in the range [-8388608,8388607]. 138</p> 139</dd> 140<dt><em>Offset Indexed Indirect</em></dt> 141<dd><p>‘<samp>[<var>number</var>,<var>reg</var>]</samp>’ 142</p> 143<p><var>Reg</var> may be either ‘<samp>X</samp>’, ‘<samp>Y</samp>’, ‘<samp>S</samp>’ or 144‘<samp>P</samp>’. 145<var>Number</var> may be any integer in the range [-8388608,8388607]. 146</p> 147</dd> 148<dt><em>Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement</em></dt> 149<dd><p>‘<samp>-<var>reg</var></samp>’, 150‘<samp>+<var>reg</var></samp>’, 151‘<samp><var>reg</var>-</samp>’ or 152‘<samp><var>reg</var>+</samp>’ 153</p> 154<p>This addressing mode is typically used to access a value at an address, 155and simultaneously to increment/decrement the register pointing to that 156address. 157Thus <var>reg</var> may be any of the 24 bit registers ‘<samp>X</samp>’, ‘<samp>Y</samp>’, or 158‘<samp>S</samp>’. 159Pre-increment and post-decrement are not available for 160register ‘<samp>S</samp>’ (only post-increment and pre-decrement are available). 161</p> 162</dd> 163<dt><em>Register Offset Direct</em></dt> 164<dd><p>‘<samp>(<var>data-reg</var>,<var>reg</var>)</samp>’ 165</p> 166<p><var>Reg</var> can be either ‘<samp>X</samp>’, ‘<samp>Y</samp>’, or ‘<samp>S</samp>’. 167<var>Data-reg</var> 168must be one of the data registers ‘<samp>D0</samp>’, ‘<samp>D1</samp>’ … ‘<samp>D7</samp>’. 169If any of the registers ‘<samp>D2</samp>’ … ‘<samp>D5</samp>’ are specified, then 170the register value is treated as a signed value. 171Otherwise it is treated as unsigned. 172</p> 173</dd> 174<dt><em>Register Offset Indirect</em></dt> 175<dd><p>‘<samp>[<var>data-reg</var>,<var>reg</var>]</samp>’ 176</p> 177<p><var>Reg</var> can be either ‘<samp>X</samp>’ or ‘<samp>Y</samp>’. 178<var>Data-reg</var> 179must be one of the data registers ‘<samp>D0</samp>’, ‘<samp>D1</samp>’ … ‘<samp>D7</samp>’. 180If any of the registers ‘<samp>D2</samp>’ … ‘<samp>D5</samp>’ are specified, then 181the register value is treated as a signed value. 182Otherwise it is treated as unsigned. 183</p></dd> 184</dl> 185 186<p>For example: 187</p> 188<div class="smallexample"> 189<pre class="smallexample"> trap #197 ;; Immediate mode 190 bra *+49 ;; Relative mode 191 bra .L0 ;; ditto 192 jmp 0xFE0034 ;; Absolute direct mode 193 jmp [0xFD0012] ;; Absolute indirect mode 194 inc.b (4,x) ;; Constant offset indexed mode 195 jsr (45, d0) ;; ditto 196 dec.w [4,y] ;; Constant offset indexed indirect mode 197 clr.p (-s) ;; Pre-decrement mode 198 neg.l (d0, s) ;; Register offset direct mode 199 com.b [d1, x] ;; Register offset indirect mode 200 psh cch ;; Register mode 201</pre></div> 202 203<hr> 204<div class="header"> 205<p> 206Next: <a href="S12Z-Register-Notation.html#S12Z-Register-Notation" accesskey="n" rel="next">S12Z Register Notation</a>, Previous: <a href="S12Z-Syntax-Overview.html#S12Z-Syntax-Overview" accesskey="p" rel="previous">S12Z Syntax Overview</a>, Up: <a href="S12Z-Syntax.html#S12Z-Syntax" accesskey="u" rel="up">S12Z Syntax</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p> 207</div> 208 209 210 211</body> 212</html> 213