1<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd"> 2<html> 3<!-- This file documents the GNU Assembler "as". 4 5Copyright (C) 1991-2021 Free Software Foundation, Inc. 6 7Permission is granted to copy, distribute and/or modify this document 8under the terms of the GNU Free Documentation License, Version 1.3 9or any later version published by the Free Software Foundation; 10with no Invariant Sections, with no Front-Cover Texts, and with no 11Back-Cover Texts. A copy of the license is included in the 12section entitled "GNU Free Documentation License". 13 --> 14<!-- Created by GNU Texinfo 5.1, http://www.gnu.org/software/texinfo/ --> 15<head> 16<title>Using as: MIPS Options</title> 17 18<meta name="description" content="Using as: MIPS Options"> 19<meta name="keywords" content="Using as: MIPS Options"> 20<meta name="resource-type" content="document"> 21<meta name="distribution" content="global"> 22<meta name="Generator" content="makeinfo"> 23<meta http-equiv="Content-Type" content="text/html; charset=utf-8"> 24<link href="index.html#Top" rel="start" title="Top"> 25<link href="AS-Index.html#AS-Index" rel="index" title="AS Index"> 26<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents"> 27<link href="MIPS_002dDependent.html#MIPS_002dDependent" rel="up" title="MIPS-Dependent"> 28<link href="MIPS-Macros.html#MIPS-Macros" rel="next" title="MIPS Macros"> 29<link href="MIPS_002dDependent.html#MIPS_002dDependent" rel="previous" title="MIPS-Dependent"> 30<style type="text/css"> 31<!-- 32a.summary-letter {text-decoration: none} 33blockquote.smallquotation {font-size: smaller} 34div.display {margin-left: 3.2em} 35div.example {margin-left: 3.2em} 36div.indentedblock {margin-left: 3.2em} 37div.lisp {margin-left: 3.2em} 38div.smalldisplay {margin-left: 3.2em} 39div.smallexample {margin-left: 3.2em} 40div.smallindentedblock {margin-left: 3.2em; font-size: smaller} 41div.smalllisp {margin-left: 3.2em} 42kbd {font-style:oblique} 43pre.display {font-family: inherit} 44pre.format {font-family: inherit} 45pre.menu-comment {font-family: serif} 46pre.menu-preformatted {font-family: serif} 47pre.smalldisplay {font-family: inherit; font-size: smaller} 48pre.smallexample {font-size: smaller} 49pre.smallformat {font-family: inherit; font-size: smaller} 50pre.smalllisp {font-size: smaller} 51span.nocodebreak {white-space:nowrap} 52span.nolinebreak {white-space:nowrap} 53span.roman {font-family:serif; font-weight:normal} 54span.sansserif {font-family:sans-serif; font-weight:normal} 55ul.no-bullet {list-style: none} 56--> 57</style> 58 59 60</head> 61 62<body lang="en" bgcolor="#FFFFFF" text="#000000" link="#0000FF" vlink="#800080" alink="#FF0000"> 63<a name="MIPS-Options"></a> 64<div class="header"> 65<p> 66Next: <a href="MIPS-Macros.html#MIPS-Macros" accesskey="n" rel="next">MIPS Macros</a>, Up: <a href="MIPS_002dDependent.html#MIPS_002dDependent" accesskey="u" rel="up">MIPS-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p> 67</div> 68<hr> 69<a name="Assembler-options"></a> 70<h4 class="subsection">9.27.1 Assembler options</h4> 71 72<p>The MIPS configurations of <small>GNU</small> <code>as</code> support these 73special options: 74</p> 75<dl compact="compact"> 76<dd><a name="index-_002dG-option-_0028MIPS_0029"></a> 77</dd> 78<dt><code>-G <var>num</var></code></dt> 79<dd><p>Set the “small data” limit to <var>n</var> bytes. The default limit is 8 bytes. 80See <a href="MIPS-Small-Data.html#MIPS-Small-Data">Controlling the use of small data accesses</a>. 81</p> 82<a name="index-_002dEB-option-_0028MIPS_0029"></a> 83<a name="index-_002dEL-option-_0028MIPS_0029"></a> 84<a name="index-MIPS-big_002dendian-output"></a> 85<a name="index-MIPS-little_002dendian-output"></a> 86<a name="index-big_002dendian-output_002c-MIPS"></a> 87<a name="index-little_002dendian-output_002c-MIPS"></a> 88</dd> 89<dt><code>-EB</code></dt> 90<dt><code>-EL</code></dt> 91<dd><p>Any MIPS configuration of <code>as</code> can select big-endian or 92little-endian output at run time (unlike the other <small>GNU</small> development 93tools, which must be configured for one or the other). Use ‘<samp>-EB</samp>’ 94to select big-endian output, and ‘<samp>-EL</samp>’ for little-endian. 95</p> 96</dd> 97<dt><code>-KPIC</code></dt> 98<dd><a name="index-PIC-selection_002c-MIPS"></a> 99<a name="index-_002dKPIC-option_002c-MIPS"></a> 100<p>Generate SVR4-style PIC. This option tells the assembler to generate 101SVR4-style position-independent macro expansions. It also tells the 102assembler to mark the output file as PIC. 103</p> 104</dd> 105<dt><code>-mvxworks-pic</code></dt> 106<dd><a name="index-_002dmvxworks_002dpic-option_002c-MIPS"></a> 107<p>Generate VxWorks PIC. This option tells the assembler to generate 108VxWorks-style position-independent macro expansions. 109</p> 110<a name="index-MIPS-architecture-options"></a> 111</dd> 112<dt><code>-mips1</code></dt> 113<dt><code>-mips2</code></dt> 114<dt><code>-mips3</code></dt> 115<dt><code>-mips4</code></dt> 116<dt><code>-mips5</code></dt> 117<dt><code>-mips32</code></dt> 118<dt><code>-mips32r2</code></dt> 119<dt><code>-mips32r3</code></dt> 120<dt><code>-mips32r5</code></dt> 121<dt><code>-mips32r6</code></dt> 122<dt><code>-mips64</code></dt> 123<dt><code>-mips64r2</code></dt> 124<dt><code>-mips64r3</code></dt> 125<dt><code>-mips64r5</code></dt> 126<dt><code>-mips64r6</code></dt> 127<dd><p>Generate code for a particular MIPS Instruction Set Architecture level. 128‘<samp>-mips1</samp>’ corresponds to the R2000 and R3000 processors, 129‘<samp>-mips2</samp>’ to the R6000 processor, ‘<samp>-mips3</samp>’ to the 130R4000 processor, and ‘<samp>-mips4</samp>’ to the R8000 and R10000 processors. 131‘<samp>-mips5</samp>’, ‘<samp>-mips32</samp>’, ‘<samp>-mips32r2</samp>’, ‘<samp>-mips32r3</samp>’, 132‘<samp>-mips32r5</samp>’, ‘<samp>-mips32r6</samp>’, ‘<samp>-mips64</samp>’, ‘<samp>-mips64r2</samp>’, 133‘<samp>-mips64r3</samp>’, ‘<samp>-mips64r5</samp>’, and ‘<samp>-mips64r6</samp>’ correspond to 134generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 135Release 5, MIPS32 Release 6, MIPS64, and MIPS64 Release 2, MIPS64 136Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA processors, 137respectively. You can also switch instruction sets during the assembly; 138see <a href="MIPS-ISA.html#MIPS-ISA">Directives to override the ISA level</a>. 139</p> 140</dd> 141<dt><code>-mgp32</code></dt> 142<dt><code>-mfp32</code></dt> 143<dd><p>Some macros have different expansions for 32-bit and 64-bit registers. 144The register sizes are normally inferred from the ISA and ABI, but these 145flags force a certain group of registers to be treated as 32 bits wide at 146all times. ‘<samp>-mgp32</samp>’ controls the size of general-purpose registers 147and ‘<samp>-mfp32</samp>’ controls the size of floating-point registers. 148</p> 149<p>The <code>.set gp=32</code> and <code>.set fp=32</code> directives allow the size 150of registers to be changed for parts of an object. The default value is 151restored by <code>.set gp=default</code> and <code>.set fp=default</code>. 152</p> 153<p>On some MIPS variants there is a 32-bit mode flag; when this flag is 154set, 64-bit instructions generate a trap. Also, some 32-bit OSes only 155save the 32-bit registers on a context switch, so it is essential never 156to use the 64-bit registers. 157</p> 158</dd> 159<dt><code>-mgp64</code></dt> 160<dt><code>-mfp64</code></dt> 161<dd><p>Assume that 64-bit registers are available. This is provided in the 162interests of symmetry with ‘<samp>-mgp32</samp>’ and ‘<samp>-mfp32</samp>’. 163</p> 164<p>The <code>.set gp=64</code> and <code>.set fp=64</code> directives allow the size 165of registers to be changed for parts of an object. The default value is 166restored by <code>.set gp=default</code> and <code>.set fp=default</code>. 167</p> 168</dd> 169<dt><code>-mfpxx</code></dt> 170<dd><p>Make no assumptions about whether 32-bit or 64-bit floating-point 171registers are available. This is provided to support having modules 172compatible with either ‘<samp>-mfp32</samp>’ or ‘<samp>-mfp64</samp>’. This option can 173only be used with MIPS II and above. 174</p> 175<p>The <code>.set fp=xx</code> directive allows a part of an object to be marked 176as not making assumptions about 32-bit or 64-bit FP registers. The 177default value is restored by <code>.set fp=default</code>. 178</p> 179</dd> 180<dt><code>-modd-spreg</code></dt> 181<dt><code>-mno-odd-spreg</code></dt> 182<dd><p>Enable use of floating-point operations on odd-numbered single-precision 183registers when supported by the ISA. ‘<samp>-mfpxx</samp>’ implies 184‘<samp>-mno-odd-spreg</samp>’, otherwise the default is ‘<samp>-modd-spreg</samp>’ 185</p> 186</dd> 187<dt><code>-mips16</code></dt> 188<dt><code>-no-mips16</code></dt> 189<dd><p>Generate code for the MIPS 16 processor. This is equivalent to putting 190<code>.module mips16</code> at the start of the assembly file. ‘<samp>-no-mips16</samp>’ 191turns off this option. 192</p> 193</dd> 194<dt><code>-mmips16e2</code></dt> 195<dt><code>-mno-mips16e2</code></dt> 196<dd><p>Enable the use of MIPS16e2 instructions in MIPS16 mode. This is equivalent 197to putting <code>.module mips16e2</code> at the start of the assembly file. 198‘<samp>-mno-mips16e2</samp>’ turns off this option. 199</p> 200</dd> 201<dt><code>-mmicromips</code></dt> 202<dt><code>-mno-micromips</code></dt> 203<dd><p>Generate code for the microMIPS processor. This is equivalent to putting 204<code>.module micromips</code> at the start of the assembly file. 205‘<samp>-mno-micromips</samp>’ turns off this option. This is equivalent to putting 206<code>.module nomicromips</code> at the start of the assembly file. 207</p> 208</dd> 209<dt><code>-msmartmips</code></dt> 210<dt><code>-mno-smartmips</code></dt> 211<dd><p>Enables the SmartMIPS extensions to the MIPS32 instruction set, which 212provides a number of new instructions which target smartcard and 213cryptographic applications. This is equivalent to putting 214<code>.module smartmips</code> at the start of the assembly file. 215‘<samp>-mno-smartmips</samp>’ turns off this option. 216</p> 217</dd> 218<dt><code>-mips3d</code></dt> 219<dt><code>-no-mips3d</code></dt> 220<dd><p>Generate code for the MIPS-3D Application Specific Extension. 221This tells the assembler to accept MIPS-3D instructions. 222‘<samp>-no-mips3d</samp>’ turns off this option. 223</p> 224</dd> 225<dt><code>-mdmx</code></dt> 226<dt><code>-no-mdmx</code></dt> 227<dd><p>Generate code for the MDMX Application Specific Extension. 228This tells the assembler to accept MDMX instructions. 229‘<samp>-no-mdmx</samp>’ turns off this option. 230</p> 231</dd> 232<dt><code>-mdsp</code></dt> 233<dt><code>-mno-dsp</code></dt> 234<dd><p>Generate code for the DSP Release 1 Application Specific Extension. 235This tells the assembler to accept DSP Release 1 instructions. 236‘<samp>-mno-dsp</samp>’ turns off this option. 237</p> 238</dd> 239<dt><code>-mdspr2</code></dt> 240<dt><code>-mno-dspr2</code></dt> 241<dd><p>Generate code for the DSP Release 2 Application Specific Extension. 242This option implies ‘<samp>-mdsp</samp>’. 243This tells the assembler to accept DSP Release 2 instructions. 244‘<samp>-mno-dspr2</samp>’ turns off this option. 245</p> 246</dd> 247<dt><code>-mdspr3</code></dt> 248<dt><code>-mno-dspr3</code></dt> 249<dd><p>Generate code for the DSP Release 3 Application Specific Extension. 250This option implies ‘<samp>-mdsp</samp>’ and ‘<samp>-mdspr2</samp>’. 251This tells the assembler to accept DSP Release 3 instructions. 252‘<samp>-mno-dspr3</samp>’ turns off this option. 253</p> 254</dd> 255<dt><code>-mmt</code></dt> 256<dt><code>-mno-mt</code></dt> 257<dd><p>Generate code for the MT Application Specific Extension. 258This tells the assembler to accept MT instructions. 259‘<samp>-mno-mt</samp>’ turns off this option. 260</p> 261</dd> 262<dt><code>-mmcu</code></dt> 263<dt><code>-mno-mcu</code></dt> 264<dd><p>Generate code for the MCU Application Specific Extension. 265This tells the assembler to accept MCU instructions. 266‘<samp>-mno-mcu</samp>’ turns off this option. 267</p> 268</dd> 269<dt><code>-mmsa</code></dt> 270<dt><code>-mno-msa</code></dt> 271<dd><p>Generate code for the MIPS SIMD Architecture Extension. 272This tells the assembler to accept MSA instructions. 273‘<samp>-mno-msa</samp>’ turns off this option. 274</p> 275</dd> 276<dt><code>-mxpa</code></dt> 277<dt><code>-mno-xpa</code></dt> 278<dd><p>Generate code for the MIPS eXtended Physical Address (XPA) Extension. 279This tells the assembler to accept XPA instructions. 280‘<samp>-mno-xpa</samp>’ turns off this option. 281</p> 282</dd> 283<dt><code>-mvirt</code></dt> 284<dt><code>-mno-virt</code></dt> 285<dd><p>Generate code for the Virtualization Application Specific Extension. 286This tells the assembler to accept Virtualization instructions. 287‘<samp>-mno-virt</samp>’ turns off this option. 288</p> 289</dd> 290<dt><code>-mcrc</code></dt> 291<dt><code>-mno-crc</code></dt> 292<dd><p>Generate code for the cyclic redundancy check (CRC) Application Specific 293Extension. This tells the assembler to accept CRC instructions. 294‘<samp>-mno-crc</samp>’ turns off this option. 295</p> 296</dd> 297<dt><code>-mginv</code></dt> 298<dt><code>-mno-ginv</code></dt> 299<dd><p>Generate code for the Global INValidate (GINV) Application Specific 300Extension. This tells the assembler to accept GINV instructions. 301‘<samp>-mno-ginv</samp>’ turns off this option. 302</p> 303</dd> 304<dt><code>-mloongson-mmi</code></dt> 305<dt><code>-mno-loongson-mmi</code></dt> 306<dd><p>Generate code for the Loongson MultiMedia extensions Instructions (MMI) 307Application Specific Extension. This tells the assembler to accept MMI 308instructions. 309‘<samp>-mno-loongson-mmi</samp>’ turns off this option. 310</p> 311</dd> 312<dt><code>-mloongson-cam</code></dt> 313<dt><code>-mno-loongson-cam</code></dt> 314<dd><p>Generate code for the Loongson Content Address Memory (CAM) 315Application Specific Extension. This tells the assembler to accept CAM 316instructions. 317‘<samp>-mno-loongson-cam</samp>’ turns off this option. 318</p> 319</dd> 320<dt><code>-mloongson-ext</code></dt> 321<dt><code>-mno-loongson-ext</code></dt> 322<dd><p>Generate code for the Loongson EXTensions (EXT) instructions 323Application Specific Extension. This tells the assembler to accept EXT 324instructions. 325‘<samp>-mno-loongson-ext</samp>’ turns off this option. 326</p> 327</dd> 328<dt><code>-mloongson-ext2</code></dt> 329<dt><code>-mno-loongson-ext2</code></dt> 330<dd><p>Generate code for the Loongson EXTensions R2 (EXT2) instructions 331Application Specific Extension. This tells the assembler to accept EXT2 332instructions. 333‘<samp>-mno-loongson-ext2</samp>’ turns off this option. 334</p> 335</dd> 336<dt><code>-minsn32</code></dt> 337<dt><code>-mno-insn32</code></dt> 338<dd><p>Only use 32-bit instruction encodings when generating code for the 339microMIPS processor. This option inhibits the use of any 16-bit 340instructions. This is equivalent to putting <code>.set insn32</code> at 341the start of the assembly file. ‘<samp>-mno-insn32</samp>’ turns off this 342option. This is equivalent to putting <code>.set noinsn32</code> at the 343start of the assembly file. By default ‘<samp>-mno-insn32</samp>’ is 344selected, allowing all instructions to be used. 345</p> 346</dd> 347<dt><code>-mfix7000</code></dt> 348<dt><code>-mno-fix7000</code></dt> 349<dd><p>Cause nops to be inserted if the read of the destination register 350of an mfhi or mflo instruction occurs in the following two instructions. 351</p> 352</dd> 353<dt><code>-mfix-rm7000</code></dt> 354<dt><code>-mno-fix-rm7000</code></dt> 355<dd><p>Cause nops to be inserted if a dmult or dmultu instruction is 356followed by a load instruction. 357</p> 358</dd> 359<dt><code>-mfix-loongson2f-jump</code></dt> 360<dt><code>-mno-fix-loongson2f-jump</code></dt> 361<dd><p>Eliminate instruction fetch from outside 256M region to work around the 362Loongson2F ‘<samp>jump</samp>’ instructions. Without it, under extreme cases, 363the kernel may crash. The issue has been solved in latest processor 364batches, but this fix has no side effect to them. 365</p> 366</dd> 367<dt><code>-mfix-loongson2f-nop</code></dt> 368<dt><code>-mno-fix-loongson2f-nop</code></dt> 369<dd><p>Replace nops by <code>or at,at,zero</code> to work around the Loongson2F 370‘<samp>nop</samp>’ errata. Without it, under extreme cases, the CPU might 371deadlock. The issue has been solved in later Loongson2F batches, but 372this fix has no side effect to them. 373</p> 374</dd> 375<dt><code>-mfix-loongson3-llsc</code></dt> 376<dt><code>-mno-fix-loongson3-llsc</code></dt> 377<dd><p>Insert ‘<samp>sync</samp>’ before ‘<samp>ll</samp>’ and ‘<samp>lld</samp>’ to work around 378Loongson3 LLSC errata. Without it, under extrame cases, the CPU might 379deadlock. The default can be controlled by the 380<samp>--enable-mips-fix-loongson3-llsc=[yes|no]</samp> configure option. 381</p> 382</dd> 383<dt><code>-mfix-vr4120</code></dt> 384<dt><code>-mno-fix-vr4120</code></dt> 385<dd><p>Insert nops to work around certain VR4120 errata. This option is 386intended to be used on GCC-generated code: it is not designed to catch 387all problems in hand-written assembler code. 388</p> 389</dd> 390<dt><code>-mfix-vr4130</code></dt> 391<dt><code>-mno-fix-vr4130</code></dt> 392<dd><p>Insert nops to work around the VR4130 ‘<samp>mflo</samp>’/‘<samp>mfhi</samp>’ errata. 393</p> 394</dd> 395<dt><code>-mfix-24k</code></dt> 396<dt><code>-mno-fix-24k</code></dt> 397<dd><p>Insert nops to work around the 24K ‘<samp>eret</samp>’/‘<samp>deret</samp>’ errata. 398</p> 399</dd> 400<dt><code>-mfix-cn63xxp1</code></dt> 401<dt><code>-mno-fix-cn63xxp1</code></dt> 402<dd><p>Replace <code>pref</code> hints 0 - 4 and 6 - 24 with hint 28 to work around 403certain CN63XXP1 errata. 404</p> 405</dd> 406<dt><code>-mfix-r5900</code></dt> 407<dt><code>-mno-fix-r5900</code></dt> 408<dd><p>Do not attempt to schedule the preceding instruction into the delay slot 409of a branch instruction placed at the end of a short loop of six 410instructions or fewer and always schedule a <code>nop</code> instruction there 411instead. The short loop bug under certain conditions causes loops to 412execute only once or twice, due to a hardware bug in the R5900 chip. 413</p> 414</dd> 415<dt><code>-m4010</code></dt> 416<dt><code>-no-m4010</code></dt> 417<dd><p>Generate code for the LSI R4010 chip. This tells the assembler to 418accept the R4010-specific instructions (‘<samp>addciu</samp>’, ‘<samp>ffc</samp>’, 419etc.), and to not schedule ‘<samp>nop</samp>’ instructions around accesses to 420the ‘<samp>HI</samp>’ and ‘<samp>LO</samp>’ registers. ‘<samp>-no-m4010</samp>’ turns off this 421option. 422</p> 423</dd> 424<dt><code>-m4650</code></dt> 425<dt><code>-no-m4650</code></dt> 426<dd><p>Generate code for the MIPS R4650 chip. This tells the assembler to accept 427the ‘<samp>mad</samp>’ and ‘<samp>madu</samp>’ instruction, and to not schedule ‘<samp>nop</samp>’ 428instructions around accesses to the ‘<samp>HI</samp>’ and ‘<samp>LO</samp>’ registers. 429‘<samp>-no-m4650</samp>’ turns off this option. 430</p> 431</dd> 432<dt><code>-m3900</code></dt> 433<dt><code>-no-m3900</code></dt> 434<dt><code>-m4100</code></dt> 435<dt><code>-no-m4100</code></dt> 436<dd><p>For each option ‘<samp>-m<var>nnnn</var></samp>’, generate code for the MIPS 437R<var>nnnn</var> chip. This tells the assembler to accept instructions 438specific to that chip, and to schedule for that chip’s hazards. 439</p> 440</dd> 441<dt><code>-march=<var>cpu</var></code></dt> 442<dd><p>Generate code for a particular MIPS CPU. It is exactly equivalent to 443‘<samp>-m<var>cpu</var></samp>’, except that there are more value of <var>cpu</var> 444understood. Valid <var>cpu</var> value are: 445</p> 446<blockquote> 447<p>2000, 4483000, 4493900, 4504000, 4514010, 4524100, 4534111, 454vr4120, 455vr4130, 456vr4181, 4574300, 4584400, 4594600, 4604650, 4615000, 462rm5200, 463rm5230, 464rm5231, 465rm5261, 466rm5721, 467vr5400, 468vr5500, 4696000, 470rm7000, 4718000, 472rm9000, 47310000, 47412000, 47514000, 47616000, 4774kc, 4784km, 4794kp, 4804ksc, 4814kec, 4824kem, 4834kep, 4844ksd, 485m4k, 486m4kp, 487m14k, 488m14kc, 489m14ke, 490m14kec, 49124kc, 49224kf2_1, 49324kf, 49424kf1_1, 49524kec, 49624kef2_1, 49724kef, 49824kef1_1, 49934kc, 50034kf2_1, 50134kf, 50234kf1_1, 50334kn, 50474kc, 50574kf2_1, 50674kf, 50774kf1_1, 50874kf3_2, 5091004kc, 5101004kf2_1, 5111004kf, 5121004kf1_1, 513interaptiv, 514interaptiv-mr2, 515m5100, 516m5101, 517p5600, 5185kc, 5195kf, 52020kc, 52125kf, 522sb1, 523sb1a, 524i6400, 525i6500, 526p6600, 527loongson2e, 528loongson2f, 529gs464, 530gs464e, 531gs264e, 532octeon, 533octeon+, 534octeon2, 535octeon3, 536xlr, 537xlp 538</p></blockquote> 539 540<p>For compatibility reasons, ‘<samp><var>n</var>x</samp>’ and ‘<samp><var>b</var>fx</samp>’ are 541accepted as synonyms for ‘<samp><var>n</var>f1_1</samp>’. These values are 542deprecated. 543</p> 544</dd> 545<dt><code>-mtune=<var>cpu</var></code></dt> 546<dd><p>Schedule and tune for a particular MIPS CPU. Valid <var>cpu</var> values are 547identical to ‘<samp>-march=<var>cpu</var></samp>’. 548</p> 549</dd> 550<dt><code>-mabi=<var>abi</var></code></dt> 551<dd><p>Record which ABI the source code uses. The recognized arguments 552are: ‘<samp>32</samp>’, ‘<samp>n32</samp>’, ‘<samp>o64</samp>’, ‘<samp>64</samp>’ and ‘<samp>eabi</samp>’. 553</p> 554</dd> 555<dt><code>-msym32</code></dt> 556<dt><code>-mno-sym32</code></dt> 557<dd><a name="index-_002dmsym32"></a> 558<a name="index-_002dmno_002dsym32"></a> 559<p>Equivalent to adding <code>.set sym32</code> or <code>.set nosym32</code> to 560the beginning of the assembler input. See <a href="MIPS-Symbol-Sizes.html#MIPS-Symbol-Sizes">MIPS Symbol Sizes</a>. 561</p> 562<a name="index-_002dnocpp-ignored-_0028MIPS_0029"></a> 563</dd> 564<dt><code>-nocpp</code></dt> 565<dd><p>This option is ignored. It is accepted for command-line compatibility with 566other assemblers, which use it to turn off C style preprocessing. With 567<small>GNU</small> <code>as</code>, there is no need for ‘<samp>-nocpp</samp>’, because the 568<small>GNU</small> assembler itself never runs the C preprocessor. 569</p> 570</dd> 571<dt><code>-msoft-float</code></dt> 572<dt><code>-mhard-float</code></dt> 573<dd><p>Disable or enable floating-point instructions. Note that by default 574floating-point instructions are always allowed even with CPU targets 575that don’t have support for these instructions. 576</p> 577</dd> 578<dt><code>-msingle-float</code></dt> 579<dt><code>-mdouble-float</code></dt> 580<dd><p>Disable or enable double-precision floating-point operations. Note 581that by default double-precision floating-point operations are always 582allowed even with CPU targets that don’t have support for these 583operations. 584</p> 585</dd> 586<dt><code>--construct-floats</code></dt> 587<dt><code>--no-construct-floats</code></dt> 588<dd><p>The <code>--no-construct-floats</code> option disables the construction of 589double width floating point constants by loading the two halves of the 590value into the two single width floating point registers that make up 591the double width register. This feature is useful if the processor 592support the FR bit in its status register, and this bit is known (by 593the programmer) to be set. This bit prevents the aliasing of the double 594width register by the single width registers. 595</p> 596<p>By default <code>--construct-floats</code> is selected, allowing construction 597of these floating point constants. 598</p> 599</dd> 600<dt><code>--relax-branch</code></dt> 601<dt><code>--no-relax-branch</code></dt> 602<dd><p>The ‘<samp>--relax-branch</samp>’ option enables the relaxation of out-of-range 603branches. Any branches whose target cannot be reached directly are 604converted to a small instruction sequence including an inverse-condition 605branch to the physically next instruction, and a jump to the original 606target is inserted between the two instructions. In PIC code the jump 607will involve further instructions for address calculation. 608</p> 609<p>The <code>BC1ANY2F</code>, <code>BC1ANY2T</code>, <code>BC1ANY4F</code>, <code>BC1ANY4T</code>, 610<code>BPOSGE32</code> and <code>BPOSGE64</code> instructions are excluded from 611relaxation, because they have no complementing counterparts. They could 612be relaxed with the use of a longer sequence involving another branch, 613however this has not been implemented and if their target turns out of 614reach, they produce an error even if branch relaxation is enabled. 615</p> 616<p>Also no MIPS16 branches are ever relaxed. 617</p> 618<p>By default ‘<samp>--no-relax-branch</samp>’ is selected, causing any out-of-range 619branches to produce an error. 620</p> 621</dd> 622<dt><code>-mignore-branch-isa</code></dt> 623<dt><code>-mno-ignore-branch-isa</code></dt> 624<dd><p>Ignore branch checks for invalid transitions between ISA modes. 625</p> 626<p>The semantics of branches does not provide for an ISA mode switch, so in 627most cases the ISA mode a branch has been encoded for has to be the same 628as the ISA mode of the branch’s target label. If the ISA modes do not 629match, then such a branch, if taken, will cause the ISA mode to remain 630unchanged and instructions that follow will be executed in the wrong ISA 631mode causing the program to misbehave or crash. 632</p> 633<p>In the case of the <code>BAL</code> instruction it may be possible to relax 634it to an equivalent <code>JALX</code> instruction so that the ISA mode is 635switched at the run time as required. For other branches no relaxation 636is possible and therefore GAS has checks implemented that verify in 637branch assembly that the two ISA modes match, and report an error 638otherwise so that the problem with code can be diagnosed at the assembly 639time rather than at the run time. 640</p> 641<p>However some assembly code, including generated code produced by some 642versions of GCC, may incorrectly include branches to data labels, which 643appear to require a mode switch but are either dead or immediately 644followed by valid instructions encoded for the same ISA the branch has 645been encoded for. While not strictly correct at the source level such 646code will execute as intended, so to help with these cases 647‘<samp>-mignore-branch-isa</samp>’ is supported which disables ISA mode checks 648for branches. 649</p> 650<p>By default ‘<samp>-mno-ignore-branch-isa</samp>’ is selected, causing any invalid 651branch requiring a transition between ISA modes to produce an error. 652</p> 653<a name="index-_002dmnan_003d-command_002dline-option_002c-MIPS"></a> 654</dd> 655<dt><code>-mnan=<var>encoding</var></code></dt> 656<dd><p>This option indicates whether the source code uses the IEEE 2008 657NaN encoding (<samp>-mnan=2008</samp>) or the original MIPS encoding 658(<samp>-mnan=legacy</samp>). It is equivalent to adding a <code>.nan</code> 659directive to the beginning of the source file. See <a href="MIPS-NaN-Encodings.html#MIPS-NaN-Encodings">MIPS NaN Encodings</a>. 660</p> 661<p><samp>-mnan=legacy</samp> is the default if no <samp>-mnan</samp> option or 662<code>.nan</code> directive is used. 663</p> 664</dd> 665<dt><code>--trap</code></dt> 666<dt><code>--no-break</code></dt> 667<dd><p><code>as</code> automatically macro expands certain division and 668multiplication instructions to check for overflow and division by zero. This 669option causes <code>as</code> to generate code to take a trap exception 670rather than a break exception when an error is detected. The trap instructions 671are only supported at Instruction Set Architecture level 2 and higher. 672</p> 673</dd> 674<dt><code>--break</code></dt> 675<dt><code>--no-trap</code></dt> 676<dd><p>Generate code to take a break exception rather than a trap exception when an 677error is detected. This is the default. 678</p> 679</dd> 680<dt><code>-mpdr</code></dt> 681<dt><code>-mno-pdr</code></dt> 682<dd><p>Control generation of <code>.pdr</code> sections. Off by default on IRIX, on 683elsewhere. 684</p> 685</dd> 686<dt><code>-mshared</code></dt> 687<dt><code>-mno-shared</code></dt> 688<dd><p>When generating code using the Unix calling conventions (selected by 689‘<samp>-KPIC</samp>’ or ‘<samp>-mcall_shared</samp>’), gas will normally generate code 690which can go into a shared library. The ‘<samp>-mno-shared</samp>’ option 691tells gas to generate code which uses the calling convention, but can 692not go into a shared library. The resulting code is slightly more 693efficient. This option only affects the handling of the 694‘<samp>.cpload</samp>’ and ‘<samp>.cpsetup</samp>’ pseudo-ops. 695</p></dd> 696</dl> 697 698<hr> 699<div class="header"> 700<p> 701Next: <a href="MIPS-Macros.html#MIPS-Macros" accesskey="n" rel="next">MIPS Macros</a>, Up: <a href="MIPS_002dDependent.html#MIPS_002dDependent" accesskey="u" rel="up">MIPS-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p> 702</div> 703 704 705 706</body> 707</html> 708