1<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd"> 2<html> 3<!-- This file documents the GNU Assembler "as". 4 5Copyright (C) 1991-2021 Free Software Foundation, Inc. 6 7Permission is granted to copy, distribute and/or modify this document 8under the terms of the GNU Free Documentation License, Version 1.3 9or any later version published by the Free Software Foundation; 10with no Invariant Sections, with no Front-Cover Texts, and with no 11Back-Cover Texts. A copy of the license is included in the 12section entitled "GNU Free Documentation License". 13 --> 14<!-- Created by GNU Texinfo 5.1, http://www.gnu.org/software/texinfo/ --> 15<head> 16<title>Using as: AVR Opcodes</title> 17 18<meta name="description" content="Using as: AVR Opcodes"> 19<meta name="keywords" content="Using as: AVR Opcodes"> 20<meta name="resource-type" content="document"> 21<meta name="distribution" content="global"> 22<meta name="Generator" content="makeinfo"> 23<meta http-equiv="Content-Type" content="text/html; charset=utf-8"> 24<link href="index.html#Top" rel="start" title="Top"> 25<link href="AS-Index.html#AS-Index" rel="index" title="AS Index"> 26<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents"> 27<link href="AVR_002dDependent.html#AVR_002dDependent" rel="up" title="AVR-Dependent"> 28<link href="AVR-Pseudo-Instructions.html#AVR-Pseudo-Instructions" rel="next" title="AVR Pseudo Instructions"> 29<link href="AVR_002dModifiers.html#AVR_002dModifiers" rel="previous" title="AVR-Modifiers"> 30<style type="text/css"> 31<!-- 32a.summary-letter {text-decoration: none} 33blockquote.smallquotation {font-size: smaller} 34div.display {margin-left: 3.2em} 35div.example {margin-left: 3.2em} 36div.indentedblock {margin-left: 3.2em} 37div.lisp {margin-left: 3.2em} 38div.smalldisplay {margin-left: 3.2em} 39div.smallexample {margin-left: 3.2em} 40div.smallindentedblock {margin-left: 3.2em; font-size: smaller} 41div.smalllisp {margin-left: 3.2em} 42kbd {font-style:oblique} 43pre.display {font-family: inherit} 44pre.format {font-family: inherit} 45pre.menu-comment {font-family: serif} 46pre.menu-preformatted {font-family: serif} 47pre.smalldisplay {font-family: inherit; font-size: smaller} 48pre.smallexample {font-size: smaller} 49pre.smallformat {font-family: inherit; font-size: smaller} 50pre.smalllisp {font-size: smaller} 51span.nocodebreak {white-space:nowrap} 52span.nolinebreak {white-space:nowrap} 53span.roman {font-family:serif; font-weight:normal} 54span.sansserif {font-family:sans-serif; font-weight:normal} 55ul.no-bullet {list-style: none} 56--> 57</style> 58 59 60</head> 61 62<body lang="en" bgcolor="#FFFFFF" text="#000000" link="#0000FF" vlink="#800080" alink="#FF0000"> 63<a name="AVR-Opcodes"></a> 64<div class="header"> 65<p> 66Next: <a href="AVR-Pseudo-Instructions.html#AVR-Pseudo-Instructions" accesskey="n" rel="next">AVR Pseudo Instructions</a>, Previous: <a href="AVR-Syntax.html#AVR-Syntax" accesskey="p" rel="previous">AVR Syntax</a>, Up: <a href="AVR_002dDependent.html#AVR_002dDependent" accesskey="u" rel="up">AVR-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p> 67</div> 68<hr> 69<a name="Opcodes-4"></a> 70<h4 class="subsection">9.5.3 Opcodes</h4> 71 72<a name="index-AVR-opcode-summary"></a> 73<a name="index-opcode-summary_002c-AVR"></a> 74<a name="index-mnemonics_002c-AVR"></a> 75<a name="index-instruction-summary_002c-AVR"></a> 76<p>For detailed information on the AVR machine instruction set, see 77<a href="www.atmel.com/products/AVR">www.atmel.com/products/AVR</a>. 78</p> 79<p><code>as</code> implements all the standard AVR opcodes. 80The following table summarizes the AVR opcodes, and their arguments. 81</p> 82<div class="smallexample"> 83<pre class="smallexample"><i>Legend:</i> 84 r <span class="roman">any register</span> 85 d <span class="roman">‘ldi’ register (r16-r31)</span> 86 v <span class="roman">‘movw’ even register (r0, r2, ..., r28, r30)</span> 87 a <span class="roman">‘fmul’ register (r16-r23)</span> 88 w <span class="roman">‘adiw’ register (r24,r26,r28,r30)</span> 89 e <span class="roman">pointer registers (X,Y,Z)</span> 90 b <span class="roman">base pointer register and displacement ([YZ]+disp)</span> 91 z <span class="roman">Z pointer register (for [e]lpm Rd,Z[+])</span> 92 M <span class="roman">immediate value from 0 to 255</span> 93 n <span class="roman">immediate value from 0 to 255 ( n = ~M ). Relocation impossible</span> 94 s <span class="roman">immediate value from 0 to 7</span> 95 P <span class="roman">Port address value from 0 to 63. (in, out)</span> 96 p <span class="roman">Port address value from 0 to 31. (cbi, sbi, sbic, sbis)</span> 97 K <span class="roman">immediate value from 0 to 63 (used in ‘adiw’, ‘sbiw’)</span> 98 i <span class="roman">immediate value</span> 99 l <span class="roman">signed pc relative offset from -64 to 63</span> 100 L <span class="roman">signed pc relative offset from -2048 to 2047</span> 101 h <span class="roman">absolute code address (call, jmp)</span> 102 S <span class="roman">immediate value from 0 to 7 (S = s << 4)</span> 103 ? <span class="roman">use this opcode entry if no parameters, else use next opcode entry</span> 104 1051001010010001000 clc 1061001010011011000 clh 1071001010011111000 cli 1081001010010101000 cln 1091001010011001000 cls 1101001010011101000 clt 1111001010010111000 clv 1121001010010011000 clz 1131001010000001000 sec 1141001010001011000 seh 1151001010001111000 sei 1161001010000101000 sen 1171001010001001000 ses 1181001010001101000 set 1191001010000111000 sev 1201001010000011000 sez 121100101001SSS1000 bclr S 122100101000SSS1000 bset S 1231001010100001001 icall 1241001010000001001 ijmp 1251001010111001000 lpm ? 1261001000ddddd010+ lpm r,z 1271001010111011000 elpm ? 1281001000ddddd011+ elpm r,z 1290000000000000000 nop 1301001010100001000 ret 1311001010100011000 reti 1321001010110001000 sleep 1331001010110011000 break 1341001010110101000 wdr 1351001010111101000 spm 136000111rdddddrrrr adc r,r 137000011rdddddrrrr add r,r 138001000rdddddrrrr and r,r 139000101rdddddrrrr cp r,r 140000001rdddddrrrr cpc r,r 141000100rdddddrrrr cpse r,r 142001001rdddddrrrr eor r,r 143001011rdddddrrrr mov r,r 144100111rdddddrrrr mul r,r 145001010rdddddrrrr or r,r 146000010rdddddrrrr sbc r,r 147000110rdddddrrrr sub r,r 148001001rdddddrrrr clr r 149000011rdddddrrrr lsl r 150000111rdddddrrrr rol r 151001000rdddddrrrr tst r 1520111KKKKddddKKKK andi d,M 1530111KKKKddddKKKK cbr d,n 1541110KKKKddddKKKK ldi d,M 15511101111dddd1111 ser d 1560110KKKKddddKKKK ori d,M 1570110KKKKddddKKKK sbr d,M 1580011KKKKddddKKKK cpi d,M 1590100KKKKddddKKKK sbci d,M 1600101KKKKddddKKKK subi d,M 1611111110rrrrr0sss sbrc r,s 1621111111rrrrr0sss sbrs r,s 1631111100ddddd0sss bld r,s 1641111101ddddd0sss bst r,s 16510110PPdddddPPPP in r,P 16610111PPrrrrrPPPP out P,r 16710010110KKddKKKK adiw w,K 16810010111KKddKKKK sbiw w,K 16910011000pppppsss cbi p,s 17010011010pppppsss sbi p,s 17110011001pppppsss sbic p,s 17210011011pppppsss sbis p,s 173111101lllllll000 brcc l 174111100lllllll000 brcs l 175111100lllllll001 breq l 176111101lllllll100 brge l 177111101lllllll101 brhc l 178111100lllllll101 brhs l 179111101lllllll111 brid l 180111100lllllll111 brie l 181111100lllllll000 brlo l 182111100lllllll100 brlt l 183111100lllllll010 brmi l 184111101lllllll001 brne l 185111101lllllll010 brpl l 186111101lllllll000 brsh l 187111101lllllll110 brtc l 188111100lllllll110 brts l 189111101lllllll011 brvc l 190111100lllllll011 brvs l 191111101lllllllsss brbc s,l 192111100lllllllsss brbs s,l 1931101LLLLLLLLLLLL rcall L 1941100LLLLLLLLLLLL rjmp L 1951001010hhhhh111h call h 1961001010hhhhh110h jmp h 1971001010rrrrr0101 asr r 1981001010rrrrr0000 com r 1991001010rrrrr1010 dec r 2001001010rrrrr0011 inc r 2011001010rrrrr0110 lsr r 2021001010rrrrr0001 neg r 2031001000rrrrr1111 pop r 2041001001rrrrr1111 push r 2051001010rrrrr0111 ror r 2061001010rrrrr0010 swap r 20700000001ddddrrrr movw v,v 20800000010ddddrrrr muls d,d 209000000110ddd0rrr mulsu a,a 210000000110ddd1rrr fmul a,a 211000000111ddd0rrr fmuls a,a 212000000111ddd1rrr fmulsu a,a 2131001001ddddd0000 sts i,r 2141001000ddddd0000 lds r,i 21510o0oo0dddddbooo ldd r,b 216100!000dddddee-+ ld r,e 21710o0oo1rrrrrbooo std b,r 218100!001rrrrree-+ st e,r 2191001010100011001 eicall 2201001010000011001 eijmp 221</pre></div> 222 223<hr> 224<div class="header"> 225<p> 226Next: <a href="AVR-Pseudo-Instructions.html#AVR-Pseudo-Instructions" accesskey="n" rel="next">AVR Pseudo Instructions</a>, Previous: <a href="AVR-Syntax.html#AVR-Syntax" accesskey="p" rel="previous">AVR Syntax</a>, Up: <a href="AVR_002dDependent.html#AVR_002dDependent" accesskey="u" rel="up">AVR-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p> 227</div> 228 229 230 231</body> 232</html> 233