1<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd"> 2<html> 3<!-- This file documents the GNU Assembler "as". 4 5Copyright (C) 1991-2021 Free Software Foundation, Inc. 6 7Permission is granted to copy, distribute and/or modify this document 8under the terms of the GNU Free Documentation License, Version 1.3 9or any later version published by the Free Software Foundation; 10with no Invariant Sections, with no Front-Cover Texts, and with no 11Back-Cover Texts. A copy of the license is included in the 12section entitled "GNU Free Documentation License". 13 --> 14<!-- Created by GNU Texinfo 5.1, http://www.gnu.org/software/texinfo/ --> 15<head> 16<title>Using as: ARC Directives</title> 17 18<meta name="description" content="Using as: ARC Directives"> 19<meta name="keywords" content="Using as: ARC Directives"> 20<meta name="resource-type" content="document"> 21<meta name="distribution" content="global"> 22<meta name="Generator" content="makeinfo"> 23<meta http-equiv="Content-Type" content="text/html; charset=utf-8"> 24<link href="index.html#Top" rel="start" title="Top"> 25<link href="AS-Index.html#AS-Index" rel="index" title="AS Index"> 26<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents"> 27<link href="ARC_002dDependent.html#ARC_002dDependent" rel="up" title="ARC-Dependent"> 28<link href="ARC-Modifiers.html#ARC-Modifiers" rel="next" title="ARC Modifiers"> 29<link href="ARC_002dRegs.html#ARC_002dRegs" rel="previous" title="ARC-Regs"> 30<style type="text/css"> 31<!-- 32a.summary-letter {text-decoration: none} 33blockquote.smallquotation {font-size: smaller} 34div.display {margin-left: 3.2em} 35div.example {margin-left: 3.2em} 36div.indentedblock {margin-left: 3.2em} 37div.lisp {margin-left: 3.2em} 38div.smalldisplay {margin-left: 3.2em} 39div.smallexample {margin-left: 3.2em} 40div.smallindentedblock {margin-left: 3.2em; font-size: smaller} 41div.smalllisp {margin-left: 3.2em} 42kbd {font-style:oblique} 43pre.display {font-family: inherit} 44pre.format {font-family: inherit} 45pre.menu-comment {font-family: serif} 46pre.menu-preformatted {font-family: serif} 47pre.smalldisplay {font-family: inherit; font-size: smaller} 48pre.smallexample {font-size: smaller} 49pre.smallformat {font-family: inherit; font-size: smaller} 50pre.smalllisp {font-size: smaller} 51span.nocodebreak {white-space:nowrap} 52span.nolinebreak {white-space:nowrap} 53span.roman {font-family:serif; font-weight:normal} 54span.sansserif {font-family:sans-serif; font-weight:normal} 55ul.no-bullet {list-style: none} 56--> 57</style> 58 59 60</head> 61 62<body lang="en" bgcolor="#FFFFFF" text="#000000" link="#0000FF" vlink="#800080" alink="#FF0000"> 63<a name="ARC-Directives"></a> 64<div class="header"> 65<p> 66Next: <a href="ARC-Modifiers.html#ARC-Modifiers" accesskey="n" rel="next">ARC Modifiers</a>, Previous: <a href="ARC-Syntax.html#ARC-Syntax" accesskey="p" rel="previous">ARC Syntax</a>, Up: <a href="ARC_002dDependent.html#ARC_002dDependent" accesskey="u" rel="up">ARC-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p> 67</div> 68<hr> 69<a name="ARC-Machine-Directives"></a> 70<h4 class="subsection">9.3.3 ARC Machine Directives</h4> 71 72<a name="index-machine-directives_002c-ARC"></a> 73<a name="index-ARC-machine-directives"></a> 74<p>The ARC version of <code>as</code> supports the following additional 75machine directives: 76</p> 77<dl compact="compact"> 78<dd> 79<a name="index-lcomm-directive-1"></a> 80</dd> 81<dt><code>.lcomm <var>symbol</var>, <var>length</var>[, <var>alignment</var>]</code></dt> 82<dd><p>Reserve <var>length</var> (an absolute expression) bytes for a local common 83denoted by <var>symbol</var>. The section and value of <var>symbol</var> are 84those of the new local common. The addresses are allocated in the bss 85section, so that at run-time the bytes start off zeroed. Since 86<var>symbol</var> is not declared global, it is normally not visible to 87<code>ld</code>. The optional third parameter, <var>alignment</var>, 88specifies the desired alignment of the symbol in the bss section, 89specified as a byte boundary (for example, an alignment of 16 means 90that the least significant 4 bits of the address should be zero). The 91alignment must be an absolute expression, and it must be a power of 92two. If no alignment is specified, as will set the alignment to the 93largest power of two less than or equal to the size of the symbol, up 94to a maximum of 16. 95</p> 96<a name="index-lcommon-directive_002c-ARC"></a> 97</dd> 98<dt><code>.lcommon <var>symbol</var>, <var>length</var>[, <var>alignment</var>]</code></dt> 99<dd><p>The same as <code>lcomm</code> directive. 100</p> 101<a name="index-cpu-directive_002c-ARC"></a> 102</dd> 103<dt><code>.cpu <var>cpu</var></code></dt> 104<dd><p>The <code>.cpu</code> directive must be followed by the desired core 105version. Permitted values for CPU are: 106</p><dl compact="compact"> 107<dt><code>ARC600</code></dt> 108<dd><p>Assemble for the ARC600 instruction set. 109</p> 110</dd> 111<dt><code>arc600_norm</code></dt> 112<dd><p>Assemble for ARC 600 with norm instructions. 113</p> 114</dd> 115<dt><code>arc600_mul64</code></dt> 116<dd><p>Assemble for ARC 600 with mul64 instructions. 117</p> 118</dd> 119<dt><code>arc600_mul32x16</code></dt> 120<dd><p>Assemble for ARC 600 with mul32x16 instructions. 121</p> 122</dd> 123<dt><code>arc601</code></dt> 124<dd><p>Assemble for ARC 601 instruction set. 125</p> 126</dd> 127<dt><code>arc601_norm</code></dt> 128<dd><p>Assemble for ARC 601 with norm instructions. 129</p> 130</dd> 131<dt><code>arc601_mul64</code></dt> 132<dd><p>Assemble for ARC 601 with mul64 instructions. 133</p> 134</dd> 135<dt><code>arc601_mul32x16</code></dt> 136<dd><p>Assemble for ARC 601 with mul32x16 instructions. 137</p> 138</dd> 139<dt><code>ARC700</code></dt> 140<dd><p>Assemble for the ARC700 instruction set. 141</p> 142</dd> 143<dt><code>NPS400</code></dt> 144<dd><p>Assemble for the NPS400 instruction set. 145</p> 146</dd> 147<dt><code>EM</code></dt> 148<dd><p>Assemble for the ARC EM instruction set. 149</p> 150</dd> 151<dt><code>arcem</code></dt> 152<dd><p>Assemble for ARC EM instruction set 153</p> 154</dd> 155<dt><code>em4</code></dt> 156<dd><p>Assemble for ARC EM with code-density instructions. 157</p> 158</dd> 159<dt><code>em4_dmips</code></dt> 160<dd><p>Assemble for ARC EM with code-density instructions. 161</p> 162</dd> 163<dt><code>em4_fpus</code></dt> 164<dd><p>Assemble for ARC EM with code-density instructions. 165</p> 166</dd> 167<dt><code>em4_fpuda</code></dt> 168<dd><p>Assemble for ARC EM with code-density, and double-precision assist 169instructions. 170</p> 171</dd> 172<dt><code>quarkse_em</code></dt> 173<dd><p>Assemble for QuarkSE-EM instruction set. 174</p> 175</dd> 176<dt><code>HS</code></dt> 177<dd><p>Assemble for the ARC HS instruction set. 178</p> 179</dd> 180<dt><code>archs</code></dt> 181<dd><p>Assemble for ARC HS instruction set. 182</p> 183</dd> 184<dt><code>hs</code></dt> 185<dd><p>Assemble for ARC HS instruction set. 186</p> 187</dd> 188<dt><code>hs34</code></dt> 189<dd><p>Assemble for ARC HS34 instruction set. 190</p> 191</dd> 192<dt><code>hs38</code></dt> 193<dd><p>Assemble for ARC HS38 instruction set. 194</p> 195</dd> 196<dt><code>hs38_linux</code></dt> 197<dd><p>Assemble for ARC HS38 with floating point support on. 198</p> 199</dd> 200</dl> 201 202<p>Note: the <code>.cpu</code> directive overrides the command-line option 203<code>-mcpu=<var>cpu</var></code>; a warning is emitted when the version is not 204consistent between the two. 205</p> 206</dd> 207<dt><code>.extAuxRegister <var>name</var>, <var>addr</var>, <var>mode</var></code></dt> 208<dd><a name="index-extAuxRegister-directive_002c-ARC"></a> 209<p>Auxiliary registers can be defined in the assembler source code by 210using this directive. The first parameter, <var>name</var>, is the name of the 211new auxiliary register. The second parameter, <var>addr</var>, is 212address the of the auxiliary register. The third parameter, 213<var>mode</var>, specifies whether the register is readable and/or writable 214and is one of: 215</p><dl compact="compact"> 216<dt><code>r</code></dt> 217<dd><p>Read only; 218</p> 219</dd> 220<dt><code>w</code></dt> 221<dd><p>Write only; 222</p> 223</dd> 224<dt><code>r|w</code></dt> 225<dd><p>Read and write. 226</p> 227</dd> 228</dl> 229 230<p>For example: 231</p><div class="example"> 232<pre class="example"> .extAuxRegister mulhi, 0x12, w 233</pre></div> 234<p>specifies a write only extension auxiliary register, <var>mulhi</var> at 235address 0x12. 236</p> 237</dd> 238<dt><code>.extCondCode <var>suffix</var>, <var>val</var></code></dt> 239<dd><a name="index-extCondCode-directive_002c-ARC"></a> 240<p>ARC supports extensible condition codes. This directive defines a new 241condition code, to be known by the suffix, <var>suffix</var> and will 242depend on the value, <var>val</var> in the condition code. 243</p> 244<p>For example: 245</p><div class="example"> 246<pre class="example"> .extCondCode is_busy,0x14 247 add.is_busy r1,r2,r3 248</pre></div> 249<p>will only execute the <code>add</code> instruction if the condition code 250value is 0x14. 251</p> 252</dd> 253<dt><code>.extCoreRegister <var>name</var>, <var>regnum</var>, <var>mode</var>, <var>shortcut</var></code></dt> 254<dd><a name="index-extCoreRegister-directive_002c-ARC"></a> 255<p>Specifies an extension core register named <var>name</var> as a synonym for 256the register numbered <var>regnum</var>. The register number must be 257between 32 and 59. The third argument, <var>mode</var>, indicates whether 258the register is readable and/or writable and is one of: 259</p><dl compact="compact"> 260<dt><code>r</code></dt> 261<dd><p>Read only; 262</p> 263</dd> 264<dt><code>w</code></dt> 265<dd><p>Write only; 266</p> 267</dd> 268<dt><code>r|w</code></dt> 269<dd><p>Read and write. 270</p> 271</dd> 272</dl> 273 274<p>The final parameter, <var>shortcut</var> indicates whether the register has 275a short cut in the pipeline. The valid values are: 276</p><dl compact="compact"> 277<dt><code>can_shortcut</code></dt> 278<dd><p>The register has a short cut in the pipeline; 279</p> 280</dd> 281<dt><code>cannot_shortcut</code></dt> 282<dd><p>The register does not have a short cut in the pipeline. 283</p></dd> 284</dl> 285 286<p>For example: 287</p><div class="example"> 288<pre class="example"> .extCoreRegister mlo, 57, r , can_shortcut 289</pre></div> 290<p>defines a read only extension core register, <code>mlo</code>, which is 291register 57, and can short cut the pipeline. 292</p> 293</dd> 294<dt><code>.extInstruction <var>name</var>, <var>opcode</var>, <var>subopcode</var>, <var>suffixclass</var>, <var>syntaxclass</var></code></dt> 295<dd><a name="index-extInstruction-directive_002c-ARC"></a> 296<p>ARC allows the user to specify extension instructions. These 297extension instructions are not macros; the assembler creates encodings 298for use of these instructions according to the specification by the 299user. 300</p> 301<p>The first argument, <var>name</var>, gives the name of the instruction. 302</p> 303<p>The second argument, <var>opcode</var>, is the opcode to be used (bits 31:27 304in the encoding). 305</p> 306<p>The third argument, <var>subopcode</var>, is the sub-opcode to be used, but 307the correct value also depends on the fifth argument, 308<var>syntaxclass</var> 309</p> 310<p>The fourth argument, <var>suffixclass</var>, determines the kinds of 311suffixes to be allowed. Valid values are: 312</p><dl compact="compact"> 313<dt><code>SUFFIX_NONE</code></dt> 314<dd><p>No suffixes are permitted; 315</p> 316</dd> 317<dt><code>SUFFIX_COND</code></dt> 318<dd><p>Conditional suffixes are permitted; 319</p> 320</dd> 321<dt><code>SUFFIX_FLAG</code></dt> 322<dd><p>Flag setting suffixes are permitted. 323</p> 324</dd> 325<dt><code>SUFFIX_COND|SUFFIX_FLAG</code></dt> 326<dd><p>Both conditional and flag setting suffices are permitted. 327</p> 328</dd> 329</dl> 330 331<p>The fifth and final argument, <var>syntaxclass</var>, determines the syntax 332class for the instruction. It can have the following values: 333</p><dl compact="compact"> 334<dt><code>SYNTAX_2OP</code></dt> 335<dd><p>Two Operand Instruction; 336</p> 337</dd> 338<dt><code>SYNTAX_3OP</code></dt> 339<dd><p>Three Operand Instruction. 340</p> 341</dd> 342<dt><code>SYNTAX_1OP</code></dt> 343<dd><p>One Operand Instruction. 344</p> 345</dd> 346<dt><code>SYNTAX_NOP</code></dt> 347<dd><p>No Operand Instruction. 348</p></dd> 349</dl> 350 351<p>The syntax class may be followed by ‘<samp>|</samp>’ and one of the following 352modifiers. 353</p><dl compact="compact"> 354<dt><code>OP1_MUST_BE_IMM</code></dt> 355<dd><p>Modifies syntax class <code>SYNTAX_3OP</code>, specifying that the first 356operand of a three-operand instruction must be an immediate (i.e., the 357result is discarded). This is usually used to set the flags using 358specific instructions and not retain results. 359</p> 360</dd> 361<dt><code>OP1_IMM_IMPLIED</code></dt> 362<dd><p>Modifies syntax class <code>SYNTAX_20P</code>, specifying that there is an 363implied immediate destination operand which does not appear in the 364syntax. 365</p> 366<p>For example, if the source code contains an instruction like: 367</p><div class="example"> 368<pre class="example">inst r1,r2 369</pre></div> 370<p>the first argument is an implied immediate (that is, the result is 371discarded). This is the same as though the source code were: inst 3720,r1,r2. 373</p> 374</dd> 375</dl> 376 377<p>For example, defining a 64-bit multiplier with immediate operands: 378</p><div class="example"> 379<pre class="example"> .extInstruction mp64, 0x07, 0x2d, SUFFIX_COND|SUFFIX_FLAG, 380 SYNTAX_3OP|OP1_MUST_BE_IMM 381</pre></div> 382<p>which specifies an extension instruction named <code>mp64</code> with 3 383operands. It sets the flags and can be used with a condition code, 384for which the first operand is an immediate, i.e. equivalent to 385discarding the result of the operation. 386</p> 387<p>A two operands instruction variant would be: 388</p><div class="example"> 389<pre class="example"> .extInstruction mul64, 0x07, 0x2d, SUFFIX_COND, 390 SYNTAX_2OP|OP1_IMM_IMPLIED 391</pre></div> 392<p>which describes a two operand instruction with an implicit first 393immediate operand. The result of this operation would be discarded. 394</p> 395<a name="index-_002earc_005fattribute-directive_002c-ARC"></a> 396</dd> 397<dt><code>.arc_attribute <var>tag</var>, <var>value</var></code></dt> 398<dd><p>Set the ARC object attribute <var>tag</var> to <var>value</var>. 399</p> 400<p>The <var>tag</var> is either an attribute number, or one of the following: 401<code>Tag_ARC_PCS_config</code>, <code>Tag_ARC_CPU_base</code>, 402<code>Tag_ARC_CPU_variation</code>, <code>Tag_ARC_CPU_name</code>, 403<code>Tag_ARC_ABI_rf16</code>, <code>Tag_ARC_ABI_osver</code>, <code>Tag_ARC_ABI_sda</code>, 404<code>Tag_ARC_ABI_pic</code>, <code>Tag_ARC_ABI_tls</code>, <code>Tag_ARC_ABI_enumsize</code>, 405<code>Tag_ARC_ABI_exceptions</code>, <code>Tag_ARC_ABI_double_size</code>, 406<code>Tag_ARC_ISA_config</code>, <code>Tag_ARC_ISA_apex</code>, 407<code>Tag_ARC_ISA_mpy_option</code> 408</p> 409<p>The <var>value</var> is either a <code>number</code>, <code>"string"</code>, or 410<code>number, "string"</code> depending on the tag. 411</p> 412</dd> 413</dl> 414 415<hr> 416<div class="header"> 417<p> 418Next: <a href="ARC-Modifiers.html#ARC-Modifiers" accesskey="n" rel="next">ARC Modifiers</a>, Previous: <a href="ARC-Syntax.html#ARC-Syntax" accesskey="p" rel="previous">ARC Syntax</a>, Up: <a href="ARC_002dDependent.html#ARC_002dDependent" accesskey="u" rel="up">ARC-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p> 419</div> 420 421 422 423</body> 424</html> 425