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16<title>Using as: AArch64 Opcodes</title>
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66Next: <a href="AArch64-Mapping-Symbols.html#AArch64-Mapping-Symbols" accesskey="n" rel="next">AArch64 Mapping Symbols</a>, Previous: <a href="AArch64-Directives.html#AArch64-Directives" accesskey="p" rel="previous">AArch64 Directives</a>, Up: <a href="AArch64_002dDependent.html#AArch64_002dDependent" accesskey="u" rel="up">AArch64-Dependent</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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69<a name="Opcodes"></a>
70<h4 class="subsection">9.1.6 Opcodes</h4>
71
72<a name="index-AArch64-opcodes"></a>
73<a name="index-opcodes-for-AArch64"></a>
74<p>GAS implements all the standard AArch64 opcodes.  It also
75implements several pseudo opcodes, including several synthetic load
76instructions.
77</p>
78<dl compact="compact">
79<dd>
80<a name="index-LDR-reg_002c_003d_003cexpr_003e-pseudo-op_002c-AArch64"></a>
81</dd>
82<dt><code>LDR =</code></dt>
83<dd><div class="smallexample">
84<pre class="smallexample">  ldr &lt;register&gt; , =&lt;expression&gt;
85</pre></div>
86
87<p>The constant expression will be placed into the nearest literal pool (if it not
88already there) and a PC-relative LDR instruction will be generated.
89</p>
90</dd>
91</dl>
92
93<p>For more information on the AArch64 instruction set and assembly language
94notation, see &lsquo;<samp>ARMv8 Instruction Set Overview</samp>&rsquo; available at
95<a href="http://infocenter.arm.com">http://infocenter.arm.com</a>.
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