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63<a name="MIPS-FP-ABI-Variants"></a>
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65<p>
66Next: <a href="MIPS-FP-ABI-Selection.html#MIPS-FP-ABI-Selection" accesskey="n" rel="next">MIPS FP ABI Selection</a>, Previous: <a href="MIPS-FP-ABI-History.html#MIPS-FP-ABI-History" accesskey="p" rel="previous">MIPS FP ABI History</a>, Up: <a href="MIPS-FP-ABIs.html#MIPS-FP-ABIs" accesskey="u" rel="up">MIPS FP ABIs</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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69<a name="Supported-FP-ABIs"></a>
70<h4 class="subsubsection">9.27.9.2 Supported FP ABIs</h4>
71<p>The supported floating-point ABI variants are:
72</p>
73<dl compact="compact">
74<dt><code>0 - No floating-point</code></dt>
75<dd><p>This variant is used to indicate that floating-point is not used within
76the module at all and therefore has no impact on the ABI.  This is the
77default.
78</p>
79</dd>
80<dt><code>1 - Double-precision</code></dt>
81<dd><p>This variant indicates that double-precision support is used.  For 64-bit
82ABIs this means that 64-bit wide floating-point registers are required.
83For 32-bit ABIs this means that 32-bit wide floating-point registers are
84required and double-precision operations use pairs of registers.
85</p>
86</dd>
87<dt><code>2 - Single-precision</code></dt>
88<dd><p>This variant indicates that single-precision support is used.  Double
89precision operations will be supported via soft-float routines.
90</p>
91</dd>
92<dt><code>3 - Soft-float</code></dt>
93<dd><p>This variant indicates that although floating-point support is used all
94operations are emulated in software.  This means the ABI is modified to
95pass all floating-point data in general-purpose registers.
96</p>
97</dd>
98<dt><code>4 - Deprecated</code></dt>
99<dd><p>This variant existed as an initial attempt at supporting 64-bit wide
100floating-point registers for O32 ABI on a MIPS32r2 CPU.  This has been
101superseded by 5, 6 and 7.
102</p>
103</dd>
104<dt><code>5 - Double-precision 32-bit CPU, 32-bit or 64-bit FPU</code></dt>
105<dd><p>This variant is used by 32-bit ABIs to indicate that the floating-point
106code in the module has been designed to operate correctly with either
10732-bit wide or 64-bit wide floating-point registers.  Double-precision
108support is used.  Only O32 currently supports this variant and requires
109a minimum architecture of MIPS II.
110</p>
111</dd>
112<dt><code>6 - Double-precision 32-bit FPU, 64-bit FPU</code></dt>
113<dd><p>This variant is used by 32-bit ABIs to indicate that the floating-point
114code in the module requires 64-bit wide floating-point registers.
115Double-precision support is used.  Only O32 currently supports this
116variant and requires a minimum architecture of MIPS32r2.
117</p>
118</dd>
119<dt><code>7 - Double-precision compat 32-bit FPU, 64-bit FPU</code></dt>
120<dd><p>This variant is used by 32-bit ABIs to indicate that the floating-point
121code in the module requires 64-bit wide floating-point registers.
122Double-precision support is used.  This differs from the previous ABI
123as it restricts use of odd-numbered single-precision registers.  Only
124O32 currently supports this variant and requires a minimum architecture
125of MIPS32r2.
126</p></dd>
127</dl>
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132Next: <a href="MIPS-FP-ABI-Selection.html#MIPS-FP-ABI-Selection" accesskey="n" rel="next">MIPS FP ABI Selection</a>, Previous: <a href="MIPS-FP-ABI-History.html#MIPS-FP-ABI-History" accesskey="p" rel="previous">MIPS FP ABI History</a>, Up: <a href="MIPS-FP-ABIs.html#MIPS-FP-ABIs" accesskey="u" rel="up">MIPS FP ABIs</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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