1 // SPDX-License-Identifier: GPL-2.0-only
2 /* sound/soc/rockchip/rk_spdif.c
3 *
4 * ALSA SoC Audio Layer - Rockchip I2S Controller driver
5 *
6 * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
7 * Author: Jianqun <jay.xu@rock-chips.com>
8 * Copyright (c) 2015 Collabora Ltd.
9 * Author: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
10 */
11
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/of_gpio.h>
15 #include <linux/clk.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/mfd/syscon.h>
18 #include <linux/regmap.h>
19 #include <sound/pcm_params.h>
20 #include <sound/pcm_iec958.h>
21 #include <sound/dmaengine_pcm.h>
22
23 #include "rockchip_spdif.h"
24
25 enum rk_spdif_type {
26 RK_SPDIF_RK3066,
27 RK_SPDIF_RK3188,
28 RK_SPDIF_RK3288,
29 RK_SPDIF_RK3366,
30 };
31
32 /*
33 * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
34 * CS0: | Mode | d | c | b | a |
35 * CS1: | Category Code |
36 * CS2: | Channel Number | Source Number |
37 * CS3: | Clock Accuracy | Sample Freq |
38 * CS4: | Ori Sample Freq | Word Length |
39 * CS5: | | CGMS-A |
40 * CS6~CS23: Reserved
41 *
42 * a: use of channel status block
43 * b: linear PCM identification: 0 for lpcm, 1 for nlpcm
44 * c: copyright information
45 * d: additional format information
46 */
47 #define CS_BYTE 6
48 #define CS_FRAME(c) ((c) << 16 | (c))
49
50 #define RK3288_GRF_SOC_CON2 0x24c
51
52 struct rk_spdif_dev {
53 struct device *dev;
54
55 struct clk *mclk;
56 struct clk *hclk;
57
58 struct snd_dmaengine_dai_dma_data playback_dma_data;
59
60 struct regmap *regmap;
61 };
62
63 static const struct of_device_id rk_spdif_match[] __maybe_unused = {
64 { .compatible = "rockchip,rk3066-spdif",
65 .data = (void *)RK_SPDIF_RK3066 },
66 { .compatible = "rockchip,rk3188-spdif",
67 .data = (void *)RK_SPDIF_RK3188 },
68 { .compatible = "rockchip,rk3228-spdif",
69 .data = (void *)RK_SPDIF_RK3366 },
70 { .compatible = "rockchip,rk3288-spdif",
71 .data = (void *)RK_SPDIF_RK3288 },
72 { .compatible = "rockchip,rk3328-spdif",
73 .data = (void *)RK_SPDIF_RK3366 },
74 { .compatible = "rockchip,rk3366-spdif",
75 .data = (void *)RK_SPDIF_RK3366 },
76 { .compatible = "rockchip,rk3368-spdif",
77 .data = (void *)RK_SPDIF_RK3366 },
78 { .compatible = "rockchip,rk3399-spdif",
79 .data = (void *)RK_SPDIF_RK3366 },
80 { .compatible = "rockchip,rk3568-spdif",
81 .data = (void *)RK_SPDIF_RK3366 },
82 { .compatible = "rockchip,rk3588-spdif",
83 .data = (void *)RK_SPDIF_RK3366 },
84 {},
85 };
86 MODULE_DEVICE_TABLE(of, rk_spdif_match);
87
rk_spdif_runtime_suspend(struct device * dev)88 static int __maybe_unused rk_spdif_runtime_suspend(struct device *dev)
89 {
90 struct rk_spdif_dev *spdif = dev_get_drvdata(dev);
91
92 regcache_cache_only(spdif->regmap, true);
93 clk_disable_unprepare(spdif->mclk);
94 clk_disable_unprepare(spdif->hclk);
95
96 return 0;
97 }
98
rk_spdif_runtime_resume(struct device * dev)99 static int __maybe_unused rk_spdif_runtime_resume(struct device *dev)
100 {
101 struct rk_spdif_dev *spdif = dev_get_drvdata(dev);
102 int ret;
103
104 ret = clk_prepare_enable(spdif->mclk);
105 if (ret) {
106 dev_err(spdif->dev, "mclk clock enable failed %d\n", ret);
107 return ret;
108 }
109
110 ret = clk_prepare_enable(spdif->hclk);
111 if (ret) {
112 dev_err(spdif->dev, "hclk clock enable failed %d\n", ret);
113 return ret;
114 }
115
116 regcache_cache_only(spdif->regmap, false);
117 regcache_mark_dirty(spdif->regmap);
118
119 ret = regcache_sync(spdif->regmap);
120 if (ret) {
121 clk_disable_unprepare(spdif->mclk);
122 clk_disable_unprepare(spdif->hclk);
123 }
124
125 return ret;
126 }
127
rk_spdif_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)128 static int rk_spdif_hw_params(struct snd_pcm_substream *substream,
129 struct snd_pcm_hw_params *params,
130 struct snd_soc_dai *dai)
131 {
132 struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
133 unsigned int val = SPDIF_CFGR_HALFWORD_ENABLE;
134 unsigned int mclk_rate = clk_get_rate(spdif->mclk);
135 int bmc, div, ret, i;
136 u8 cs[CS_BYTE];
137 u16 *fc = (u16 *)cs;
138
139 ret = snd_pcm_create_iec958_consumer_hw_params(params, cs, sizeof(cs));
140 if (ret < 0)
141 return ret;
142
143 for (i = 0; i < CS_BYTE / 2; i++)
144 regmap_write(spdif->regmap, SPDIF_CHNSRn(i), CS_FRAME(fc[i]));
145
146 regmap_update_bits(spdif->regmap, SPDIF_CFGR, SPDIF_CFGR_CSE_MASK,
147 SPDIF_CFGR_CSE_EN);
148
149 /* bmc = 128fs */
150 bmc = 128 * params_rate(params);
151 div = DIV_ROUND_CLOSEST(mclk_rate, bmc);
152 val |= SPDIF_CFGR_CLK_DIV(div);
153
154 switch (params_format(params)) {
155 case SNDRV_PCM_FORMAT_S16_LE:
156 val |= SPDIF_CFGR_VDW_16;
157 break;
158 case SNDRV_PCM_FORMAT_S20_3LE:
159 val |= SPDIF_CFGR_VDW_20;
160 break;
161 case SNDRV_PCM_FORMAT_S24_LE:
162 val |= SPDIF_CFGR_VDW_24;
163 val |= SPDIF_CFGR_ADJ_RIGHT_J;
164 break;
165 case SNDRV_PCM_FORMAT_S32_LE:
166 val |= SPDIF_CFGR_VDW_24;
167 val |= SPDIF_CFGR_ADJ_LEFT_J;
168 break;
169 default:
170 return -EINVAL;
171 }
172
173 regmap_update_bits(spdif->regmap, SPDIF_CFGR, SPDIF_CFGR_CLR_MASK,
174 SPDIF_CFGR_CLR_EN);
175
176 udelay(1);
177 ret = regmap_update_bits(spdif->regmap, SPDIF_CFGR,
178 SPDIF_CFGR_CLK_DIV_MASK |
179 SPDIF_CFGR_HALFWORD_ENABLE |
180 SDPIF_CFGR_VDW_MASK |
181 SPDIF_CFGR_ADJ_MASK, val);
182
183 return ret;
184 }
185
rk_spdif_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)186 static int rk_spdif_trigger(struct snd_pcm_substream *substream,
187 int cmd, struct snd_soc_dai *dai)
188 {
189 struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
190 int ret;
191
192 switch (cmd) {
193 case SNDRV_PCM_TRIGGER_START:
194 case SNDRV_PCM_TRIGGER_RESUME:
195 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
196 ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,
197 SPDIF_DMACR_TDE_ENABLE |
198 SPDIF_DMACR_TDL_MASK,
199 SPDIF_DMACR_TDE_ENABLE |
200 SPDIF_DMACR_TDL(16));
201
202 if (ret != 0)
203 return ret;
204
205 ret = regmap_update_bits(spdif->regmap, SPDIF_XFER,
206 SPDIF_XFER_TXS_START,
207 SPDIF_XFER_TXS_START);
208 break;
209 case SNDRV_PCM_TRIGGER_SUSPEND:
210 case SNDRV_PCM_TRIGGER_STOP:
211 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
212 ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,
213 SPDIF_DMACR_TDE_ENABLE,
214 SPDIF_DMACR_TDE_DISABLE);
215
216 if (ret != 0)
217 return ret;
218
219 ret = regmap_update_bits(spdif->regmap, SPDIF_XFER,
220 SPDIF_XFER_TXS_START,
221 SPDIF_XFER_TXS_STOP);
222 break;
223 default:
224 ret = -EINVAL;
225 break;
226 }
227
228 return ret;
229 }
230
rk_spdif_dai_probe(struct snd_soc_dai * dai)231 static int rk_spdif_dai_probe(struct snd_soc_dai *dai)
232 {
233 struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
234
235 dai->playback_dma_data = &spdif->playback_dma_data;
236
237 return 0;
238 }
239
rk_spdif_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)240 static int rk_spdif_set_sysclk(struct snd_soc_dai *dai,
241 int clk_id, unsigned int freq, int dir)
242 {
243 struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
244 int ret = 0;
245
246 if (!freq)
247 return 0;
248
249 ret = clk_set_rate(spdif->mclk, freq);
250 if (ret)
251 dev_err(spdif->dev, "Failed to set mclk: %d\n", ret);
252
253 return ret;
254 }
255
256 static const struct snd_soc_dai_ops rk_spdif_dai_ops = {
257 .set_sysclk = rk_spdif_set_sysclk,
258 .hw_params = rk_spdif_hw_params,
259 .trigger = rk_spdif_trigger,
260 };
261
262 static struct snd_soc_dai_driver rk_spdif_dai = {
263 .probe = rk_spdif_dai_probe,
264 .playback = {
265 .stream_name = "Playback",
266 .channels_min = 2,
267 .channels_max = 2,
268 .rates = SNDRV_PCM_RATE_8000_192000,
269 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
270 SNDRV_PCM_FMTBIT_S20_3LE |
271 SNDRV_PCM_FMTBIT_S24_LE |
272 SNDRV_PCM_FMTBIT_S32_LE),
273 },
274 .ops = &rk_spdif_dai_ops,
275 };
276
277 static const struct snd_soc_component_driver rk_spdif_component = {
278 .name = "rockchip-spdif",
279 };
280
rk_spdif_wr_reg(struct device * dev,unsigned int reg)281 static bool rk_spdif_wr_reg(struct device *dev, unsigned int reg)
282 {
283 switch (reg) {
284 case SPDIF_CFGR:
285 case SPDIF_DMACR:
286 case SPDIF_INTCR:
287 case SPDIF_XFER:
288 case SPDIF_SMPDR:
289 case SPDIF_VLDFRn(0) ... SPDIF_VLDFRn(11):
290 case SPDIF_USRDRn(0) ... SPDIF_USRDRn(11):
291 case SPDIF_CHNSRn(0) ... SPDIF_CHNSRn(11):
292 return true;
293 default:
294 return false;
295 }
296 }
297
rk_spdif_rd_reg(struct device * dev,unsigned int reg)298 static bool rk_spdif_rd_reg(struct device *dev, unsigned int reg)
299 {
300 switch (reg) {
301 case SPDIF_CFGR:
302 case SPDIF_SDBLR:
303 case SPDIF_INTCR:
304 case SPDIF_INTSR:
305 case SPDIF_XFER:
306 case SPDIF_SMPDR:
307 case SPDIF_VLDFRn(0) ... SPDIF_VLDFRn(11):
308 case SPDIF_USRDRn(0) ... SPDIF_USRDRn(11):
309 case SPDIF_CHNSRn(0) ... SPDIF_CHNSRn(11):
310 return true;
311 default:
312 return false;
313 }
314 }
315
rk_spdif_volatile_reg(struct device * dev,unsigned int reg)316 static bool rk_spdif_volatile_reg(struct device *dev, unsigned int reg)
317 {
318 switch (reg) {
319 case SPDIF_INTSR:
320 case SPDIF_SDBLR:
321 case SPDIF_SMPDR:
322 return true;
323 default:
324 return false;
325 }
326 }
327
328 static const struct regmap_config rk_spdif_regmap_config = {
329 .reg_bits = 32,
330 .reg_stride = 4,
331 .val_bits = 32,
332 .max_register = SPDIF_VERSION,
333 .writeable_reg = rk_spdif_wr_reg,
334 .readable_reg = rk_spdif_rd_reg,
335 .volatile_reg = rk_spdif_volatile_reg,
336 .cache_type = REGCACHE_FLAT,
337 };
338
rk_spdif_probe(struct platform_device * pdev)339 static int rk_spdif_probe(struct platform_device *pdev)
340 {
341 struct device_node *np = pdev->dev.of_node;
342 struct rk_spdif_dev *spdif;
343 const struct of_device_id *match;
344 struct resource *res;
345 void __iomem *regs;
346 int ret;
347
348 match = of_match_node(rk_spdif_match, np);
349 if (match->data == (void *)RK_SPDIF_RK3288) {
350 struct regmap *grf;
351
352 grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
353 if (IS_ERR(grf)) {
354 dev_err(&pdev->dev,
355 "rockchip_spdif missing 'rockchip,grf'\n");
356 return PTR_ERR(grf);
357 }
358
359 /* Select the 8 channel SPDIF solution on RK3288 as
360 * the 2 channel one does not appear to work
361 */
362 regmap_write(grf, RK3288_GRF_SOC_CON2, BIT(1) << 16);
363 }
364
365 spdif = devm_kzalloc(&pdev->dev, sizeof(*spdif), GFP_KERNEL);
366 if (!spdif)
367 return -ENOMEM;
368
369 spdif->hclk = devm_clk_get(&pdev->dev, "hclk");
370 if (IS_ERR(spdif->hclk))
371 return PTR_ERR(spdif->hclk);
372
373 spdif->mclk = devm_clk_get(&pdev->dev, "mclk");
374 if (IS_ERR(spdif->mclk))
375 return PTR_ERR(spdif->mclk);
376
377 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
378 if (IS_ERR(regs))
379 return PTR_ERR(regs);
380
381 spdif->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "hclk", regs,
382 &rk_spdif_regmap_config);
383 if (IS_ERR(spdif->regmap))
384 return PTR_ERR(spdif->regmap);
385
386 spdif->playback_dma_data.addr = res->start + SPDIF_SMPDR;
387 spdif->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
388 spdif->playback_dma_data.maxburst = 4;
389
390 spdif->dev = &pdev->dev;
391 dev_set_drvdata(&pdev->dev, spdif);
392
393 pm_runtime_enable(&pdev->dev);
394 if (!pm_runtime_enabled(&pdev->dev)) {
395 ret = rk_spdif_runtime_resume(&pdev->dev);
396 if (ret)
397 goto err_pm_runtime;
398 }
399
400 ret = devm_snd_soc_register_component(&pdev->dev,
401 &rk_spdif_component,
402 &rk_spdif_dai, 1);
403 if (ret) {
404 dev_err(&pdev->dev, "Could not register DAI\n");
405 goto err_pm_suspend;
406 }
407
408 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
409 if (ret) {
410 dev_err(&pdev->dev, "Could not register PCM\n");
411 goto err_pm_suspend;
412 }
413
414 return 0;
415
416 err_pm_suspend:
417 if (!pm_runtime_status_suspended(&pdev->dev))
418 rk_spdif_runtime_suspend(&pdev->dev);
419 err_pm_runtime:
420 pm_runtime_disable(&pdev->dev);
421
422 return ret;
423 }
424
rk_spdif_remove(struct platform_device * pdev)425 static int rk_spdif_remove(struct platform_device *pdev)
426 {
427 pm_runtime_disable(&pdev->dev);
428 if (!pm_runtime_status_suspended(&pdev->dev))
429 rk_spdif_runtime_suspend(&pdev->dev);
430
431 return 0;
432 }
433
434 static const struct dev_pm_ops rk_spdif_pm_ops = {
435 SET_RUNTIME_PM_OPS(rk_spdif_runtime_suspend, rk_spdif_runtime_resume,
436 NULL)
437 };
438
439 static struct platform_driver rk_spdif_driver = {
440 .probe = rk_spdif_probe,
441 .remove = rk_spdif_remove,
442 .driver = {
443 .name = "rockchip-spdif",
444 .of_match_table = of_match_ptr(rk_spdif_match),
445 .pm = &rk_spdif_pm_ops,
446 },
447 };
448 module_platform_driver(rk_spdif_driver);
449
450 MODULE_ALIAS("platform:rockchip-spdif");
451 MODULE_DESCRIPTION("ROCKCHIP SPDIF transceiver Interface");
452 MODULE_AUTHOR("Sjoerd Simons <sjoerd.simons@collabora.co.uk>");
453 MODULE_LICENSE("GPL v2");
454