1 /* sound/soc/rockchip/rockchip_i2s_tdm.c
2 *
3 * ALSA SoC Audio Layer - Rockchip I2S/TDM Controller driver
4 *
5 * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
6 * Author: Sugar Zhang <sugar.zhang@rock-chips.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/module.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/delay.h>
16 #include <linux/of_gpio.h>
17 #include <linux/of_device.h>
18 #include <linux/of_address.h>
19 #include <linux/clk.h>
20 #include <linux/clk-provider.h>
21 #include <linux/clk/rockchip.h>
22 #include <linux/pinctrl/consumer.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/regmap.h>
25 #include <linux/reset.h>
26 #include <linux/spinlock.h>
27 #include <sound/pcm_params.h>
28 #include <sound/dmaengine_pcm.h>
29
30 #include "rockchip_i2s_tdm.h"
31 #include "rockchip_dlp.h"
32
33 #define DRV_NAME "rockchip-i2s-tdm"
34
35 #if IS_ENABLED(CONFIG_CPU_PX30) || IS_ENABLED(CONFIG_CPU_RK1808) || IS_ENABLED(CONFIG_CPU_RK3308)
36 #define HAVE_SYNC_RESET
37 #endif
38
39 #ifdef CONFIG_SND_SOC_ROCKCHIP_I2S_TDM_MULTI_LANES
40 /*
41 * Example: RK3588
42 *
43 * Use I2S2_2CH as Clk-Gen to serve TDM_MULTI_LANES
44 *
45 * I2S2_2CH ----> BCLK,I2S_LRCK --------> I2S0_8CH_TX (Slave TRCM-TXONLY)
46 * |
47 * |--------> BCLK,TDM_SYNC --------> TDM Device (Slave)
48 *
49 * Note:
50 *
51 * I2S2_2CH_MCLK: BCLK
52 * I2S2_2CH_SCLK: I2S_LRCK (GPIO2_B7)
53 * I2S2_2CH_LRCK: TDM_SYNC (GPIO2_C0)
54 *
55 */
56
57 #define CLK_MAX_COUNT 1000
58 #define NSAMPLES 4
59 #define XFER_EN 0x3
60 #define XFER_DIS 0x0
61 #define CKR_V(m, r, t) ((m - 1) << 16 | (r - 1) << 8 | (t - 1) << 0)
62 #define I2S_XCR_IBM_V(v) ((v) & I2S_TXCR_IBM_MASK)
63 #define I2S_XCR_IBM_NORMAL I2S_TXCR_IBM_NORMAL
64 #define I2S_XCR_IBM_LSJM I2S_TXCR_IBM_LSJM
65 #endif
66
67 #define DEFAULT_MCLK_FS 256
68 #define DEFAULT_FS 48000
69 #define CH_GRP_MAX 4 /* The max channel 8 / 2 */
70 #define MULTIPLEX_CH_MAX 10
71 #define CLK_PPM_MIN (-1000)
72 #define CLK_PPM_MAX (1000)
73 #define MAXBURST_PER_FIFO 8
74
75 #define QUIRK_ALWAYS_ON BIT(0)
76 #define QUIRK_HDMI_PATH BIT(1)
77
78 struct txrx_config {
79 u32 addr;
80 u32 reg;
81 u32 txonly;
82 u32 rxonly;
83 };
84
85 struct rk_i2s_soc_data {
86 u32 softrst_offset;
87 u32 grf_reg_offset;
88 u32 grf_shift;
89 int config_count;
90 const struct txrx_config *configs;
91 int (*init)(struct device *dev, u32 addr);
92 };
93
94 struct rk_i2s_tdm_dev {
95 struct device *dev;
96 struct clk *hclk;
97 struct clk *mclk_tx;
98 struct clk *mclk_rx;
99 /* The mclk_tx_src is parent of mclk_tx */
100 struct clk *mclk_tx_src;
101 /* The mclk_rx_src is parent of mclk_rx */
102 struct clk *mclk_rx_src;
103 /*
104 * The mclk_root0 and mclk_root1 are root parent and supplies for
105 * the different FS.
106 *
107 * e.g:
108 * mclk_root0 is VPLL0, used for FS=48000Hz
109 * mclk_root0 is VPLL1, used for FS=44100Hz
110 */
111 struct clk *mclk_root0;
112 struct clk *mclk_root1;
113 struct regmap *regmap;
114 struct regmap *grf;
115 struct snd_dmaengine_dai_dma_data capture_dma_data;
116 struct snd_dmaengine_dai_dma_data playback_dma_data;
117 struct snd_pcm_substream *substreams[SNDRV_PCM_STREAM_LAST + 1];
118 struct reset_control *tx_reset;
119 struct reset_control *rx_reset;
120 struct pinctrl *pinctrl;
121 struct pinctrl_state *clk_state;
122 const struct rk_i2s_soc_data *soc_data;
123 #ifdef HAVE_SYNC_RESET
124 void __iomem *cru_base;
125 int tx_reset_id;
126 int rx_reset_id;
127 #endif
128 bool is_master_mode;
129 bool io_multiplex;
130 bool mclk_calibrate;
131 bool tdm_mode;
132 bool tdm_fsync_half_frame;
133 bool is_dma_active[SNDRV_PCM_STREAM_LAST + 1];
134 unsigned int mclk_rx_freq;
135 unsigned int mclk_tx_freq;
136 unsigned int mclk_root0_freq;
137 unsigned int mclk_root1_freq;
138 unsigned int mclk_root0_initial_freq;
139 unsigned int mclk_root1_initial_freq;
140 unsigned int bclk_fs;
141 unsigned int clk_trcm;
142 unsigned int i2s_sdis[CH_GRP_MAX];
143 unsigned int i2s_sdos[CH_GRP_MAX];
144 unsigned int quirks;
145 unsigned int lrck_ratio;
146 int clk_ppm;
147 atomic_t refcount;
148 spinlock_t lock; /* xfer lock */
149 #ifdef CONFIG_SND_SOC_ROCKCHIP_I2S_TDM_MULTI_LANES
150 struct snd_soc_dai *clk_src_dai;
151 struct gpio_desc *i2s_lrck_gpio;
152 struct gpio_desc *tdm_fsync_gpio;
153 unsigned int tx_lanes;
154 unsigned int rx_lanes;
155 void __iomem *clk_src_base;
156 bool is_tdm_multi_lanes;
157 #endif
158 };
159
160 static struct i2s_of_quirks {
161 char *quirk;
162 int id;
163 } of_quirks[] = {
164 {
165 .quirk = "rockchip,always-on",
166 .id = QUIRK_ALWAYS_ON,
167 },
168 {
169 .quirk = "rockchip,hdmi-path",
170 .id = QUIRK_HDMI_PATH,
171 },
172 };
173
to_ch_num(unsigned int val)174 static int to_ch_num(unsigned int val)
175 {
176 int chs;
177
178 switch (val) {
179 case I2S_CHN_4:
180 chs = 4;
181 break;
182 case I2S_CHN_6:
183 chs = 6;
184 break;
185 case I2S_CHN_8:
186 chs = 8;
187 break;
188 default:
189 chs = 2;
190 break;
191 }
192
193 return chs;
194 }
195
i2s_tdm_runtime_suspend(struct device * dev)196 static int i2s_tdm_runtime_suspend(struct device *dev)
197 {
198 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
199
200 regcache_cache_only(i2s_tdm->regmap, true);
201
202 clk_disable_unprepare(i2s_tdm->mclk_tx);
203 clk_disable_unprepare(i2s_tdm->mclk_rx);
204
205 pinctrl_pm_select_idle_state(dev);
206
207 return 0;
208 }
209
rockchip_i2s_tdm_pinctrl_select_clk_state(struct device * dev)210 static int rockchip_i2s_tdm_pinctrl_select_clk_state(struct device *dev)
211 {
212 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
213
214 if (IS_ERR_OR_NULL(i2s_tdm->pinctrl) || !i2s_tdm->clk_state)
215 return 0;
216
217 pinctrl_select_state(i2s_tdm->pinctrl, i2s_tdm->clk_state);
218
219 return 0;
220 }
221
i2s_tdm_runtime_resume(struct device * dev)222 static int i2s_tdm_runtime_resume(struct device *dev)
223 {
224 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
225 int ret;
226
227 /*
228 * pinctrl default state is invoked by ASoC framework, so,
229 * we just handle clk state here if DT assigned.
230 */
231 if (i2s_tdm->is_master_mode)
232 rockchip_i2s_tdm_pinctrl_select_clk_state(dev);
233
234 ret = clk_prepare_enable(i2s_tdm->mclk_tx);
235 if (ret)
236 goto err_mclk_tx;
237
238 ret = clk_prepare_enable(i2s_tdm->mclk_rx);
239 if (ret)
240 goto err_mclk_rx;
241
242 regcache_cache_only(i2s_tdm->regmap, false);
243 regcache_mark_dirty(i2s_tdm->regmap);
244 ret = regcache_sync(i2s_tdm->regmap);
245 if (ret)
246 goto err_regmap;
247
248 /*
249 * should be placed after regcache sync done to back
250 * to the slave mode and then enable clk state.
251 */
252 if (!i2s_tdm->is_master_mode)
253 rockchip_i2s_tdm_pinctrl_select_clk_state(dev);
254
255 return 0;
256
257 err_regmap:
258 clk_disable_unprepare(i2s_tdm->mclk_rx);
259 err_mclk_rx:
260 clk_disable_unprepare(i2s_tdm->mclk_tx);
261 err_mclk_tx:
262 return ret;
263 }
264
to_info(struct snd_soc_dai * dai)265 static inline struct rk_i2s_tdm_dev *to_info(struct snd_soc_dai *dai)
266 {
267 return snd_soc_dai_get_drvdata(dai);
268 }
269
is_stream_active(struct rk_i2s_tdm_dev * i2s_tdm,int stream)270 static inline bool is_stream_active(struct rk_i2s_tdm_dev *i2s_tdm, int stream)
271 {
272 unsigned int val;
273
274 regmap_read(i2s_tdm->regmap, I2S_XFER, &val);
275
276 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
277 return (val & I2S_XFER_TXS_START);
278 else
279 return (val & I2S_XFER_RXS_START);
280 }
281
is_dma_active(struct rk_i2s_tdm_dev * i2s_tdm,int stream)282 static inline bool is_dma_active(struct rk_i2s_tdm_dev *i2s_tdm, int stream)
283 {
284 unsigned int val;
285
286 regmap_read(i2s_tdm->regmap, I2S_DMACR, &val);
287
288 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
289 return (val & I2S_DMACR_TDE_MASK);
290 else
291 return (val & I2S_DMACR_RDE_MASK);
292 }
293
294 #ifdef HAVE_SYNC_RESET
295 #if defined(CONFIG_ARM) && !defined(writeq)
__raw_writeq(u64 val,volatile void __iomem * addr)296 static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
297 {
298 asm volatile("strd %0, %H0, [%1]" : : "r" (val), "r" (addr));
299 }
300 #define writeq(v,c) ({ __iowmb(); __raw_writeq((__force u64) cpu_to_le64(v), c); })
301 #endif
302
rockchip_i2s_tdm_reset_assert(struct rk_i2s_tdm_dev * i2s_tdm)303 static void rockchip_i2s_tdm_reset_assert(struct rk_i2s_tdm_dev *i2s_tdm)
304 {
305 int tx_bank, rx_bank, tx_offset, rx_offset, tx_id, rx_id;
306 void __iomem *cru_reset, *addr;
307 unsigned long flags;
308 u64 val;
309
310 if (!i2s_tdm->cru_base || !i2s_tdm->soc_data || !i2s_tdm->is_master_mode)
311 return;
312
313 tx_id = i2s_tdm->tx_reset_id;
314 rx_id = i2s_tdm->rx_reset_id;
315 if (tx_id < 0 || rx_id < 0)
316 return;
317
318 tx_bank = tx_id / 16;
319 tx_offset = tx_id % 16;
320 rx_bank = rx_id / 16;
321 rx_offset = rx_id % 16;
322
323 dev_dbg(i2s_tdm->dev,
324 "tx_bank: %d, rx_bank: %d,tx_offset: %d, rx_offset: %d\n",
325 tx_bank, rx_bank, tx_offset, rx_offset);
326
327 cru_reset = i2s_tdm->cru_base + i2s_tdm->soc_data->softrst_offset;
328
329 switch (abs(tx_bank - rx_bank)) {
330 case 0:
331 writel(BIT(tx_offset) | BIT(rx_offset) |
332 (BIT(tx_offset) << 16) | (BIT(rx_offset) << 16),
333 cru_reset + (tx_bank * 4));
334 break;
335 case 1:
336 if (tx_bank < rx_bank) {
337 val = BIT(rx_offset) | (BIT(rx_offset) << 16);
338 val <<= 32;
339 val |= BIT(tx_offset) | (BIT(tx_offset) << 16);
340 addr = cru_reset + (tx_bank * 4);
341 } else {
342 val = BIT(tx_offset) | (BIT(tx_offset) << 16);
343 val <<= 32;
344 val |= BIT(rx_offset) | (BIT(rx_offset) << 16);
345 addr = cru_reset + (rx_bank * 4);
346 }
347
348 if (IS_ALIGNED((uintptr_t)addr, 8)) {
349 writeq(val, addr);
350 break;
351 }
352 fallthrough;
353 default:
354 local_irq_save(flags);
355 writel(BIT(tx_offset) | (BIT(tx_offset) << 16),
356 cru_reset + (tx_bank * 4));
357 writel(BIT(rx_offset) | (BIT(rx_offset) << 16),
358 cru_reset + (rx_bank * 4));
359 local_irq_restore(flags);
360 break;
361 }
362 /* delay for reset assert done */
363 udelay(10);
364 }
365
rockchip_i2s_tdm_reset_deassert(struct rk_i2s_tdm_dev * i2s_tdm)366 static void rockchip_i2s_tdm_reset_deassert(struct rk_i2s_tdm_dev *i2s_tdm)
367 {
368 int tx_bank, rx_bank, tx_offset, rx_offset, tx_id, rx_id;
369 void __iomem *cru_reset, *addr;
370 unsigned long flags;
371 u64 val;
372
373 if (!i2s_tdm->cru_base || !i2s_tdm->soc_data || !i2s_tdm->is_master_mode)
374 return;
375
376 tx_id = i2s_tdm->tx_reset_id;
377 rx_id = i2s_tdm->rx_reset_id;
378 if (tx_id < 0 || rx_id < 0)
379 return;
380
381 tx_bank = tx_id / 16;
382 tx_offset = tx_id % 16;
383 rx_bank = rx_id / 16;
384 rx_offset = rx_id % 16;
385
386 dev_dbg(i2s_tdm->dev,
387 "tx_bank: %d, rx_bank: %d,tx_offset: %d, rx_offset: %d\n",
388 tx_bank, rx_bank, tx_offset, rx_offset);
389
390 cru_reset = i2s_tdm->cru_base + i2s_tdm->soc_data->softrst_offset;
391
392 switch (abs(tx_bank - rx_bank)) {
393 case 0:
394 writel((BIT(tx_offset) << 16) | (BIT(rx_offset) << 16),
395 cru_reset + (tx_bank * 4));
396 break;
397 case 1:
398 if (tx_bank < rx_bank) {
399 val = (BIT(rx_offset) << 16);
400 val <<= 32;
401 val |= (BIT(tx_offset) << 16);
402 addr = cru_reset + (tx_bank * 4);
403 } else {
404 val = (BIT(tx_offset) << 16);
405 val <<= 32;
406 val |= (BIT(rx_offset) << 16);
407 addr = cru_reset + (rx_bank * 4);
408 }
409
410 if (IS_ALIGNED((uintptr_t)addr, 8)) {
411 writeq(val, addr);
412 break;
413 }
414 fallthrough;
415 default:
416 local_irq_save(flags);
417 writel((BIT(tx_offset) << 16),
418 cru_reset + (tx_bank * 4));
419 writel((BIT(rx_offset) << 16),
420 cru_reset + (rx_bank * 4));
421 local_irq_restore(flags);
422 break;
423 }
424 /* delay for reset deassert done */
425 udelay(10);
426 }
427
428 /*
429 * make sure both tx and rx are reset at the same time for sync lrck
430 * when clk_trcm > 0
431 */
rockchip_i2s_tdm_sync_reset(struct rk_i2s_tdm_dev * i2s_tdm)432 static void rockchip_i2s_tdm_sync_reset(struct rk_i2s_tdm_dev *i2s_tdm)
433 {
434 rockchip_i2s_tdm_reset_assert(i2s_tdm);
435 rockchip_i2s_tdm_reset_deassert(i2s_tdm);
436 }
437 #else
rockchip_i2s_tdm_reset_assert(struct rk_i2s_tdm_dev * i2s_tdm)438 static inline void rockchip_i2s_tdm_reset_assert(struct rk_i2s_tdm_dev *i2s_tdm)
439 {
440 }
rockchip_i2s_tdm_reset_deassert(struct rk_i2s_tdm_dev * i2s_tdm)441 static inline void rockchip_i2s_tdm_reset_deassert(struct rk_i2s_tdm_dev *i2s_tdm)
442 {
443 }
rockchip_i2s_tdm_sync_reset(struct rk_i2s_tdm_dev * i2s_tdm)444 static inline void rockchip_i2s_tdm_sync_reset(struct rk_i2s_tdm_dev *i2s_tdm)
445 {
446 }
447 #endif
448
rockchip_i2s_tdm_reset(struct reset_control * rc)449 static void rockchip_i2s_tdm_reset(struct reset_control *rc)
450 {
451 if (IS_ERR_OR_NULL(rc))
452 return;
453
454 reset_control_assert(rc);
455 /* delay for reset assert done */
456 udelay(10);
457 reset_control_deassert(rc);
458 /* delay for reset deassert done */
459 udelay(10);
460 }
461
rockchip_i2s_tdm_clear(struct rk_i2s_tdm_dev * i2s_tdm,unsigned int clr)462 static int rockchip_i2s_tdm_clear(struct rk_i2s_tdm_dev *i2s_tdm,
463 unsigned int clr)
464 {
465 struct reset_control *rst = NULL;
466 unsigned int val = 0;
467 int ret = 0;
468
469 switch (clr) {
470 case I2S_CLR_TXC:
471 rst = i2s_tdm->tx_reset;
472 break;
473 case I2S_CLR_RXC:
474 rst = i2s_tdm->rx_reset;
475 break;
476 case I2S_CLR_TXC | I2S_CLR_RXC:
477 break;
478 default:
479 return -EINVAL;
480 }
481
482 regmap_update_bits(i2s_tdm->regmap, I2S_CLR, clr, clr);
483 ret = regmap_read_poll_timeout_atomic(i2s_tdm->regmap, I2S_CLR, val,
484 !(val & clr), 10, 100);
485 if (ret == 0)
486 return 0;
487
488 /*
489 * Workaround for FIFO clear on SLAVE mode:
490 *
491 * A Suggest to do reset hclk domain and then do mclk
492 * domain, especially for SLAVE mode without CLK in.
493 * at last, recovery regmap config.
494 *
495 * B Suggest to switch to MASTER, and then do FIFO clr,
496 * at last, bring back to SLAVE.
497 *
498 * Now we choose plan B here.
499 */
500 if (!i2s_tdm->is_master_mode)
501 regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
502 I2S_CKR_MSS_MASK, I2S_CKR_MSS_MASTER);
503 regmap_update_bits(i2s_tdm->regmap, I2S_CLR, clr, clr);
504 ret = regmap_read_poll_timeout_atomic(i2s_tdm->regmap, I2S_CLR, val,
505 !(val & clr), 10, 100);
506 if (!i2s_tdm->is_master_mode)
507 regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
508 I2S_CKR_MSS_MASK, I2S_CKR_MSS_SLAVE);
509
510 if (ret < 0) {
511 dev_warn(i2s_tdm->dev, "failed to clear %u on %s mode\n",
512 clr, i2s_tdm->is_master_mode ? "master" : "slave");
513 goto reset;
514 }
515
516 return 0;
517
518 reset:
519 if (i2s_tdm->clk_trcm)
520 rockchip_i2s_tdm_sync_reset(i2s_tdm);
521 else
522 rockchip_i2s_tdm_reset(rst);
523
524 return 0;
525 }
526
527 /*
528 * HDMI controller ignores the first FRAME_SYNC cycle, Lost one frame is no big deal
529 * for LPCM, but it does matter for Bitstream (NLPCM/HBR), So, padding one frame
530 * before xfer the real data to fix it.
531 */
rockchip_i2s_tdm_tx_fifo_padding(struct rk_i2s_tdm_dev * i2s_tdm,bool en)532 static void rockchip_i2s_tdm_tx_fifo_padding(struct rk_i2s_tdm_dev *i2s_tdm, bool en)
533 {
534 unsigned int val, w, c, i;
535
536 if (!en)
537 return;
538
539 regmap_read(i2s_tdm->regmap, I2S_TXCR, &val);
540 w = ((val & I2S_TXCR_VDW_MASK) >> I2S_TXCR_VDW_SHIFT) + 1;
541 c = to_ch_num(val & I2S_TXCR_CSR_MASK) * w / 32;
542
543 for (i = 0; i < c; i++)
544 regmap_write(i2s_tdm->regmap, I2S_TXDR, 0x0);
545 }
546
rockchip_i2s_tdm_fifo_xrun_detect(struct rk_i2s_tdm_dev * i2s_tdm,int stream,bool en)547 static void rockchip_i2s_tdm_fifo_xrun_detect(struct rk_i2s_tdm_dev *i2s_tdm,
548 int stream, bool en)
549 {
550 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
551 /* clear irq status which was asserted before TXUIE enabled */
552 regmap_update_bits(i2s_tdm->regmap, I2S_INTCR,
553 I2S_INTCR_TXUIC, I2S_INTCR_TXUIC);
554 regmap_update_bits(i2s_tdm->regmap, I2S_INTCR,
555 I2S_INTCR_TXUIE_MASK,
556 I2S_INTCR_TXUIE(en));
557 } else {
558 /* clear irq status which was asserted before RXOIE enabled */
559 regmap_update_bits(i2s_tdm->regmap, I2S_INTCR,
560 I2S_INTCR_RXOIC, I2S_INTCR_RXOIC);
561 regmap_update_bits(i2s_tdm->regmap, I2S_INTCR,
562 I2S_INTCR_RXOIE_MASK,
563 I2S_INTCR_RXOIE(en));
564 }
565 }
566
rockchip_i2s_tdm_dma_ctrl(struct rk_i2s_tdm_dev * i2s_tdm,int stream,bool en)567 static void rockchip_i2s_tdm_dma_ctrl(struct rk_i2s_tdm_dev *i2s_tdm,
568 int stream, bool en)
569 {
570 if (!en)
571 rockchip_i2s_tdm_fifo_xrun_detect(i2s_tdm, stream, 0);
572
573 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
574 if (i2s_tdm->quirks & QUIRK_HDMI_PATH)
575 rockchip_i2s_tdm_tx_fifo_padding(i2s_tdm, en);
576
577 regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
578 I2S_DMACR_TDE_MASK,
579 I2S_DMACR_TDE(en));
580 /*
581 * Explicitly delay 1 usec for dma to fill FIFO,
582 * though there was a implied HW delay that around
583 * half LRCK cycle (e.g. 2.6us@192k) from XFER-start
584 * to FIFO-pop.
585 *
586 * 1 usec is enough to fill at lease 4 entry each FIFO
587 * @192k 8ch 32bit situation.
588 */
589 udelay(1);
590 } else {
591 regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
592 I2S_DMACR_RDE_MASK,
593 I2S_DMACR_RDE(en));
594 }
595
596 if (en)
597 rockchip_i2s_tdm_fifo_xrun_detect(i2s_tdm, stream, 1);
598 }
599
600 #ifdef CONFIG_SND_SOC_ROCKCHIP_I2S_TDM_MULTI_LANES
601 static const char * const tx_lanes_text[] = { "Auto", "SDOx1", "SDOx2", "SDOx3", "SDOx4" };
602 static const char * const rx_lanes_text[] = { "Auto", "SDIx1", "SDIx2", "SDIx3", "SDIx4" };
603 static const struct soc_enum tx_lanes_enum =
604 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_lanes_text), tx_lanes_text);
605 static const struct soc_enum rx_lanes_enum =
606 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_lanes_text), rx_lanes_text);
607
rockchip_i2s_tdm_tx_lanes_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)608 static int rockchip_i2s_tdm_tx_lanes_get(struct snd_kcontrol *kcontrol,
609 struct snd_ctl_elem_value *ucontrol)
610 {
611 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
612 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_component_get_drvdata(component);
613
614 ucontrol->value.enumerated.item[0] = i2s_tdm->tx_lanes;
615
616 return 0;
617 }
618
rockchip_i2s_tdm_tx_lanes_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)619 static int rockchip_i2s_tdm_tx_lanes_put(struct snd_kcontrol *kcontrol,
620 struct snd_ctl_elem_value *ucontrol)
621 {
622 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
623 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_component_get_drvdata(component);
624 int num;
625
626 num = ucontrol->value.enumerated.item[0];
627 if (num >= ARRAY_SIZE(tx_lanes_text))
628 return -EINVAL;
629
630 i2s_tdm->tx_lanes = num;
631
632 return 1;
633 }
634
rockchip_i2s_tdm_rx_lanes_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)635 static int rockchip_i2s_tdm_rx_lanes_get(struct snd_kcontrol *kcontrol,
636 struct snd_ctl_elem_value *ucontrol)
637 {
638 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
639 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_component_get_drvdata(component);
640
641 ucontrol->value.enumerated.item[0] = i2s_tdm->rx_lanes;
642
643 return 0;
644 }
645
rockchip_i2s_tdm_rx_lanes_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)646 static int rockchip_i2s_tdm_rx_lanes_put(struct snd_kcontrol *kcontrol,
647 struct snd_ctl_elem_value *ucontrol)
648 {
649 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
650 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_component_get_drvdata(component);
651 int num;
652
653 num = ucontrol->value.enumerated.item[0];
654 if (num >= ARRAY_SIZE(rx_lanes_text))
655 return -EINVAL;
656
657 i2s_tdm->rx_lanes = num;
658
659 return 1;
660 }
661
rockchip_i2s_tdm_get_lanes(struct rk_i2s_tdm_dev * i2s_tdm,int stream)662 static int rockchip_i2s_tdm_get_lanes(struct rk_i2s_tdm_dev *i2s_tdm, int stream)
663 {
664 unsigned int lanes = 1;
665
666 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
667 if (i2s_tdm->tx_lanes)
668 lanes = i2s_tdm->tx_lanes;
669 } else {
670 if (i2s_tdm->rx_lanes)
671 lanes = i2s_tdm->rx_lanes;
672 }
673
674 return lanes;
675 }
676
rockchip_i2s_tdm_find_dai(struct device_node * np)677 static struct snd_soc_dai *rockchip_i2s_tdm_find_dai(struct device_node *np)
678 {
679 struct snd_soc_dai_link_component dai_component = { 0 };
680
681 dai_component.of_node = np;
682
683 return snd_soc_find_dai_with_mutex(&dai_component);
684 }
685
rockchip_i2s_tdm_multi_lanes_set_clk(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * cpu_dai)686 static int rockchip_i2s_tdm_multi_lanes_set_clk(struct snd_pcm_substream *substream,
687 struct snd_pcm_hw_params *params,
688 struct snd_soc_dai *cpu_dai)
689 {
690 struct rk_i2s_tdm_dev *i2s_tdm = to_info(cpu_dai);
691 struct snd_soc_dai *dai = i2s_tdm->clk_src_dai;
692 unsigned int div, mclk_rate;
693 unsigned int lanes, ch_per_lane;
694
695 lanes = rockchip_i2s_tdm_get_lanes(i2s_tdm, substream->stream);
696 ch_per_lane = params_channels(params) / lanes;
697 mclk_rate = ch_per_lane * params_rate(params) * 32;
698 div = ch_per_lane / 2;
699
700 /* Do nothing when use external clk src */
701 if (dai && dai->driver->ops) {
702 if (dai->driver->ops->set_sysclk)
703 dai->driver->ops->set_sysclk(dai, substream->stream, mclk_rate, 0);
704
705 writel(XFER_DIS, i2s_tdm->clk_src_base + I2S_XFER);
706 writel(CKR_V(64, div, div), i2s_tdm->clk_src_base + I2S_CKR);
707 writel(XFER_EN, i2s_tdm->clk_src_base + I2S_XFER);
708 }
709
710 i2s_tdm->lrck_ratio = div;
711 i2s_tdm->mclk_tx_freq = mclk_rate;
712 i2s_tdm->mclk_rx_freq = mclk_rate;
713
714 return 0;
715 }
716
tdm_multi_lanes_clk_assert_h(const struct gpio_desc * desc)717 static inline int tdm_multi_lanes_clk_assert_h(const struct gpio_desc *desc)
718 {
719 int cnt = CLK_MAX_COUNT;
720
721 while (gpiod_get_raw_value(desc) && --cnt)
722 ;
723
724 return cnt;
725 }
726
tdm_multi_lanes_clk_assert_l(const struct gpio_desc * desc)727 static inline int tdm_multi_lanes_clk_assert_l(const struct gpio_desc *desc)
728 {
729 int cnt = CLK_MAX_COUNT;
730
731 while (!gpiod_get_raw_value(desc) && --cnt)
732 ;
733
734 return cnt;
735 }
736
rockchip_i2s_tdm_clk_valid(struct rk_i2s_tdm_dev * i2s_tdm)737 static inline bool rockchip_i2s_tdm_clk_valid(struct rk_i2s_tdm_dev *i2s_tdm)
738 {
739 int dc_h = CLK_MAX_COUNT, dc_l = CLK_MAX_COUNT;
740
741 /*
742 * TBD: optimize debounce and get value
743 *
744 * debounce at least one cycle found, otherwise, the clk ref maybe
745 * not on the fly.
746 */
747
748 /* check HIGH-Level */
749 dc_h = tdm_multi_lanes_clk_assert_h(i2s_tdm->i2s_lrck_gpio);
750 if (!dc_h)
751 return false;
752
753 /* check LOW-Level */
754 dc_l = tdm_multi_lanes_clk_assert_l(i2s_tdm->i2s_lrck_gpio);
755 if (!dc_l)
756 return false;
757
758 /* check HIGH-Level */
759 dc_h = tdm_multi_lanes_clk_assert_h(i2s_tdm->tdm_fsync_gpio);
760 if (!dc_h)
761 return false;
762
763 /* check LOW-Level */
764 dc_l = tdm_multi_lanes_clk_assert_l(i2s_tdm->tdm_fsync_gpio);
765 if (!dc_l)
766 return false;
767
768 return true;
769 }
770
rockchip_i2s_tdm_gpio_clk_meas(struct rk_i2s_tdm_dev * i2s_tdm,const struct gpio_desc * desc,const char * name)771 static void __maybe_unused rockchip_i2s_tdm_gpio_clk_meas(struct rk_i2s_tdm_dev *i2s_tdm,
772 const struct gpio_desc *desc,
773 const char *name)
774 {
775 int h[NSAMPLES], l[NSAMPLES], i;
776
777 dev_dbg(i2s_tdm->dev, "%s:\n", name);
778
779 if (!rockchip_i2s_tdm_clk_valid(i2s_tdm))
780 return;
781
782 for (i = 0; i < NSAMPLES; i++) {
783 h[i] = tdm_multi_lanes_clk_assert_h(desc);
784 l[i] = tdm_multi_lanes_clk_assert_l(desc);
785 }
786
787 for (i = 0; i < NSAMPLES; i++)
788 dev_dbg(i2s_tdm->dev, "H[%d]: %2d, L[%d]: %2d\n",
789 i, CLK_MAX_COUNT - h[i], i, CLK_MAX_COUNT - l[i]);
790 }
791
rockchip_i2s_tdm_multi_lanes_start(struct rk_i2s_tdm_dev * i2s_tdm,int stream)792 static int rockchip_i2s_tdm_multi_lanes_start(struct rk_i2s_tdm_dev *i2s_tdm, int stream)
793 {
794 unsigned int tdm_h = 0, tdm_l = 0, i2s_h = 0, i2s_l = 0;
795 unsigned int msk, val, reg, fmt;
796 unsigned long flags;
797
798 if (!i2s_tdm->tdm_fsync_gpio || !i2s_tdm->i2s_lrck_gpio)
799 return -ENOSYS;
800
801 if (i2s_tdm->lrck_ratio != 4 && i2s_tdm->lrck_ratio != 8)
802 return -EINVAL;
803
804 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
805 msk = I2S_XFER_TXS_MASK;
806 val = I2S_XFER_TXS_START;
807 reg = I2S_TXCR;
808 } else {
809 msk = I2S_XFER_RXS_MASK;
810 val = I2S_XFER_RXS_START;
811 reg = I2S_RXCR;
812 }
813
814 regmap_read(i2s_tdm->regmap, reg, &fmt);
815 fmt = I2S_XCR_IBM_V(fmt);
816
817 local_irq_save(flags);
818
819 if (!rockchip_i2s_tdm_clk_valid(i2s_tdm)) {
820 local_irq_restore(flags);
821 dev_err(i2s_tdm->dev, "Invalid LRCK / FSYNC measured by ref IO\n");
822 return -EINVAL;
823 }
824
825 switch (fmt) {
826 case I2S_XCR_IBM_NORMAL:
827 tdm_h = tdm_multi_lanes_clk_assert_h(i2s_tdm->tdm_fsync_gpio);
828 tdm_l = tdm_multi_lanes_clk_assert_l(i2s_tdm->tdm_fsync_gpio);
829
830 if (i2s_tdm->lrck_ratio == 8) {
831 tdm_multi_lanes_clk_assert_l(i2s_tdm->i2s_lrck_gpio);
832 tdm_multi_lanes_clk_assert_h(i2s_tdm->i2s_lrck_gpio);
833 tdm_multi_lanes_clk_assert_l(i2s_tdm->i2s_lrck_gpio);
834 tdm_multi_lanes_clk_assert_h(i2s_tdm->i2s_lrck_gpio);
835 }
836
837 i2s_l = tdm_multi_lanes_clk_assert_l(i2s_tdm->i2s_lrck_gpio);
838
839 if (stream == SNDRV_PCM_STREAM_CAPTURE)
840 i2s_h = tdm_multi_lanes_clk_assert_h(i2s_tdm->i2s_lrck_gpio);
841 break;
842 case I2S_XCR_IBM_LSJM:
843 tdm_l = tdm_multi_lanes_clk_assert_l(i2s_tdm->tdm_fsync_gpio);
844 tdm_h = tdm_multi_lanes_clk_assert_h(i2s_tdm->tdm_fsync_gpio);
845
846 if (i2s_tdm->lrck_ratio == 8) {
847 tdm_multi_lanes_clk_assert_h(i2s_tdm->i2s_lrck_gpio);
848 tdm_multi_lanes_clk_assert_l(i2s_tdm->i2s_lrck_gpio);
849 tdm_multi_lanes_clk_assert_h(i2s_tdm->i2s_lrck_gpio);
850 tdm_multi_lanes_clk_assert_l(i2s_tdm->i2s_lrck_gpio);
851 }
852
853 tdm_multi_lanes_clk_assert_h(i2s_tdm->i2s_lrck_gpio);
854
855 i2s_l = tdm_multi_lanes_clk_assert_l(i2s_tdm->i2s_lrck_gpio);
856 i2s_h = tdm_multi_lanes_clk_assert_h(i2s_tdm->i2s_lrck_gpio);
857 break;
858 default:
859 local_irq_restore(flags);
860 return -EINVAL;
861 }
862
863 regmap_update_bits(i2s_tdm->regmap, I2S_XFER, msk, val);
864 local_irq_restore(flags);
865
866 dev_dbg(i2s_tdm->dev, "STREAM[%d]: TDM-H: %d, TDM-L: %d, I2S-H: %d, I2S-L: %d\n", stream,
867 CLK_MAX_COUNT - tdm_h, CLK_MAX_COUNT - tdm_l,
868 CLK_MAX_COUNT - i2s_h, CLK_MAX_COUNT - i2s_l);
869
870 return 0;
871 }
872 #endif
873
rockchip_i2s_tdm_xfer_start(struct rk_i2s_tdm_dev * i2s_tdm,int stream)874 static void rockchip_i2s_tdm_xfer_start(struct rk_i2s_tdm_dev *i2s_tdm,
875 int stream)
876 {
877 #ifdef CONFIG_SND_SOC_ROCKCHIP_I2S_TDM_MULTI_LANES
878 if (i2s_tdm->is_tdm_multi_lanes) {
879 if (rockchip_i2s_tdm_multi_lanes_start(i2s_tdm, stream) != -ENOSYS)
880 return;
881 }
882 #endif
883 if (i2s_tdm->clk_trcm) {
884 rockchip_i2s_tdm_reset_assert(i2s_tdm);
885 regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
886 I2S_XFER_TXS_MASK |
887 I2S_XFER_RXS_MASK,
888 I2S_XFER_TXS_START |
889 I2S_XFER_RXS_START);
890 rockchip_i2s_tdm_reset_deassert(i2s_tdm);
891 } else if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
892 regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
893 I2S_XFER_TXS_MASK,
894 I2S_XFER_TXS_START);
895 } else {
896 regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
897 I2S_XFER_RXS_MASK,
898 I2S_XFER_RXS_START);
899 }
900 }
901
rockchip_i2s_tdm_xfer_stop(struct rk_i2s_tdm_dev * i2s_tdm,int stream,bool force)902 static void rockchip_i2s_tdm_xfer_stop(struct rk_i2s_tdm_dev *i2s_tdm,
903 int stream, bool force)
904 {
905 unsigned int msk, val, clr;
906
907 if (i2s_tdm->quirks & QUIRK_ALWAYS_ON && !force)
908 return;
909
910 if (i2s_tdm->clk_trcm) {
911 msk = I2S_XFER_TXS_MASK | I2S_XFER_RXS_MASK;
912 val = I2S_XFER_TXS_STOP | I2S_XFER_RXS_STOP;
913 clr = I2S_CLR_TXC | I2S_CLR_RXC;
914 } else if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
915 msk = I2S_XFER_TXS_MASK;
916 val = I2S_XFER_TXS_STOP;
917 clr = I2S_CLR_TXC;
918 } else {
919 msk = I2S_XFER_RXS_MASK;
920 val = I2S_XFER_RXS_STOP;
921 clr = I2S_CLR_RXC;
922 }
923
924 regmap_update_bits(i2s_tdm->regmap, I2S_XFER, msk, val);
925
926 /* delay for LRCK signal integrity */
927 udelay(150);
928
929 rockchip_i2s_tdm_clear(i2s_tdm, clr);
930 }
931
rockchip_i2s_tdm_xfer_trcm_start(struct rk_i2s_tdm_dev * i2s_tdm)932 static void rockchip_i2s_tdm_xfer_trcm_start(struct rk_i2s_tdm_dev *i2s_tdm)
933 {
934 unsigned long flags;
935
936 spin_lock_irqsave(&i2s_tdm->lock, flags);
937 if (atomic_inc_return(&i2s_tdm->refcount) == 1)
938 rockchip_i2s_tdm_xfer_start(i2s_tdm, 0);
939 spin_unlock_irqrestore(&i2s_tdm->lock, flags);
940 }
941
rockchip_i2s_tdm_xfer_trcm_stop(struct rk_i2s_tdm_dev * i2s_tdm)942 static void rockchip_i2s_tdm_xfer_trcm_stop(struct rk_i2s_tdm_dev *i2s_tdm)
943 {
944 unsigned long flags;
945
946 spin_lock_irqsave(&i2s_tdm->lock, flags);
947 if (atomic_dec_and_test(&i2s_tdm->refcount))
948 rockchip_i2s_tdm_xfer_stop(i2s_tdm, 0, false);
949 spin_unlock_irqrestore(&i2s_tdm->lock, flags);
950 }
951
rockchip_i2s_tdm_trcm_pause(struct snd_pcm_substream * substream,struct rk_i2s_tdm_dev * i2s_tdm)952 static void rockchip_i2s_tdm_trcm_pause(struct snd_pcm_substream *substream,
953 struct rk_i2s_tdm_dev *i2s_tdm)
954 {
955 int stream = substream->stream;
956 int bstream = SNDRV_PCM_STREAM_LAST - stream;
957
958 /* store the current state, prepare for resume if necessary */
959 i2s_tdm->is_dma_active[bstream] = is_dma_active(i2s_tdm, bstream);
960
961 /* disable dma for both tx and rx */
962 rockchip_i2s_tdm_dma_ctrl(i2s_tdm, stream, 0);
963 rockchip_i2s_tdm_dma_ctrl(i2s_tdm, bstream, 0);
964 rockchip_i2s_tdm_xfer_stop(i2s_tdm, bstream, true);
965 }
966
rockchip_i2s_tdm_trcm_resume(struct snd_pcm_substream * substream,struct rk_i2s_tdm_dev * i2s_tdm)967 static void rockchip_i2s_tdm_trcm_resume(struct snd_pcm_substream *substream,
968 struct rk_i2s_tdm_dev *i2s_tdm)
969 {
970 int bstream = SNDRV_PCM_STREAM_LAST - substream->stream;
971
972 /*
973 * just resume bstream, because current stream will be
974 * startup in the trigger-cmd-START
975 */
976 if (i2s_tdm->is_dma_active[bstream])
977 rockchip_i2s_tdm_dma_ctrl(i2s_tdm, bstream, 1);
978 rockchip_i2s_tdm_xfer_start(i2s_tdm, bstream);
979 }
980
rockchip_i2s_tdm_start(struct rk_i2s_tdm_dev * i2s_tdm,int stream)981 static void rockchip_i2s_tdm_start(struct rk_i2s_tdm_dev *i2s_tdm, int stream)
982 {
983 /*
984 * On HDMI-PATH-ALWAYS-ON situation, we almost keep XFER always on,
985 * so, for new data start, suggested to STOP-CLEAR-START to make sure
986 * data aligned.
987 */
988 if ((i2s_tdm->quirks & QUIRK_HDMI_PATH) &&
989 (i2s_tdm->quirks & QUIRK_ALWAYS_ON) &&
990 (stream == SNDRV_PCM_STREAM_PLAYBACK)) {
991 rockchip_i2s_tdm_xfer_stop(i2s_tdm, stream, true);
992 }
993
994 rockchip_i2s_tdm_dma_ctrl(i2s_tdm, stream, 1);
995
996 if (i2s_tdm->clk_trcm)
997 rockchip_i2s_tdm_xfer_trcm_start(i2s_tdm);
998 else
999 rockchip_i2s_tdm_xfer_start(i2s_tdm, stream);
1000 }
1001
rockchip_i2s_tdm_stop(struct rk_i2s_tdm_dev * i2s_tdm,int stream)1002 static void rockchip_i2s_tdm_stop(struct rk_i2s_tdm_dev *i2s_tdm, int stream)
1003 {
1004 rockchip_i2s_tdm_dma_ctrl(i2s_tdm, stream, 0);
1005
1006 if (i2s_tdm->clk_trcm)
1007 rockchip_i2s_tdm_xfer_trcm_stop(i2s_tdm);
1008 else
1009 rockchip_i2s_tdm_xfer_stop(i2s_tdm, stream, false);
1010 }
1011
rockchip_i2s_tdm_set_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)1012 static int rockchip_i2s_tdm_set_fmt(struct snd_soc_dai *cpu_dai,
1013 unsigned int fmt)
1014 {
1015 struct rk_i2s_tdm_dev *i2s_tdm = to_info(cpu_dai);
1016 unsigned int mask = 0, val = 0, tdm_val = 0;
1017 int ret = 0;
1018 bool is_tdm = i2s_tdm->tdm_mode;
1019
1020 pm_runtime_get_sync(cpu_dai->dev);
1021 mask = I2S_CKR_MSS_MASK;
1022 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1023 case SND_SOC_DAIFMT_CBS_CFS:
1024 val = I2S_CKR_MSS_MASTER;
1025 i2s_tdm->is_master_mode = true;
1026 break;
1027 case SND_SOC_DAIFMT_CBM_CFM:
1028 val = I2S_CKR_MSS_SLAVE;
1029 i2s_tdm->is_master_mode = false;
1030 /*
1031 * TRCM require TX/RX enabled at the same time, or need the one
1032 * which provide clk enabled at first for master mode.
1033 *
1034 * It is quite a different for slave mode which does not have
1035 * these restrictions, because the BCLK / LRCK are provided by
1036 * external master devices.
1037 *
1038 * So, we just set the right clk path value on TRCM register on
1039 * stage probe and then drop the trcm value to make TX / RX work
1040 * independently.
1041 */
1042 i2s_tdm->clk_trcm = 0;
1043 break;
1044 default:
1045 ret = -EINVAL;
1046 goto err_pm_put;
1047 }
1048
1049 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, mask, val);
1050
1051 mask = I2S_CKR_CKP_MASK | I2S_CKR_TLP_MASK | I2S_CKR_RLP_MASK;
1052 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1053 case SND_SOC_DAIFMT_NB_NF:
1054 val = I2S_CKR_CKP_NORMAL |
1055 I2S_CKR_TLP_NORMAL |
1056 I2S_CKR_RLP_NORMAL;
1057 break;
1058 case SND_SOC_DAIFMT_NB_IF:
1059 val = I2S_CKR_CKP_NORMAL |
1060 I2S_CKR_TLP_INVERTED |
1061 I2S_CKR_RLP_INVERTED;
1062 break;
1063 case SND_SOC_DAIFMT_IB_NF:
1064 val = I2S_CKR_CKP_INVERTED |
1065 I2S_CKR_TLP_NORMAL |
1066 I2S_CKR_RLP_NORMAL;
1067 break;
1068 case SND_SOC_DAIFMT_IB_IF:
1069 val = I2S_CKR_CKP_INVERTED |
1070 I2S_CKR_TLP_INVERTED |
1071 I2S_CKR_RLP_INVERTED;
1072 break;
1073 default:
1074 ret = -EINVAL;
1075 goto err_pm_put;
1076 }
1077
1078 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, mask, val);
1079
1080 mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK;
1081 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1082 case SND_SOC_DAIFMT_RIGHT_J:
1083 val = I2S_TXCR_IBM_RSJM;
1084 break;
1085 case SND_SOC_DAIFMT_LEFT_J:
1086 val = I2S_TXCR_IBM_LSJM;
1087 break;
1088 case SND_SOC_DAIFMT_I2S:
1089 val = I2S_TXCR_IBM_NORMAL;
1090 break;
1091 case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 mode */
1092 val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1);
1093 break;
1094 case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
1095 val = I2S_TXCR_TFS_PCM;
1096 break;
1097 default:
1098 ret = -EINVAL;
1099 goto err_pm_put;
1100 }
1101
1102 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, mask, val);
1103
1104 mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK;
1105 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1106 case SND_SOC_DAIFMT_RIGHT_J:
1107 val = I2S_RXCR_IBM_RSJM;
1108 break;
1109 case SND_SOC_DAIFMT_LEFT_J:
1110 val = I2S_RXCR_IBM_LSJM;
1111 break;
1112 case SND_SOC_DAIFMT_I2S:
1113 val = I2S_RXCR_IBM_NORMAL;
1114 break;
1115 case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 mode */
1116 val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1);
1117 break;
1118 case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
1119 val = I2S_RXCR_TFS_PCM;
1120 break;
1121 default:
1122 ret = -EINVAL;
1123 goto err_pm_put;
1124 }
1125
1126 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, mask, val);
1127
1128 if (is_tdm) {
1129 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1130 case SND_SOC_DAIFMT_RIGHT_J:
1131 val = I2S_TXCR_TFS_TDM_I2S;
1132 tdm_val = TDM_SHIFT_CTRL(2);
1133 break;
1134 case SND_SOC_DAIFMT_LEFT_J:
1135 val = I2S_TXCR_TFS_TDM_I2S;
1136 tdm_val = TDM_SHIFT_CTRL(1);
1137 break;
1138 case SND_SOC_DAIFMT_I2S:
1139 val = I2S_TXCR_TFS_TDM_I2S;
1140 tdm_val = TDM_SHIFT_CTRL(0);
1141 break;
1142 case SND_SOC_DAIFMT_DSP_A:
1143 val = I2S_TXCR_TFS_TDM_PCM;
1144 tdm_val = TDM_SHIFT_CTRL(2);
1145 break;
1146 case SND_SOC_DAIFMT_DSP_B:
1147 val = I2S_TXCR_TFS_TDM_PCM;
1148 tdm_val = TDM_SHIFT_CTRL(4);
1149 break;
1150 default:
1151 ret = -EINVAL;
1152 goto err_pm_put;
1153 }
1154
1155 tdm_val |= TDM_FSYNC_WIDTH_SEL1(1);
1156 if (i2s_tdm->tdm_fsync_half_frame)
1157 tdm_val |= TDM_FSYNC_WIDTH_HALF_FRAME;
1158 else
1159 tdm_val |= TDM_FSYNC_WIDTH_ONE_FRAME;
1160
1161 mask = I2S_TXCR_TFS_MASK;
1162 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, mask, val);
1163 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, mask, val);
1164
1165 mask = TDM_FSYNC_WIDTH_SEL1_MSK | TDM_FSYNC_WIDTH_SEL0_MSK |
1166 TDM_SHIFT_CTRL_MSK;
1167 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_TXCR,
1168 mask, tdm_val);
1169 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_RXCR,
1170 mask, tdm_val);
1171
1172 if (val == I2S_TXCR_TFS_TDM_I2S && !i2s_tdm->tdm_fsync_half_frame) {
1173 /* refine frame width for TDM_I2S_ONE_FRAME */
1174 mask = TDM_FRAME_WIDTH_MSK;
1175 tdm_val = TDM_FRAME_WIDTH(i2s_tdm->bclk_fs >> 1);
1176 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_TXCR,
1177 mask, tdm_val);
1178 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_RXCR,
1179 mask, tdm_val);
1180 }
1181 }
1182
1183 err_pm_put:
1184 pm_runtime_put(cpu_dai->dev);
1185
1186 return ret;
1187 }
1188
rockchip_i2s_tdm_clk_set_rate(struct rk_i2s_tdm_dev * i2s_tdm,struct clk * clk,unsigned long rate,int ppm)1189 static int rockchip_i2s_tdm_clk_set_rate(struct rk_i2s_tdm_dev *i2s_tdm,
1190 struct clk *clk, unsigned long rate,
1191 int ppm)
1192 {
1193 unsigned long rate_target;
1194 int delta, ret;
1195
1196 if (ppm == i2s_tdm->clk_ppm)
1197 return 0;
1198
1199 ret = rockchip_pll_clk_compensation(clk, ppm);
1200 if (ret != -ENOSYS)
1201 goto out;
1202
1203 delta = (ppm < 0) ? -1 : 1;
1204 delta *= (int)div64_u64((uint64_t)rate * (uint64_t)abs(ppm) + 500000, 1000000);
1205
1206 rate_target = rate + delta;
1207
1208 if (!rate_target)
1209 return -EINVAL;
1210
1211 ret = clk_set_rate(clk, rate_target);
1212 if (ret)
1213 return ret;
1214 out:
1215 if (!ret)
1216 i2s_tdm->clk_ppm = ppm;
1217
1218 return ret;
1219 }
1220
rockchip_i2s_tdm_calibrate_mclk(struct rk_i2s_tdm_dev * i2s_tdm,struct snd_pcm_substream * substream,unsigned int lrck_freq)1221 static int rockchip_i2s_tdm_calibrate_mclk(struct rk_i2s_tdm_dev *i2s_tdm,
1222 struct snd_pcm_substream *substream,
1223 unsigned int lrck_freq)
1224 {
1225 struct clk *mclk_root;
1226 struct clk *mclk_parent;
1227 unsigned int mclk_root_freq;
1228 unsigned int mclk_root_initial_freq;
1229 unsigned int mclk_parent_freq;
1230 unsigned int div, delta;
1231 uint64_t ppm;
1232 int ret;
1233
1234 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1235 mclk_parent = i2s_tdm->mclk_tx_src;
1236 else
1237 mclk_parent = i2s_tdm->mclk_rx_src;
1238
1239 switch (lrck_freq) {
1240 case 8000:
1241 case 16000:
1242 case 24000:
1243 case 32000:
1244 case 48000:
1245 case 64000:
1246 case 96000:
1247 case 192000:
1248 mclk_root = i2s_tdm->mclk_root0;
1249 mclk_root_freq = i2s_tdm->mclk_root0_freq;
1250 mclk_root_initial_freq = i2s_tdm->mclk_root0_initial_freq;
1251 mclk_parent_freq = DEFAULT_MCLK_FS * 192000;
1252 break;
1253 case 11025:
1254 case 22050:
1255 case 44100:
1256 case 88200:
1257 case 176400:
1258 mclk_root = i2s_tdm->mclk_root1;
1259 mclk_root_freq = i2s_tdm->mclk_root1_freq;
1260 mclk_root_initial_freq = i2s_tdm->mclk_root1_initial_freq;
1261 mclk_parent_freq = DEFAULT_MCLK_FS * 176400;
1262 break;
1263 default:
1264 dev_err(i2s_tdm->dev, "Invalid LRCK freq: %u Hz\n",
1265 lrck_freq);
1266 return -EINVAL;
1267 }
1268
1269 ret = clk_set_parent(mclk_parent, mclk_root);
1270 if (ret)
1271 goto out;
1272
1273 ret = rockchip_i2s_tdm_clk_set_rate(i2s_tdm, mclk_root,
1274 mclk_root_freq, 0);
1275 if (ret)
1276 goto out;
1277
1278 delta = abs(mclk_root_freq % mclk_parent_freq - mclk_parent_freq);
1279 ppm = div64_u64((uint64_t)delta * 1000000, (uint64_t)mclk_root_freq);
1280
1281 if (ppm) {
1282 div = DIV_ROUND_CLOSEST(mclk_root_initial_freq, mclk_parent_freq);
1283 if (!div)
1284 return -EINVAL;
1285
1286 mclk_root_freq = mclk_parent_freq * round_up(div, 2);
1287
1288 ret = clk_set_rate(mclk_root, mclk_root_freq);
1289 if (ret)
1290 goto out;
1291
1292 i2s_tdm->mclk_root0_freq = clk_get_rate(i2s_tdm->mclk_root0);
1293 i2s_tdm->mclk_root1_freq = clk_get_rate(i2s_tdm->mclk_root1);
1294 }
1295
1296 ret = clk_set_rate(mclk_parent, mclk_parent_freq);
1297 if (ret)
1298 goto out;
1299
1300 out:
1301 return ret;
1302 }
1303
rockchip_i2s_tdm_mclk_reparent(struct rk_i2s_tdm_dev * i2s_tdm)1304 static int rockchip_i2s_tdm_mclk_reparent(struct rk_i2s_tdm_dev *i2s_tdm)
1305 {
1306 struct clk *parent;
1307 int ret = 0;
1308
1309 /* reparent to the same clk on TRCM mode */
1310 switch (i2s_tdm->clk_trcm) {
1311 case I2S_CKR_TRCM_TXONLY:
1312 parent = clk_get_parent(i2s_tdm->mclk_tx);
1313 /*
1314 * API clk_has_parent is not available yet on GKI, so we
1315 * use clk_set_parent directly and ignore the ret value.
1316 * if the API has addressed on GKI, should remove it.
1317 */
1318 #ifdef CONFIG_NO_GKI
1319 if (clk_has_parent(i2s_tdm->mclk_rx, parent))
1320 ret = clk_set_parent(i2s_tdm->mclk_rx, parent);
1321 #else
1322 clk_set_parent(i2s_tdm->mclk_rx, parent);
1323 #endif
1324 break;
1325 case I2S_CKR_TRCM_RXONLY:
1326 parent = clk_get_parent(i2s_tdm->mclk_rx);
1327 #ifdef CONFIG_NO_GKI
1328 if (clk_has_parent(i2s_tdm->mclk_tx, parent))
1329 ret = clk_set_parent(i2s_tdm->mclk_tx, parent);
1330 #else
1331 clk_set_parent(i2s_tdm->mclk_tx, parent);
1332 #endif
1333 break;
1334 }
1335
1336 return ret;
1337 }
1338
rockchip_i2s_tdm_set_mclk(struct rk_i2s_tdm_dev * i2s_tdm,struct snd_pcm_substream * substream,struct clk ** mclk)1339 static int rockchip_i2s_tdm_set_mclk(struct rk_i2s_tdm_dev *i2s_tdm,
1340 struct snd_pcm_substream *substream,
1341 struct clk **mclk)
1342 {
1343 unsigned int mclk_freq;
1344 int ret;
1345
1346 if (i2s_tdm->clk_trcm) {
1347 if (i2s_tdm->mclk_tx_freq != i2s_tdm->mclk_rx_freq) {
1348 dev_err(i2s_tdm->dev,
1349 "clk_trcm, tx: %d and rx: %d should be same\n",
1350 i2s_tdm->mclk_tx_freq,
1351 i2s_tdm->mclk_rx_freq);
1352 ret = -EINVAL;
1353 goto err;
1354 }
1355
1356 ret = clk_set_rate(i2s_tdm->mclk_tx, i2s_tdm->mclk_tx_freq);
1357 if (ret)
1358 goto err;
1359
1360 ret = clk_set_rate(i2s_tdm->mclk_rx, i2s_tdm->mclk_rx_freq);
1361 if (ret)
1362 goto err;
1363
1364 ret = rockchip_i2s_tdm_mclk_reparent(i2s_tdm);
1365 if (ret)
1366 goto err;
1367
1368 /* mclk_rx is also ok. */
1369 *mclk = i2s_tdm->mclk_tx;
1370 } else {
1371 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1372 *mclk = i2s_tdm->mclk_tx;
1373 mclk_freq = i2s_tdm->mclk_tx_freq;
1374 } else {
1375 *mclk = i2s_tdm->mclk_rx;
1376 mclk_freq = i2s_tdm->mclk_rx_freq;
1377 }
1378
1379 ret = clk_set_rate(*mclk, mclk_freq);
1380 if (ret)
1381 goto err;
1382 }
1383
1384 return 0;
1385
1386 err:
1387 return ret;
1388 }
1389
rockchip_i2s_io_multiplex(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1390 static int rockchip_i2s_io_multiplex(struct snd_pcm_substream *substream,
1391 struct snd_soc_dai *dai)
1392 {
1393 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
1394 int usable_chs = MULTIPLEX_CH_MAX;
1395 unsigned int val = 0;
1396
1397 if (!i2s_tdm->io_multiplex)
1398 return 0;
1399
1400 if (IS_ERR(i2s_tdm->grf))
1401 return 0;
1402
1403 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
1404 struct snd_pcm_str *playback_str =
1405 &substream->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK];
1406
1407 if (playback_str->substream_opened) {
1408 regmap_read(i2s_tdm->regmap, I2S_TXCR, &val);
1409 val &= I2S_TXCR_CSR_MASK;
1410 usable_chs = MULTIPLEX_CH_MAX - to_ch_num(val);
1411 }
1412
1413 regmap_read(i2s_tdm->regmap, I2S_RXCR, &val);
1414 val &= I2S_RXCR_CSR_MASK;
1415
1416 if (to_ch_num(val) > usable_chs) {
1417 dev_err(i2s_tdm->dev,
1418 "Capture chs(%d) > usable chs(%d)\n",
1419 to_ch_num(val), usable_chs);
1420 return -EINVAL;
1421 }
1422
1423 switch (val) {
1424 case I2S_CHN_4:
1425 val = I2S_IO_6CH_OUT_4CH_IN;
1426 break;
1427 case I2S_CHN_6:
1428 val = I2S_IO_4CH_OUT_6CH_IN;
1429 break;
1430 case I2S_CHN_8:
1431 val = I2S_IO_2CH_OUT_8CH_IN;
1432 break;
1433 default:
1434 val = I2S_IO_8CH_OUT_2CH_IN;
1435 break;
1436 }
1437 } else {
1438 struct snd_pcm_str *capture_str =
1439 &substream->pcm->streams[SNDRV_PCM_STREAM_CAPTURE];
1440
1441 if (capture_str->substream_opened) {
1442 regmap_read(i2s_tdm->regmap, I2S_RXCR, &val);
1443 val &= I2S_RXCR_CSR_MASK;
1444 usable_chs = MULTIPLEX_CH_MAX - to_ch_num(val);
1445 }
1446
1447 regmap_read(i2s_tdm->regmap, I2S_TXCR, &val);
1448 val &= I2S_TXCR_CSR_MASK;
1449
1450 if (to_ch_num(val) > usable_chs) {
1451 dev_err(i2s_tdm->dev,
1452 "Playback chs(%d) > usable chs(%d)\n",
1453 to_ch_num(val), usable_chs);
1454 return -EINVAL;
1455 }
1456
1457 switch (val) {
1458 case I2S_CHN_4:
1459 val = I2S_IO_4CH_OUT_6CH_IN;
1460 break;
1461 case I2S_CHN_6:
1462 val = I2S_IO_6CH_OUT_4CH_IN;
1463 break;
1464 case I2S_CHN_8:
1465 val = I2S_IO_8CH_OUT_2CH_IN;
1466 break;
1467 default:
1468 val = I2S_IO_2CH_OUT_8CH_IN;
1469 break;
1470 }
1471 }
1472
1473 val <<= i2s_tdm->soc_data->grf_shift;
1474 val |= (I2S_IO_DIRECTION_MASK << i2s_tdm->soc_data->grf_shift) << 16;
1475 regmap_write(i2s_tdm->grf, i2s_tdm->soc_data->grf_reg_offset, val);
1476
1477 return 0;
1478 }
1479
is_params_dirty(struct snd_pcm_substream * substream,struct snd_soc_dai * dai,unsigned int div_bclk,unsigned int div_lrck,unsigned int fmt)1480 static bool is_params_dirty(struct snd_pcm_substream *substream,
1481 struct snd_soc_dai *dai,
1482 unsigned int div_bclk,
1483 unsigned int div_lrck,
1484 unsigned int fmt)
1485 {
1486 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
1487 unsigned int last_div_bclk, last_div_lrck, last_fmt, val;
1488
1489 regmap_read(i2s_tdm->regmap, I2S_CLKDIV, &val);
1490 last_div_bclk = ((val & I2S_CLKDIV_TXM_MASK) >> I2S_CLKDIV_TXM_SHIFT) + 1;
1491 if (last_div_bclk != div_bclk)
1492 return true;
1493
1494 regmap_read(i2s_tdm->regmap, I2S_CKR, &val);
1495 last_div_lrck = ((val & I2S_CKR_TSD_MASK) >> I2S_CKR_TSD_SHIFT) + 1;
1496 if (last_div_lrck != div_lrck)
1497 return true;
1498
1499 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1500 regmap_read(i2s_tdm->regmap, I2S_TXCR, &val);
1501 last_fmt = val & (I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK);
1502 } else {
1503 regmap_read(i2s_tdm->regmap, I2S_RXCR, &val);
1504 last_fmt = val & (I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK);
1505 }
1506 if (last_fmt != fmt)
1507 return true;
1508
1509 return false;
1510 }
1511
rockchip_i2s_tdm_params_trcm(struct snd_pcm_substream * substream,struct snd_soc_dai * dai,unsigned int div_bclk,unsigned int div_lrck,unsigned int fmt)1512 static int rockchip_i2s_tdm_params_trcm(struct snd_pcm_substream *substream,
1513 struct snd_soc_dai *dai,
1514 unsigned int div_bclk,
1515 unsigned int div_lrck,
1516 unsigned int fmt)
1517 {
1518 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
1519 unsigned long flags;
1520
1521 spin_lock_irqsave(&i2s_tdm->lock, flags);
1522 if (atomic_read(&i2s_tdm->refcount))
1523 rockchip_i2s_tdm_trcm_pause(substream, i2s_tdm);
1524
1525 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
1526 I2S_CLKDIV_TXM_MASK | I2S_CLKDIV_RXM_MASK,
1527 I2S_CLKDIV_TXM(div_bclk) | I2S_CLKDIV_RXM(div_bclk));
1528 regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
1529 I2S_CKR_TSD_MASK | I2S_CKR_RSD_MASK,
1530 I2S_CKR_TSD(div_lrck) | I2S_CKR_RSD(div_lrck));
1531
1532 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1533 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
1534 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
1535 fmt);
1536 else
1537 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
1538 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
1539 fmt);
1540
1541 if (atomic_read(&i2s_tdm->refcount))
1542 rockchip_i2s_tdm_trcm_resume(substream, i2s_tdm);
1543 spin_unlock_irqrestore(&i2s_tdm->lock, flags);
1544
1545 return 0;
1546 }
1547
rockchip_i2s_tdm_params(struct snd_pcm_substream * substream,struct snd_soc_dai * dai,unsigned int div_bclk,unsigned int div_lrck,unsigned int fmt)1548 static int rockchip_i2s_tdm_params(struct snd_pcm_substream *substream,
1549 struct snd_soc_dai *dai,
1550 unsigned int div_bclk,
1551 unsigned int div_lrck,
1552 unsigned int fmt)
1553 {
1554 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
1555 int stream = substream->stream;
1556
1557 if (is_stream_active(i2s_tdm, stream))
1558 rockchip_i2s_tdm_xfer_stop(i2s_tdm, stream, true);
1559
1560 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1561 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
1562 I2S_CLKDIV_TXM_MASK,
1563 I2S_CLKDIV_TXM(div_bclk));
1564 regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
1565 I2S_CKR_TSD_MASK,
1566 I2S_CKR_TSD(div_lrck));
1567 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
1568 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
1569 fmt);
1570 } else {
1571 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
1572 I2S_CLKDIV_RXM_MASK,
1573 I2S_CLKDIV_RXM(div_bclk));
1574 regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
1575 I2S_CKR_RSD_MASK,
1576 I2S_CKR_RSD(div_lrck));
1577 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
1578 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
1579 fmt);
1580 }
1581
1582 /*
1583 * Bring back CLK ASAP after cfg changed to make SINK devices active
1584 * on HDMI-PATH-ALWAYS-ON situation, this workaround for some TVs no
1585 * sound issue. at the moment, it's 8K@60Hz display situation.
1586 */
1587 if ((i2s_tdm->quirks & QUIRK_HDMI_PATH) &&
1588 (i2s_tdm->quirks & QUIRK_ALWAYS_ON) &&
1589 (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)) {
1590 rockchip_i2s_tdm_xfer_start(i2s_tdm, SNDRV_PCM_STREAM_PLAYBACK);
1591 }
1592
1593 return 0;
1594 }
1595
rockchip_i2s_tdm_params_channels(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1596 static int rockchip_i2s_tdm_params_channels(struct snd_pcm_substream *substream,
1597 struct snd_pcm_hw_params *params,
1598 struct snd_soc_dai *dai)
1599 {
1600 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
1601 unsigned int reg_fmt, fmt;
1602 int ret = 0;
1603
1604 #ifdef CONFIG_SND_SOC_ROCKCHIP_I2S_TDM_MULTI_LANES
1605 if (i2s_tdm->is_tdm_multi_lanes) {
1606 unsigned int lanes = rockchip_i2s_tdm_get_lanes(i2s_tdm,
1607 substream->stream);
1608
1609 switch (lanes) {
1610 case 4:
1611 ret = I2S_CHN_8;
1612 break;
1613 case 3:
1614 ret = I2S_CHN_6;
1615 break;
1616 case 2:
1617 ret = I2S_CHN_4;
1618 break;
1619 case 1:
1620 ret = I2S_CHN_2;
1621 break;
1622 default:
1623 ret = -EINVAL;
1624 break;
1625 }
1626
1627 return ret;
1628 }
1629 #endif
1630 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1631 reg_fmt = I2S_TXCR;
1632 else
1633 reg_fmt = I2S_RXCR;
1634
1635 regmap_read(i2s_tdm->regmap, reg_fmt, &fmt);
1636 fmt &= I2S_TXCR_TFS_MASK;
1637
1638 if (fmt == I2S_TXCR_TFS_TDM_I2S && !i2s_tdm->tdm_fsync_half_frame) {
1639 switch (params_channels(params)) {
1640 case 16:
1641 ret = I2S_CHN_8;
1642 break;
1643 case 12:
1644 ret = I2S_CHN_6;
1645 break;
1646 case 8:
1647 ret = I2S_CHN_4;
1648 break;
1649 case 4:
1650 ret = I2S_CHN_2;
1651 break;
1652 default:
1653 ret = -EINVAL;
1654 break;
1655 }
1656 } else {
1657 switch (params_channels(params)) {
1658 case 8:
1659 ret = I2S_CHN_8;
1660 break;
1661 case 6:
1662 ret = I2S_CHN_6;
1663 break;
1664 case 4:
1665 ret = I2S_CHN_4;
1666 break;
1667 case 2:
1668 ret = I2S_CHN_2;
1669 break;
1670 default:
1671 ret = -EINVAL;
1672 break;
1673 }
1674 }
1675
1676 return ret;
1677 }
1678
rockchip_i2s_tdm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1679 static int rockchip_i2s_tdm_hw_params(struct snd_pcm_substream *substream,
1680 struct snd_pcm_hw_params *params,
1681 struct snd_soc_dai *dai)
1682 {
1683 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
1684 struct snd_dmaengine_dai_dma_data *dma_data;
1685 struct clk *mclk;
1686 int ret = 0;
1687 unsigned int val = 0;
1688 unsigned int mclk_rate, bclk_rate, lrck_rate, div_bclk = 4, div_lrck = 64;
1689
1690 #ifdef CONFIG_SND_SOC_ROCKCHIP_I2S_TDM_MULTI_LANES
1691 if (i2s_tdm->is_tdm_multi_lanes)
1692 rockchip_i2s_tdm_multi_lanes_set_clk(substream, params, dai);
1693 #endif
1694 dma_data = snd_soc_dai_get_dma_data(dai, substream);
1695 dma_data->maxburst = MAXBURST_PER_FIFO * params_channels(params) / 2;
1696
1697 if (i2s_tdm->mclk_calibrate)
1698 rockchip_i2s_tdm_calibrate_mclk(i2s_tdm, substream,
1699 params_rate(params));
1700
1701 ret = rockchip_i2s_tdm_set_mclk(i2s_tdm, substream, &mclk);
1702 if (ret)
1703 goto err;
1704
1705 mclk_rate = clk_get_rate(mclk);
1706 lrck_rate = params_rate(params) * i2s_tdm->lrck_ratio;
1707 bclk_rate = i2s_tdm->bclk_fs * lrck_rate;
1708 if (!bclk_rate) {
1709 ret = -EINVAL;
1710 goto err;
1711 }
1712 div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
1713 div_lrck = bclk_rate / lrck_rate;
1714
1715 switch (params_format(params)) {
1716 case SNDRV_PCM_FORMAT_S8:
1717 val |= I2S_TXCR_VDW(8);
1718 break;
1719 case SNDRV_PCM_FORMAT_S16_LE:
1720 val |= I2S_TXCR_VDW(16);
1721 break;
1722 case SNDRV_PCM_FORMAT_S20_3LE:
1723 val |= I2S_TXCR_VDW(20);
1724 break;
1725 case SNDRV_PCM_FORMAT_S24_LE:
1726 val |= I2S_TXCR_VDW(24);
1727 break;
1728 case SNDRV_PCM_FORMAT_S32_LE:
1729 case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE:
1730 val |= I2S_TXCR_VDW(32);
1731 break;
1732 default:
1733 ret = -EINVAL;
1734 goto err;
1735 }
1736
1737 ret = rockchip_i2s_tdm_params_channels(substream, params, dai);
1738 if (ret < 0)
1739 goto err;
1740
1741 val |= ret;
1742 if (!is_params_dirty(substream, dai, div_bclk, div_lrck, val))
1743 return 0;
1744
1745 if (i2s_tdm->clk_trcm)
1746 rockchip_i2s_tdm_params_trcm(substream, dai, div_bclk, div_lrck, val);
1747 else
1748 rockchip_i2s_tdm_params(substream, dai, div_bclk, div_lrck, val);
1749
1750 ret = rockchip_i2s_io_multiplex(substream, dai);
1751
1752 err:
1753 return ret;
1754 }
1755
rockchip_i2s_tdm_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)1756 static int rockchip_i2s_tdm_trigger(struct snd_pcm_substream *substream,
1757 int cmd, struct snd_soc_dai *dai)
1758 {
1759 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
1760 int ret = 0;
1761
1762 switch (cmd) {
1763 case SNDRV_PCM_TRIGGER_START:
1764 case SNDRV_PCM_TRIGGER_RESUME:
1765 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1766 rockchip_i2s_tdm_start(i2s_tdm, substream->stream);
1767 break;
1768 case SNDRV_PCM_TRIGGER_SUSPEND:
1769 case SNDRV_PCM_TRIGGER_STOP:
1770 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1771 rockchip_i2s_tdm_stop(i2s_tdm, substream->stream);
1772 break;
1773 default:
1774 ret = -EINVAL;
1775 break;
1776 }
1777
1778 return ret;
1779 }
1780
rockchip_i2s_tdm_set_sysclk(struct snd_soc_dai * cpu_dai,int stream,unsigned int freq,int dir)1781 static int rockchip_i2s_tdm_set_sysclk(struct snd_soc_dai *cpu_dai, int stream,
1782 unsigned int freq, int dir)
1783 {
1784 struct rk_i2s_tdm_dev *i2s_tdm = to_info(cpu_dai);
1785
1786 /* Put set mclk rate into rockchip_i2s_tdm_set_mclk() */
1787 if (i2s_tdm->clk_trcm) {
1788 i2s_tdm->mclk_tx_freq = freq;
1789 i2s_tdm->mclk_rx_freq = freq;
1790 } else {
1791 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
1792 i2s_tdm->mclk_tx_freq = freq;
1793 else
1794 i2s_tdm->mclk_rx_freq = freq;
1795 }
1796
1797 dev_dbg(i2s_tdm->dev, "The target mclk_%s freq is: %d\n",
1798 stream ? "rx" : "tx", freq);
1799
1800 return 0;
1801 }
1802
rockchip_i2s_tdm_clk_compensation_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1803 static int rockchip_i2s_tdm_clk_compensation_info(struct snd_kcontrol *kcontrol,
1804 struct snd_ctl_elem_info *uinfo)
1805 {
1806 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1807 uinfo->count = 1;
1808 uinfo->value.integer.min = CLK_PPM_MIN;
1809 uinfo->value.integer.max = CLK_PPM_MAX;
1810 uinfo->value.integer.step = 1;
1811
1812 return 0;
1813 }
1814
rockchip_i2s_tdm_clk_compensation_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1815 static int rockchip_i2s_tdm_clk_compensation_get(struct snd_kcontrol *kcontrol,
1816 struct snd_ctl_elem_value *ucontrol)
1817 {
1818 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
1819 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1820
1821 ucontrol->value.integer.value[0] = i2s_tdm->clk_ppm;
1822
1823 return 0;
1824 }
1825
rockchip_i2s_tdm_clk_compensation_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1826 static int rockchip_i2s_tdm_clk_compensation_put(struct snd_kcontrol *kcontrol,
1827 struct snd_ctl_elem_value *ucontrol)
1828 {
1829 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
1830 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1831 int ret = 0, ppm = 0;
1832
1833 if ((ucontrol->value.integer.value[0] < CLK_PPM_MIN) ||
1834 (ucontrol->value.integer.value[0] > CLK_PPM_MAX))
1835 return -EINVAL;
1836
1837 ppm = ucontrol->value.integer.value[0];
1838
1839 ret = rockchip_i2s_tdm_clk_set_rate(i2s_tdm, i2s_tdm->mclk_root0,
1840 i2s_tdm->mclk_root0_freq, ppm);
1841 if (ret)
1842 return ret;
1843
1844 if (clk_is_match(i2s_tdm->mclk_root0, i2s_tdm->mclk_root1))
1845 return 0;
1846
1847 ret = rockchip_i2s_tdm_clk_set_rate(i2s_tdm, i2s_tdm->mclk_root1,
1848 i2s_tdm->mclk_root1_freq, ppm);
1849
1850 return ret;
1851 }
1852
1853 static struct snd_kcontrol_new rockchip_i2s_tdm_compensation_control = {
1854 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1855 .name = "PCM Clk Compensation In PPM",
1856 .info = rockchip_i2s_tdm_clk_compensation_info,
1857 .get = rockchip_i2s_tdm_clk_compensation_get,
1858 .put = rockchip_i2s_tdm_clk_compensation_put,
1859 };
1860
1861 /* loopback mode select */
1862 enum {
1863 LOOPBACK_MODE_DIS = 0,
1864 LOOPBACK_MODE_1,
1865 LOOPBACK_MODE_2,
1866 LOOPBACK_MODE_2_SWAP,
1867 };
1868
1869 static const char *const loopback_text[] = {
1870 "Disabled",
1871 "Mode1",
1872 "Mode2",
1873 "Mode2 Swap",
1874 };
1875
1876 static SOC_ENUM_SINGLE_EXT_DECL(loopback_mode, loopback_text);
1877
rockchip_i2s_tdm_loopback_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1878 static int rockchip_i2s_tdm_loopback_get(struct snd_kcontrol *kcontrol,
1879 struct snd_ctl_elem_value *ucontrol)
1880 {
1881 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1882 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_component_get_drvdata(component);
1883 unsigned int reg = 0, mode = 0;
1884
1885 pm_runtime_get_sync(component->dev);
1886 regmap_read(i2s_tdm->regmap, I2S_XFER, ®);
1887 pm_runtime_put(component->dev);
1888
1889 switch (reg & I2S_XFER_LP_MODE_MASK) {
1890 case I2S_XFER_LP_MODE_2_SWAP:
1891 mode = LOOPBACK_MODE_2_SWAP;
1892 break;
1893 case I2S_XFER_LP_MODE_2:
1894 mode = LOOPBACK_MODE_2;
1895 break;
1896 case I2S_XFER_LP_MODE_1:
1897 mode = LOOPBACK_MODE_1;
1898 break;
1899 default:
1900 mode = LOOPBACK_MODE_DIS;
1901 break;
1902 }
1903
1904 ucontrol->value.enumerated.item[0] = mode;
1905
1906 return 0;
1907 }
1908
rockchip_i2s_tdm_loopback_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1909 static int rockchip_i2s_tdm_loopback_put(struct snd_kcontrol *kcontrol,
1910 struct snd_ctl_elem_value *ucontrol)
1911 {
1912 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1913 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_component_get_drvdata(component);
1914 unsigned int val = 0, mode = ucontrol->value.enumerated.item[0];
1915
1916 if (mode < LOOPBACK_MODE_DIS ||
1917 mode > LOOPBACK_MODE_2_SWAP)
1918 return -EINVAL;
1919
1920 switch (mode) {
1921 case LOOPBACK_MODE_2_SWAP:
1922 val = I2S_XFER_LP_MODE_2_SWAP;
1923 break;
1924 case LOOPBACK_MODE_2:
1925 val = I2S_XFER_LP_MODE_2;
1926 break;
1927 case LOOPBACK_MODE_1:
1928 val = I2S_XFER_LP_MODE_1;
1929 break;
1930 default:
1931 val = I2S_XFER_LP_MODE_DIS;
1932 break;
1933 }
1934
1935 pm_runtime_get_sync(component->dev);
1936 regmap_update_bits(i2s_tdm->regmap, I2S_XFER, I2S_XFER_LP_MODE_MASK, val);
1937 pm_runtime_put(component->dev);
1938
1939 return 0;
1940 }
1941
1942 static const struct snd_kcontrol_new rockchip_i2s_tdm_snd_controls[] = {
1943 SOC_ENUM_EXT("I2STDM Digital Loopback Mode", loopback_mode,
1944 rockchip_i2s_tdm_loopback_get,
1945 rockchip_i2s_tdm_loopback_put),
1946 #ifdef CONFIG_SND_SOC_ROCKCHIP_I2S_TDM_MULTI_LANES
1947 SOC_ENUM_EXT("Transmit SDOx Select", tx_lanes_enum,
1948 rockchip_i2s_tdm_tx_lanes_get, rockchip_i2s_tdm_tx_lanes_put),
1949 SOC_ENUM_EXT("Receive SDIx Select", rx_lanes_enum,
1950 rockchip_i2s_tdm_rx_lanes_get, rockchip_i2s_tdm_rx_lanes_put),
1951 #endif
1952 };
1953
rockchip_i2s_tdm_dai_probe(struct snd_soc_dai * dai)1954 static int rockchip_i2s_tdm_dai_probe(struct snd_soc_dai *dai)
1955 {
1956 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1957
1958 dai->capture_dma_data = &i2s_tdm->capture_dma_data;
1959 dai->playback_dma_data = &i2s_tdm->playback_dma_data;
1960
1961 if (i2s_tdm->mclk_calibrate)
1962 snd_soc_add_dai_controls(dai, &rockchip_i2s_tdm_compensation_control, 1);
1963
1964 return 0;
1965 }
1966
rockchip_dai_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)1967 static int rockchip_dai_tdm_slot(struct snd_soc_dai *dai,
1968 unsigned int tx_mask, unsigned int rx_mask,
1969 int slots, int slot_width)
1970 {
1971 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1972 unsigned int mask, val;
1973
1974 i2s_tdm->tdm_mode = true;
1975 i2s_tdm->bclk_fs = slots * slot_width;
1976 mask = TDM_SLOT_BIT_WIDTH_MSK | TDM_FRAME_WIDTH_MSK;
1977 val = TDM_SLOT_BIT_WIDTH(slot_width) |
1978 TDM_FRAME_WIDTH(slots * slot_width);
1979 pm_runtime_get_sync(dai->dev);
1980 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_TXCR,
1981 mask, val);
1982 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_RXCR,
1983 mask, val);
1984 pm_runtime_put(dai->dev);
1985
1986 return 0;
1987 }
1988
rockchip_i2s_tdm_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1989 static int rockchip_i2s_tdm_startup(struct snd_pcm_substream *substream,
1990 struct snd_soc_dai *dai)
1991 {
1992 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1993
1994 if (i2s_tdm->substreams[substream->stream])
1995 return -EBUSY;
1996
1997 i2s_tdm->substreams[substream->stream] = substream;
1998
1999 return 0;
2000 }
2001
rockchip_i2s_tdm_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)2002 static void rockchip_i2s_tdm_shutdown(struct snd_pcm_substream *substream,
2003 struct snd_soc_dai *dai)
2004 {
2005 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
2006
2007 i2s_tdm->substreams[substream->stream] = NULL;
2008 }
2009
2010 static const struct snd_soc_dai_ops rockchip_i2s_tdm_dai_ops = {
2011 .startup = rockchip_i2s_tdm_startup,
2012 .shutdown = rockchip_i2s_tdm_shutdown,
2013 .hw_params = rockchip_i2s_tdm_hw_params,
2014 .set_sysclk = rockchip_i2s_tdm_set_sysclk,
2015 .set_fmt = rockchip_i2s_tdm_set_fmt,
2016 .set_tdm_slot = rockchip_dai_tdm_slot,
2017 .trigger = rockchip_i2s_tdm_trigger,
2018 };
2019
2020 static const struct snd_soc_component_driver rockchip_i2s_tdm_component = {
2021 .name = DRV_NAME,
2022 .controls = rockchip_i2s_tdm_snd_controls,
2023 .num_controls = ARRAY_SIZE(rockchip_i2s_tdm_snd_controls),
2024 };
2025
rockchip_i2s_tdm_wr_reg(struct device * dev,unsigned int reg)2026 static bool rockchip_i2s_tdm_wr_reg(struct device *dev, unsigned int reg)
2027 {
2028 switch (reg) {
2029 case I2S_TXCR:
2030 case I2S_RXCR:
2031 case I2S_CKR:
2032 case I2S_DMACR:
2033 case I2S_INTCR:
2034 case I2S_XFER:
2035 case I2S_CLR:
2036 case I2S_TXDR:
2037 case I2S_TDM_TXCR:
2038 case I2S_TDM_RXCR:
2039 case I2S_CLKDIV:
2040 return true;
2041 default:
2042 return false;
2043 }
2044 }
2045
rockchip_i2s_tdm_rd_reg(struct device * dev,unsigned int reg)2046 static bool rockchip_i2s_tdm_rd_reg(struct device *dev, unsigned int reg)
2047 {
2048 switch (reg) {
2049 case I2S_TXCR:
2050 case I2S_RXCR:
2051 case I2S_CKR:
2052 case I2S_DMACR:
2053 case I2S_INTCR:
2054 case I2S_XFER:
2055 case I2S_CLR:
2056 case I2S_TXDR:
2057 case I2S_RXDR:
2058 case I2S_TXFIFOLR:
2059 case I2S_INTSR:
2060 case I2S_RXFIFOLR:
2061 case I2S_TDM_TXCR:
2062 case I2S_TDM_RXCR:
2063 case I2S_CLKDIV:
2064 return true;
2065 default:
2066 return false;
2067 }
2068 }
2069
rockchip_i2s_tdm_volatile_reg(struct device * dev,unsigned int reg)2070 static bool rockchip_i2s_tdm_volatile_reg(struct device *dev, unsigned int reg)
2071 {
2072 switch (reg) {
2073 case I2S_TXFIFOLR:
2074 case I2S_INTCR:
2075 case I2S_INTSR:
2076 case I2S_CLR:
2077 case I2S_TXDR:
2078 case I2S_RXDR:
2079 case I2S_RXFIFOLR:
2080 return true;
2081 default:
2082 return false;
2083 }
2084 }
2085
rockchip_i2s_tdm_precious_reg(struct device * dev,unsigned int reg)2086 static bool rockchip_i2s_tdm_precious_reg(struct device *dev, unsigned int reg)
2087 {
2088 switch (reg) {
2089 case I2S_RXDR:
2090 return true;
2091 default:
2092 return false;
2093 }
2094 }
2095
2096 static const struct reg_default rockchip_i2s_tdm_reg_defaults[] = {
2097 {0x00, 0x7200000f},
2098 {0x04, 0x01c8000f},
2099 {0x08, 0x00001f1f},
2100 {0x10, 0x001f0000},
2101 {0x14, 0x01f00000},
2102 {0x30, 0x00003eff},
2103 {0x34, 0x00003eff},
2104 {0x38, 0x00000707},
2105 };
2106
2107 static const struct regmap_config rockchip_i2s_tdm_regmap_config = {
2108 .reg_bits = 32,
2109 .reg_stride = 4,
2110 .val_bits = 32,
2111 .max_register = I2S_CLKDIV,
2112 .reg_defaults = rockchip_i2s_tdm_reg_defaults,
2113 .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_tdm_reg_defaults),
2114 .writeable_reg = rockchip_i2s_tdm_wr_reg,
2115 .readable_reg = rockchip_i2s_tdm_rd_reg,
2116 .volatile_reg = rockchip_i2s_tdm_volatile_reg,
2117 .precious_reg = rockchip_i2s_tdm_precious_reg,
2118 .cache_type = REGCACHE_FLAT,
2119 };
2120
common_soc_init(struct device * dev,u32 addr)2121 static int common_soc_init(struct device *dev, u32 addr)
2122 {
2123 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
2124 const struct txrx_config *configs = i2s_tdm->soc_data->configs;
2125 u32 reg = 0, val = 0, trcm = i2s_tdm->clk_trcm;
2126 int i;
2127
2128 if (IS_ERR(i2s_tdm->grf))
2129 return 0;
2130
2131 switch (trcm) {
2132 case I2S_CKR_TRCM_TXONLY:
2133 case I2S_CKR_TRCM_RXONLY:
2134 break;
2135 default:
2136 return 0;
2137 }
2138
2139 for (i = 0; i < i2s_tdm->soc_data->config_count; i++) {
2140 if (addr != configs[i].addr)
2141 continue;
2142 reg = configs[i].reg;
2143 if (trcm == I2S_CKR_TRCM_TXONLY)
2144 val = configs[i].txonly;
2145 else
2146 val = configs[i].rxonly;
2147
2148 if (reg)
2149 regmap_write(i2s_tdm->grf, reg, val);
2150 }
2151
2152 return 0;
2153 }
2154
2155 static const struct txrx_config px30_txrx_config[] = {
2156 { 0xff060000, 0x184, PX30_I2S0_CLK_TXONLY, PX30_I2S0_CLK_RXONLY },
2157 };
2158
2159 static const struct txrx_config rk1808_txrx_config[] = {
2160 { 0xff7e0000, 0x190, RK1808_I2S0_CLK_TXONLY, RK1808_I2S0_CLK_RXONLY },
2161 };
2162
2163 static const struct txrx_config rk3308_txrx_config[] = {
2164 { 0xff300000, 0x308, RK3308_I2S0_CLK_TXONLY, RK3308_I2S0_CLK_RXONLY },
2165 { 0xff310000, 0x308, RK3308_I2S1_CLK_TXONLY, RK3308_I2S1_CLK_RXONLY },
2166 };
2167
2168 static const struct txrx_config rk3568_txrx_config[] = {
2169 { 0xfe410000, 0x504, RK3568_I2S1_CLK_TXONLY, RK3568_I2S1_CLK_RXONLY },
2170 { 0xfe430000, 0x504, RK3568_I2S3_CLK_TXONLY, RK3568_I2S3_CLK_RXONLY },
2171 { 0xfe430000, 0x508, RK3568_I2S3_MCLK_TXONLY, RK3568_I2S3_MCLK_RXONLY },
2172 };
2173
2174 static const struct txrx_config rv1126_txrx_config[] = {
2175 { 0xff800000, 0x10260, RV1126_I2S0_CLK_TXONLY, RV1126_I2S0_CLK_RXONLY },
2176 };
2177
2178 static const struct rk_i2s_soc_data px30_i2s_soc_data = {
2179 .softrst_offset = 0x0300,
2180 .configs = px30_txrx_config,
2181 .config_count = ARRAY_SIZE(px30_txrx_config),
2182 .init = common_soc_init,
2183 };
2184
2185 static const struct rk_i2s_soc_data rk1808_i2s_soc_data = {
2186 .softrst_offset = 0x0300,
2187 .configs = rk1808_txrx_config,
2188 .config_count = ARRAY_SIZE(rk1808_txrx_config),
2189 .init = common_soc_init,
2190 };
2191
2192 static const struct rk_i2s_soc_data rk3308_i2s_soc_data = {
2193 .softrst_offset = 0x0400,
2194 .grf_reg_offset = 0x0308,
2195 .grf_shift = 5,
2196 .configs = rk3308_txrx_config,
2197 .config_count = ARRAY_SIZE(rk3308_txrx_config),
2198 .init = common_soc_init,
2199 };
2200
2201 static const struct rk_i2s_soc_data rk3568_i2s_soc_data = {
2202 .softrst_offset = 0x0400,
2203 .configs = rk3568_txrx_config,
2204 .config_count = ARRAY_SIZE(rk3568_txrx_config),
2205 .init = common_soc_init,
2206 };
2207
2208 static const struct rk_i2s_soc_data rv1126_i2s_soc_data = {
2209 .softrst_offset = 0x0300,
2210 .configs = rv1126_txrx_config,
2211 .config_count = ARRAY_SIZE(rv1126_txrx_config),
2212 .init = common_soc_init,
2213 };
2214
2215 static const struct of_device_id rockchip_i2s_tdm_match[] = {
2216 #ifdef CONFIG_CPU_PX30
2217 { .compatible = "rockchip,px30-i2s-tdm", .data = &px30_i2s_soc_data },
2218 #endif
2219 #ifdef CONFIG_CPU_RK1808
2220 { .compatible = "rockchip,rk1808-i2s-tdm", .data = &rk1808_i2s_soc_data },
2221 #endif
2222 #ifdef CONFIG_CPU_RK3308
2223 { .compatible = "rockchip,rk3308-i2s-tdm", .data = &rk3308_i2s_soc_data },
2224 #endif
2225 #ifdef CONFIG_CPU_RK3568
2226 { .compatible = "rockchip,rk3568-i2s-tdm", .data = &rk3568_i2s_soc_data },
2227 #endif
2228 #ifdef CONFIG_CPU_RK3588
2229 { .compatible = "rockchip,rk3588-i2s-tdm", },
2230 #endif
2231 #ifdef CONFIG_CPU_RV1106
2232 { .compatible = "rockchip,rv1106-i2s-tdm", },
2233 #endif
2234 #ifdef CONFIG_CPU_RV1126
2235 { .compatible = "rockchip,rv1126-i2s-tdm", .data = &rv1126_i2s_soc_data },
2236 #endif
2237 {},
2238 };
2239
2240 #ifdef HAVE_SYNC_RESET
of_i2s_resetid_get(struct device_node * node,const char * id)2241 static int of_i2s_resetid_get(struct device_node *node,
2242 const char *id)
2243 {
2244 struct of_phandle_args args;
2245 int index = 0;
2246 int ret;
2247
2248 if (id)
2249 index = of_property_match_string(node,
2250 "reset-names", id);
2251 ret = of_parse_phandle_with_args(node, "resets", "#reset-cells",
2252 index, &args);
2253 if (ret)
2254 return ret;
2255
2256 return args.args[0];
2257 }
2258 #endif
2259
rockchip_i2s_tdm_dai_prepare(struct platform_device * pdev,struct snd_soc_dai_driver ** soc_dai)2260 static int rockchip_i2s_tdm_dai_prepare(struct platform_device *pdev,
2261 struct snd_soc_dai_driver **soc_dai)
2262 {
2263 struct snd_soc_dai_driver rockchip_i2s_tdm_dai = {
2264 .probe = rockchip_i2s_tdm_dai_probe,
2265 .playback = {
2266 .stream_name = "Playback",
2267 .channels_min = 2,
2268 .channels_max = 64,
2269 .rates = SNDRV_PCM_RATE_8000_192000,
2270 .formats = (SNDRV_PCM_FMTBIT_S8 |
2271 SNDRV_PCM_FMTBIT_S16_LE |
2272 SNDRV_PCM_FMTBIT_S20_3LE |
2273 SNDRV_PCM_FMTBIT_S24_LE |
2274 SNDRV_PCM_FMTBIT_S32_LE |
2275 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE),
2276 },
2277 .capture = {
2278 .stream_name = "Capture",
2279 .channels_min = 2,
2280 .channels_max = 64,
2281 .rates = SNDRV_PCM_RATE_8000_192000,
2282 .formats = (SNDRV_PCM_FMTBIT_S8 |
2283 SNDRV_PCM_FMTBIT_S16_LE |
2284 SNDRV_PCM_FMTBIT_S20_3LE |
2285 SNDRV_PCM_FMTBIT_S24_LE |
2286 SNDRV_PCM_FMTBIT_S32_LE |
2287 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE),
2288 },
2289 .ops = &rockchip_i2s_tdm_dai_ops,
2290 };
2291
2292 *soc_dai = devm_kmemdup(&pdev->dev, &rockchip_i2s_tdm_dai,
2293 sizeof(rockchip_i2s_tdm_dai), GFP_KERNEL);
2294 if (!(*soc_dai))
2295 return -ENOMEM;
2296
2297 return 0;
2298 }
2299
rockchip_i2s_tdm_path_check(struct rk_i2s_tdm_dev * i2s_tdm,int num,bool is_rx_path)2300 static int rockchip_i2s_tdm_path_check(struct rk_i2s_tdm_dev *i2s_tdm,
2301 int num,
2302 bool is_rx_path)
2303 {
2304 unsigned int *i2s_data;
2305 int i, j, ret = 0;
2306
2307 if (is_rx_path)
2308 i2s_data = i2s_tdm->i2s_sdis;
2309 else
2310 i2s_data = i2s_tdm->i2s_sdos;
2311
2312 for (i = 0; i < num; i++) {
2313 if (i2s_data[i] > CH_GRP_MAX - 1) {
2314 dev_err(i2s_tdm->dev,
2315 "%s path i2s_data[%d]: %d is overflow, max is: %d\n",
2316 is_rx_path ? "RX" : "TX",
2317 i, i2s_data[i], CH_GRP_MAX);
2318 ret = -EINVAL;
2319 goto err;
2320 }
2321
2322 for (j = 0; j < num; j++) {
2323 if (i == j)
2324 continue;
2325
2326 if (i2s_data[i] == i2s_data[j]) {
2327 dev_err(i2s_tdm->dev,
2328 "%s path invalid routed i2s_data: [%d]%d == [%d]%d\n",
2329 is_rx_path ? "RX" : "TX",
2330 i, i2s_data[i],
2331 j, i2s_data[j]);
2332 ret = -EINVAL;
2333 goto err;
2334 }
2335 }
2336 }
2337
2338 err:
2339 return ret;
2340 }
2341
rockchip_i2s_tdm_tx_path_config(struct rk_i2s_tdm_dev * i2s_tdm,int num)2342 static void rockchip_i2s_tdm_tx_path_config(struct rk_i2s_tdm_dev *i2s_tdm,
2343 int num)
2344 {
2345 int idx;
2346
2347 for (idx = 0; idx < num; idx++) {
2348 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
2349 I2S_TXCR_PATH_MASK(idx),
2350 I2S_TXCR_PATH(idx, i2s_tdm->i2s_sdos[idx]));
2351 }
2352 }
2353
rockchip_i2s_tdm_rx_path_config(struct rk_i2s_tdm_dev * i2s_tdm,int num)2354 static void rockchip_i2s_tdm_rx_path_config(struct rk_i2s_tdm_dev *i2s_tdm,
2355 int num)
2356 {
2357 int idx;
2358
2359 for (idx = 0; idx < num; idx++) {
2360 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
2361 I2S_RXCR_PATH_MASK(idx),
2362 I2S_RXCR_PATH(idx, i2s_tdm->i2s_sdis[idx]));
2363 }
2364 }
2365
rockchip_i2s_tdm_path_config(struct rk_i2s_tdm_dev * i2s_tdm,int num,bool is_rx_path)2366 static void rockchip_i2s_tdm_path_config(struct rk_i2s_tdm_dev *i2s_tdm,
2367 int num, bool is_rx_path)
2368 {
2369 if (is_rx_path)
2370 rockchip_i2s_tdm_rx_path_config(i2s_tdm, num);
2371 else
2372 rockchip_i2s_tdm_tx_path_config(i2s_tdm, num);
2373 }
2374
rockchip_i2s_tdm_path_prepare(struct rk_i2s_tdm_dev * i2s_tdm,struct device_node * np,bool is_rx_path)2375 static int rockchip_i2s_tdm_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm,
2376 struct device_node *np,
2377 bool is_rx_path)
2378 {
2379 char *i2s_tx_path_prop = "rockchip,i2s-tx-route";
2380 char *i2s_rx_path_prop = "rockchip,i2s-rx-route";
2381 char *i2s_path_prop;
2382 unsigned int *i2s_data;
2383 int num, ret = 0;
2384
2385 if (is_rx_path) {
2386 i2s_path_prop = i2s_rx_path_prop;
2387 i2s_data = i2s_tdm->i2s_sdis;
2388 } else {
2389 i2s_path_prop = i2s_tx_path_prop;
2390 i2s_data = i2s_tdm->i2s_sdos;
2391 }
2392
2393 num = of_count_phandle_with_args(np, i2s_path_prop, NULL);
2394 if (num < 0) {
2395 if (num != -ENOENT) {
2396 dev_err(i2s_tdm->dev,
2397 "Failed to read '%s' num: %d\n",
2398 i2s_path_prop, num);
2399 ret = num;
2400 }
2401 goto out;
2402 } else if (num != CH_GRP_MAX) {
2403 dev_err(i2s_tdm->dev,
2404 "The num: %d should be: %d\n", num, CH_GRP_MAX);
2405 ret = -EINVAL;
2406 goto out;
2407 }
2408
2409 ret = of_property_read_u32_array(np, i2s_path_prop,
2410 i2s_data, num);
2411 if (ret < 0) {
2412 dev_err(i2s_tdm->dev,
2413 "Failed to read '%s': %d\n",
2414 i2s_path_prop, ret);
2415 goto out;
2416 }
2417
2418 ret = rockchip_i2s_tdm_path_check(i2s_tdm, num, is_rx_path);
2419 if (ret < 0) {
2420 dev_err(i2s_tdm->dev,
2421 "Failed to check i2s data bus: %d\n", ret);
2422 goto out;
2423 }
2424
2425 rockchip_i2s_tdm_path_config(i2s_tdm, num, is_rx_path);
2426
2427 out:
2428 return ret;
2429 }
2430
rockchip_i2s_tdm_tx_path_prepare(struct rk_i2s_tdm_dev * i2s_tdm,struct device_node * np)2431 static int rockchip_i2s_tdm_tx_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm,
2432 struct device_node *np)
2433 {
2434 return rockchip_i2s_tdm_path_prepare(i2s_tdm, np, 0);
2435 }
2436
rockchip_i2s_tdm_rx_path_prepare(struct rk_i2s_tdm_dev * i2s_tdm,struct device_node * np)2437 static int rockchip_i2s_tdm_rx_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm,
2438 struct device_node *np)
2439 {
2440 return rockchip_i2s_tdm_path_prepare(i2s_tdm, np, 1);
2441 }
2442
rockchip_i2s_tdm_get_fifo_count(struct device * dev,int stream)2443 static int rockchip_i2s_tdm_get_fifo_count(struct device *dev, int stream)
2444 {
2445 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
2446 int val = 0;
2447
2448 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2449 regmap_read(i2s_tdm->regmap, I2S_TXFIFOLR, &val);
2450 else
2451 regmap_read(i2s_tdm->regmap, I2S_RXFIFOLR, &val);
2452
2453 val = ((val & I2S_FIFOLR_TFL3_MASK) >> I2S_FIFOLR_TFL3_SHIFT) +
2454 ((val & I2S_FIFOLR_TFL2_MASK) >> I2S_FIFOLR_TFL2_SHIFT) +
2455 ((val & I2S_FIFOLR_TFL1_MASK) >> I2S_FIFOLR_TFL1_SHIFT) +
2456 ((val & I2S_FIFOLR_TFL0_MASK) >> I2S_FIFOLR_TFL0_SHIFT);
2457
2458 return val;
2459 }
2460
2461 static const struct snd_dlp_config dconfig = {
2462 .get_fifo_count = rockchip_i2s_tdm_get_fifo_count,
2463 };
2464
rockchip_i2s_tdm_isr(int irq,void * devid)2465 static irqreturn_t rockchip_i2s_tdm_isr(int irq, void *devid)
2466 {
2467 struct rk_i2s_tdm_dev *i2s_tdm = (struct rk_i2s_tdm_dev *)devid;
2468 struct snd_pcm_substream *substream;
2469 u32 val;
2470
2471 regmap_read(i2s_tdm->regmap, I2S_INTSR, &val);
2472 if (val & I2S_INTSR_TXUI_ACT) {
2473 dev_warn_ratelimited(i2s_tdm->dev, "TX FIFO Underrun\n");
2474 regmap_update_bits(i2s_tdm->regmap, I2S_INTCR,
2475 I2S_INTCR_TXUIC, I2S_INTCR_TXUIC);
2476 regmap_update_bits(i2s_tdm->regmap, I2S_INTCR,
2477 I2S_INTCR_TXUIE_MASK,
2478 I2S_INTCR_TXUIE(0));
2479 substream = i2s_tdm->substreams[SNDRV_PCM_STREAM_PLAYBACK];
2480 if (substream)
2481 snd_pcm_stop_xrun(substream);
2482 }
2483
2484 if (val & I2S_INTSR_RXOI_ACT) {
2485 dev_warn_ratelimited(i2s_tdm->dev, "RX FIFO Overrun\n");
2486 regmap_update_bits(i2s_tdm->regmap, I2S_INTCR,
2487 I2S_INTCR_RXOIC, I2S_INTCR_RXOIC);
2488 regmap_update_bits(i2s_tdm->regmap, I2S_INTCR,
2489 I2S_INTCR_RXOIE_MASK,
2490 I2S_INTCR_RXOIE(0));
2491 substream = i2s_tdm->substreams[SNDRV_PCM_STREAM_CAPTURE];
2492 if (substream)
2493 snd_pcm_stop_xrun(substream);
2494 }
2495
2496 return IRQ_HANDLED;
2497 }
2498
rockchip_i2s_tdm_keep_clk_always_on(struct rk_i2s_tdm_dev * i2s_tdm)2499 static int rockchip_i2s_tdm_keep_clk_always_on(struct rk_i2s_tdm_dev *i2s_tdm)
2500 {
2501 unsigned int mclk_rate = DEFAULT_FS * DEFAULT_MCLK_FS;
2502 unsigned int bclk_rate = i2s_tdm->bclk_fs * DEFAULT_FS;
2503 unsigned int div_lrck = i2s_tdm->bclk_fs;
2504 unsigned int div_bclk;
2505 int ret;
2506
2507 div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
2508
2509 /* assign generic freq */
2510 clk_set_rate(i2s_tdm->mclk_rx, mclk_rate);
2511 clk_set_rate(i2s_tdm->mclk_tx, mclk_rate);
2512
2513 ret = rockchip_i2s_tdm_mclk_reparent(i2s_tdm);
2514 if (ret)
2515 return ret;
2516
2517 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
2518 I2S_CLKDIV_RXM_MASK | I2S_CLKDIV_TXM_MASK,
2519 I2S_CLKDIV_RXM(div_bclk) | I2S_CLKDIV_TXM(div_bclk));
2520 regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
2521 I2S_CKR_RSD_MASK | I2S_CKR_TSD_MASK,
2522 I2S_CKR_RSD(div_lrck) | I2S_CKR_TSD(div_lrck));
2523
2524 if (i2s_tdm->clk_trcm)
2525 rockchip_i2s_tdm_xfer_trcm_start(i2s_tdm);
2526 else
2527 rockchip_i2s_tdm_xfer_start(i2s_tdm, SNDRV_PCM_STREAM_PLAYBACK);
2528
2529 pm_runtime_forbid(i2s_tdm->dev);
2530
2531 dev_info(i2s_tdm->dev, "CLK-ALWAYS-ON: mclk: %d, bclk: %d, fsync: %d\n",
2532 mclk_rate, bclk_rate, DEFAULT_FS);
2533
2534 return 0;
2535 }
2536
rockchip_i2s_tdm_probe(struct platform_device * pdev)2537 static int rockchip_i2s_tdm_probe(struct platform_device *pdev)
2538 {
2539 struct device_node *node = pdev->dev.of_node;
2540 const struct of_device_id *of_id;
2541 struct rk_i2s_tdm_dev *i2s_tdm;
2542 struct snd_soc_dai_driver *soc_dai;
2543 struct resource *res;
2544 void __iomem *regs;
2545 #ifdef HAVE_SYNC_RESET
2546 bool sync;
2547 #endif
2548 int ret, val, i, irq;
2549
2550 ret = rockchip_i2s_tdm_dai_prepare(pdev, &soc_dai);
2551 if (ret)
2552 return ret;
2553
2554 i2s_tdm = devm_kzalloc(&pdev->dev, sizeof(*i2s_tdm), GFP_KERNEL);
2555 if (!i2s_tdm)
2556 return -ENOMEM;
2557
2558 i2s_tdm->dev = &pdev->dev;
2559 i2s_tdm->lrck_ratio = 1;
2560
2561 of_id = of_match_device(rockchip_i2s_tdm_match, &pdev->dev);
2562 if (!of_id)
2563 return -EINVAL;
2564
2565 #ifdef CONFIG_SND_SOC_ROCKCHIP_I2S_TDM_MULTI_LANES
2566 i2s_tdm->is_tdm_multi_lanes =
2567 device_property_read_bool(i2s_tdm->dev, "rockchip,tdm-multi-lanes");
2568
2569 if (i2s_tdm->is_tdm_multi_lanes) {
2570 struct device_node *clk_src_node = NULL;
2571
2572 i2s_tdm->tx_lanes = 1;
2573 i2s_tdm->rx_lanes = 1;
2574
2575 if (!device_property_read_u32(i2s_tdm->dev, "rockchip,tdm-tx-lanes", &val)) {
2576 if ((val >= 1) && (val <= 4))
2577 i2s_tdm->tx_lanes = val;
2578 }
2579
2580 if (!device_property_read_u32(i2s_tdm->dev, "rockchip,tdm-rx-lanes", &val)) {
2581 if ((val >= 1) && (val <= 4))
2582 i2s_tdm->rx_lanes = val;
2583 }
2584
2585 i2s_tdm->i2s_lrck_gpio = devm_gpiod_get_optional(&pdev->dev, "i2s-lrck", GPIOD_IN);
2586 if (IS_ERR(i2s_tdm->i2s_lrck_gpio)) {
2587 ret = PTR_ERR(i2s_tdm->i2s_lrck_gpio);
2588 dev_err(&pdev->dev, "Failed to get i2s_lrck_gpio %d\n", ret);
2589 return ret;
2590 }
2591
2592 i2s_tdm->tdm_fsync_gpio = devm_gpiod_get_optional(&pdev->dev, "tdm-fsync", GPIOD_IN);
2593 if (IS_ERR(i2s_tdm->tdm_fsync_gpio)) {
2594 ret = PTR_ERR(i2s_tdm->tdm_fsync_gpio);
2595 dev_err(&pdev->dev, "Failed to get tdm_fsync_gpio %d\n", ret);
2596 return ret;
2597 }
2598
2599 /* It's optional, required when use soc clk src, such as: i2s2_2ch */
2600 clk_src_node = of_parse_phandle(node, "rockchip,clk-src", 0);
2601 if (clk_src_node) {
2602 i2s_tdm->clk_src_base = of_iomap(clk_src_node, 0);
2603 if (!i2s_tdm->clk_src_base)
2604 return -ENOENT;
2605
2606 i2s_tdm->clk_src_dai = rockchip_i2s_tdm_find_dai(clk_src_node);
2607 if (!i2s_tdm->clk_src_dai)
2608 return -EPROBE_DEFER;
2609
2610 pm_runtime_forbid(i2s_tdm->clk_src_dai->dev);
2611 }
2612
2613 dev_info(&pdev->dev, "Used as TDM_MULTI_LANES mode\n");
2614 }
2615 #endif
2616
2617 spin_lock_init(&i2s_tdm->lock);
2618 i2s_tdm->soc_data = (const struct rk_i2s_soc_data *)of_id->data;
2619
2620 for (i = 0; i < ARRAY_SIZE(of_quirks); i++)
2621 if (of_property_read_bool(node, of_quirks[i].quirk))
2622 i2s_tdm->quirks |= of_quirks[i].id;
2623
2624 i2s_tdm->bclk_fs = 64;
2625 if (!of_property_read_u32(node, "rockchip,bclk-fs", &val)) {
2626 if ((val >= 32) && (val % 2 == 0))
2627 i2s_tdm->bclk_fs = val;
2628 }
2629
2630 i2s_tdm->clk_trcm = I2S_CKR_TRCM_TXRX;
2631 if (!of_property_read_u32(node, "rockchip,clk-trcm", &val)) {
2632 if (val >= 0 && val <= 2) {
2633 i2s_tdm->clk_trcm = val << I2S_CKR_TRCM_SHIFT;
2634 if (i2s_tdm->clk_trcm)
2635 soc_dai->symmetric_rates = 1;
2636 }
2637 }
2638
2639 i2s_tdm->tdm_fsync_half_frame =
2640 of_property_read_bool(node, "rockchip,tdm-fsync-half-frame");
2641
2642 if (of_property_read_bool(node, "rockchip,playback-only"))
2643 soc_dai->capture.channels_min = 0;
2644 else if (of_property_read_bool(node, "rockchip,capture-only"))
2645 soc_dai->playback.channels_min = 0;
2646
2647 i2s_tdm->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
2648
2649 i2s_tdm->pinctrl = devm_pinctrl_get(&pdev->dev);
2650 if (!IS_ERR_OR_NULL(i2s_tdm->pinctrl)) {
2651 i2s_tdm->clk_state = pinctrl_lookup_state(i2s_tdm->pinctrl, "clk");
2652 if (IS_ERR(i2s_tdm->clk_state)) {
2653 i2s_tdm->clk_state = NULL;
2654 dev_dbg(i2s_tdm->dev, "Have no clk pinctrl state\n");
2655 }
2656 }
2657
2658 #ifdef HAVE_SYNC_RESET
2659 sync = of_device_is_compatible(node, "rockchip,px30-i2s-tdm") ||
2660 of_device_is_compatible(node, "rockchip,rk1808-i2s-tdm") ||
2661 of_device_is_compatible(node, "rockchip,rk3308-i2s-tdm");
2662
2663 if (i2s_tdm->clk_trcm && sync) {
2664 struct device_node *cru_node;
2665
2666 cru_node = of_parse_phandle(node, "rockchip,cru", 0);
2667 i2s_tdm->cru_base = of_iomap(cru_node, 0);
2668 if (!i2s_tdm->cru_base)
2669 return -ENOENT;
2670
2671 i2s_tdm->tx_reset_id = of_i2s_resetid_get(node, "tx-m");
2672 i2s_tdm->rx_reset_id = of_i2s_resetid_get(node, "rx-m");
2673 }
2674 #endif
2675
2676 i2s_tdm->tx_reset = devm_reset_control_get(&pdev->dev, "tx-m");
2677 if (IS_ERR(i2s_tdm->tx_reset)) {
2678 ret = PTR_ERR(i2s_tdm->tx_reset);
2679 if (ret != -ENOENT)
2680 return ret;
2681 }
2682
2683 i2s_tdm->rx_reset = devm_reset_control_get(&pdev->dev, "rx-m");
2684 if (IS_ERR(i2s_tdm->rx_reset)) {
2685 ret = PTR_ERR(i2s_tdm->rx_reset);
2686 if (ret != -ENOENT)
2687 return ret;
2688 }
2689
2690 i2s_tdm->hclk = devm_clk_get(&pdev->dev, "hclk");
2691 if (IS_ERR(i2s_tdm->hclk))
2692 return PTR_ERR(i2s_tdm->hclk);
2693
2694 ret = clk_prepare_enable(i2s_tdm->hclk);
2695 if (ret)
2696 return ret;
2697
2698 i2s_tdm->mclk_tx = devm_clk_get(&pdev->dev, "mclk_tx");
2699 if (IS_ERR(i2s_tdm->mclk_tx))
2700 return PTR_ERR(i2s_tdm->mclk_tx);
2701
2702 i2s_tdm->mclk_rx = devm_clk_get(&pdev->dev, "mclk_rx");
2703 if (IS_ERR(i2s_tdm->mclk_rx))
2704 return PTR_ERR(i2s_tdm->mclk_rx);
2705
2706 i2s_tdm->io_multiplex =
2707 of_property_read_bool(node, "rockchip,io-multiplex");
2708
2709 i2s_tdm->mclk_calibrate =
2710 of_property_read_bool(node, "rockchip,mclk-calibrate");
2711 if (i2s_tdm->mclk_calibrate) {
2712 i2s_tdm->mclk_tx_src = devm_clk_get(&pdev->dev, "mclk_tx_src");
2713 if (IS_ERR(i2s_tdm->mclk_tx_src))
2714 return PTR_ERR(i2s_tdm->mclk_tx_src);
2715
2716 i2s_tdm->mclk_rx_src = devm_clk_get(&pdev->dev, "mclk_rx_src");
2717 if (IS_ERR(i2s_tdm->mclk_rx_src))
2718 return PTR_ERR(i2s_tdm->mclk_rx_src);
2719
2720 i2s_tdm->mclk_root0 = devm_clk_get(&pdev->dev, "mclk_root0");
2721 if (IS_ERR(i2s_tdm->mclk_root0))
2722 return PTR_ERR(i2s_tdm->mclk_root0);
2723
2724 i2s_tdm->mclk_root1 = devm_clk_get(&pdev->dev, "mclk_root1");
2725 if (IS_ERR(i2s_tdm->mclk_root1))
2726 return PTR_ERR(i2s_tdm->mclk_root1);
2727
2728 i2s_tdm->mclk_root0_initial_freq = clk_get_rate(i2s_tdm->mclk_root0);
2729 i2s_tdm->mclk_root1_initial_freq = clk_get_rate(i2s_tdm->mclk_root1);
2730 i2s_tdm->mclk_root0_freq = i2s_tdm->mclk_root0_initial_freq;
2731 i2s_tdm->mclk_root1_freq = i2s_tdm->mclk_root1_initial_freq;
2732 }
2733
2734 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2735 if (IS_ERR(regs))
2736 return PTR_ERR(regs);
2737
2738 i2s_tdm->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
2739 &rockchip_i2s_tdm_regmap_config);
2740 if (IS_ERR(i2s_tdm->regmap))
2741 return PTR_ERR(i2s_tdm->regmap);
2742
2743 irq = platform_get_irq_optional(pdev, 0);
2744 if (irq > 0) {
2745 ret = devm_request_irq(&pdev->dev, irq, rockchip_i2s_tdm_isr,
2746 IRQF_SHARED, node->name, i2s_tdm);
2747 if (ret) {
2748 dev_err(&pdev->dev, "failed to request irq %u\n", irq);
2749 return ret;
2750 }
2751 }
2752
2753 i2s_tdm->playback_dma_data.addr = res->start + I2S_TXDR;
2754 i2s_tdm->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2755 i2s_tdm->playback_dma_data.maxburst = MAXBURST_PER_FIFO;
2756
2757 i2s_tdm->capture_dma_data.addr = res->start + I2S_RXDR;
2758 i2s_tdm->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2759 i2s_tdm->capture_dma_data.maxburst = MAXBURST_PER_FIFO;
2760
2761 ret = rockchip_i2s_tdm_tx_path_prepare(i2s_tdm, node);
2762 if (ret < 0) {
2763 dev_err(&pdev->dev, "I2S TX path prepare failed: %d\n", ret);
2764 return ret;
2765 }
2766
2767 ret = rockchip_i2s_tdm_rx_path_prepare(i2s_tdm, node);
2768 if (ret < 0) {
2769 dev_err(&pdev->dev, "I2S RX path prepare failed: %d\n", ret);
2770 return ret;
2771 }
2772
2773 atomic_set(&i2s_tdm->refcount, 0);
2774 dev_set_drvdata(&pdev->dev, i2s_tdm);
2775
2776 pm_runtime_enable(&pdev->dev);
2777 if (!pm_runtime_enabled(&pdev->dev)) {
2778 ret = i2s_tdm_runtime_resume(&pdev->dev);
2779 if (ret)
2780 goto err_pm_disable;
2781 }
2782
2783 regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
2784 I2S_DMACR_TDL(16));
2785 regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
2786 I2S_DMACR_RDL(16));
2787 regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
2788 I2S_CKR_TRCM_MASK, i2s_tdm->clk_trcm);
2789
2790 if (i2s_tdm->soc_data && i2s_tdm->soc_data->init)
2791 i2s_tdm->soc_data->init(&pdev->dev, res->start);
2792
2793 /*
2794 * CLK_ALWAYS_ON should be placed after all registers write done,
2795 * because this situation will enable XFER bit which will make
2796 * some registers(depend on XFER) write failed.
2797 */
2798 if (i2s_tdm->quirks & QUIRK_ALWAYS_ON) {
2799 ret = rockchip_i2s_tdm_keep_clk_always_on(i2s_tdm);
2800 if (ret)
2801 goto err_pm_disable;
2802 }
2803
2804 ret = devm_snd_soc_register_component(&pdev->dev,
2805 &rockchip_i2s_tdm_component,
2806 soc_dai, 1);
2807
2808 if (ret) {
2809 dev_err(&pdev->dev, "Could not register DAI\n");
2810 goto err_suspend;
2811 }
2812
2813 if (of_property_read_bool(node, "rockchip,no-dmaengine")) {
2814 dev_info(&pdev->dev, "Used for Multi-DAI\n");
2815 return 0;
2816 }
2817
2818 if (of_property_read_bool(node, "rockchip,digital-loopback"))
2819 ret = devm_snd_dmaengine_dlp_register(&pdev->dev, &dconfig);
2820 else
2821 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
2822
2823 if (ret) {
2824 dev_err(&pdev->dev, "Could not register PCM\n");
2825 return ret;
2826 }
2827
2828 return 0;
2829
2830 err_suspend:
2831 if (!pm_runtime_status_suspended(&pdev->dev))
2832 i2s_tdm_runtime_suspend(&pdev->dev);
2833 err_pm_disable:
2834 pm_runtime_disable(&pdev->dev);
2835
2836 return ret;
2837 }
2838
rockchip_i2s_tdm_remove(struct platform_device * pdev)2839 static int rockchip_i2s_tdm_remove(struct platform_device *pdev)
2840 {
2841 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(&pdev->dev);
2842
2843 pm_runtime_disable(&pdev->dev);
2844 if (!pm_runtime_status_suspended(&pdev->dev))
2845 i2s_tdm_runtime_suspend(&pdev->dev);
2846
2847 clk_disable_unprepare(i2s_tdm->mclk_tx);
2848 clk_disable_unprepare(i2s_tdm->mclk_rx);
2849 clk_disable_unprepare(i2s_tdm->hclk);
2850
2851 return 0;
2852 }
2853
rockchip_i2s_tdm_platform_shutdown(struct platform_device * pdev)2854 static void rockchip_i2s_tdm_platform_shutdown(struct platform_device *pdev)
2855 {
2856 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(&pdev->dev);
2857
2858 pm_runtime_get_sync(i2s_tdm->dev);
2859 rockchip_i2s_tdm_stop(i2s_tdm, SNDRV_PCM_STREAM_PLAYBACK);
2860 rockchip_i2s_tdm_stop(i2s_tdm, SNDRV_PCM_STREAM_CAPTURE);
2861 pm_runtime_put(i2s_tdm->dev);
2862 }
2863
2864 #ifdef CONFIG_PM_SLEEP
rockchip_i2s_tdm_suspend(struct device * dev)2865 static int rockchip_i2s_tdm_suspend(struct device *dev)
2866 {
2867 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
2868
2869 regcache_mark_dirty(i2s_tdm->regmap);
2870
2871 return 0;
2872 }
2873
rockchip_i2s_tdm_resume(struct device * dev)2874 static int rockchip_i2s_tdm_resume(struct device *dev)
2875 {
2876 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
2877 int ret;
2878
2879 ret = pm_runtime_get_sync(dev);
2880 if (ret < 0)
2881 return ret;
2882 ret = regcache_sync(i2s_tdm->regmap);
2883 pm_runtime_put(dev);
2884
2885 return ret;
2886 }
2887 #endif
2888
2889 static const struct dev_pm_ops rockchip_i2s_tdm_pm_ops = {
2890 SET_RUNTIME_PM_OPS(i2s_tdm_runtime_suspend, i2s_tdm_runtime_resume,
2891 NULL)
2892 SET_SYSTEM_SLEEP_PM_OPS(rockchip_i2s_tdm_suspend,
2893 rockchip_i2s_tdm_resume)
2894 };
2895
2896 static struct platform_driver rockchip_i2s_tdm_driver = {
2897 .probe = rockchip_i2s_tdm_probe,
2898 .remove = rockchip_i2s_tdm_remove,
2899 .shutdown = rockchip_i2s_tdm_platform_shutdown,
2900 .driver = {
2901 .name = DRV_NAME,
2902 .of_match_table = of_match_ptr(rockchip_i2s_tdm_match),
2903 .pm = &rockchip_i2s_tdm_pm_ops,
2904 },
2905 };
2906 module_platform_driver(rockchip_i2s_tdm_driver);
2907
2908 MODULE_DESCRIPTION("ROCKCHIP I2S/TDM ASoC Interface");
2909 MODULE_AUTHOR("Sugar Zhang <sugar.zhang@rock-chips.com>");
2910 MODULE_LICENSE("GPL v2");
2911 MODULE_ALIAS("platform:" DRV_NAME);
2912 MODULE_DEVICE_TABLE(of, rockchip_i2s_tdm_match);
2913