1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver
4 //
5 // Copyright (C) 2013 Freescale Semiconductor, Inc.
6 //
7 // Based on stmp3xxx_spdif_dai.c
8 // Vladimir Barinov <vbarinov@embeddedalley.com>
9 // Copyright 2008 SigmaTel, Inc
10 // Copyright 2008 Embedded Alley Solutions, Inc
11
12 #include <linux/bitrev.h>
13 #include <linux/clk.h>
14 #include <linux/module.h>
15 #include <linux/of_address.h>
16 #include <linux/of_device.h>
17 #include <linux/of_irq.h>
18 #include <linux/regmap.h>
19 #include <linux/pm_runtime.h>
20
21 #include <sound/asoundef.h>
22 #include <sound/dmaengine_pcm.h>
23 #include <sound/soc.h>
24
25 #include "fsl_spdif.h"
26 #include "imx-pcm.h"
27
28 #define FSL_SPDIF_TXFIFO_WML 0x8
29 #define FSL_SPDIF_RXFIFO_WML 0x8
30
31 #define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC)
32 #define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL |\
33 INT_URX_OV | INT_QRX_FUL | INT_QRX_OV |\
34 INT_UQ_SYNC | INT_UQ_ERR | INT_RXFIFO_RESYNC |\
35 INT_LOSS_LOCK | INT_DPLL_LOCKED)
36
37 #define SIE_INTR_FOR(tx) (tx ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE)
38
39 /* Index list for the values that has if (DPLL Locked) condition */
40 static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb };
41 #define SRPC_NODPLL_START1 0x5
42 #define SRPC_NODPLL_START2 0xc
43
44 #define DEFAULT_RXCLK_SRC 1
45
46 /**
47 * struct fsl_spdif_soc_data: soc specific data
48 *
49 * @imx: for imx platform
50 * @shared_root_clock: flag of sharing a clock source with others;
51 * so the driver shouldn't set root clock rate
52 */
53 struct fsl_spdif_soc_data {
54 bool imx;
55 bool shared_root_clock;
56 };
57
58 /*
59 * SPDIF control structure
60 * Defines channel status, subcode and Q sub
61 */
62 struct spdif_mixer_control {
63 /* spinlock to access control data */
64 spinlock_t ctl_lock;
65
66 /* IEC958 channel tx status bit */
67 unsigned char ch_status[4];
68
69 /* User bits */
70 unsigned char subcode[2 * SPDIF_UBITS_SIZE];
71
72 /* Q subcode part of user bits */
73 unsigned char qsub[2 * SPDIF_QSUB_SIZE];
74
75 /* Buffer offset for U/Q */
76 u32 upos;
77 u32 qpos;
78
79 /* Ready buffer index of the two buffers */
80 u32 ready_buf;
81 };
82
83 /**
84 * struct fsl_spdif_priv - Freescale SPDIF private data
85 * @soc: SPDIF soc data
86 * @fsl_spdif_control: SPDIF control data
87 * @cpu_dai_drv: cpu dai driver
88 * @pdev: platform device pointer
89 * @regmap: regmap handler
90 * @dpll_locked: dpll lock flag
91 * @txrate: the best rates for playback
92 * @txclk_df: STC_TXCLK_DF dividers value for playback
93 * @sysclk_df: STC_SYSCLK_DF dividers value for playback
94 * @txclk_src: STC_TXCLK_SRC values for playback
95 * @rxclk_src: SRPC_CLKSRC_SEL values for capture
96 * @txclk: tx clock sources for playback
97 * @rxclk: rx clock sources for capture
98 * @coreclk: core clock for register access via DMA
99 * @sysclk: system clock for rx clock rate measurement
100 * @spbaclk: SPBA clock (optional, depending on SoC design)
101 * @dma_params_tx: DMA parameters for transmit channel
102 * @dma_params_rx: DMA parameters for receive channel
103 * @regcache_srpc: regcache for SRPC
104 */
105 struct fsl_spdif_priv {
106 const struct fsl_spdif_soc_data *soc;
107 struct spdif_mixer_control fsl_spdif_control;
108 struct snd_soc_dai_driver cpu_dai_drv;
109 struct platform_device *pdev;
110 struct regmap *regmap;
111 bool dpll_locked;
112 u32 txrate[SPDIF_TXRATE_MAX];
113 u8 txclk_df[SPDIF_TXRATE_MAX];
114 u16 sysclk_df[SPDIF_TXRATE_MAX];
115 u8 txclk_src[SPDIF_TXRATE_MAX];
116 u8 rxclk_src;
117 struct clk *txclk[SPDIF_TXRATE_MAX];
118 struct clk *rxclk;
119 struct clk *coreclk;
120 struct clk *sysclk;
121 struct clk *spbaclk;
122 struct snd_dmaengine_dai_dma_data dma_params_tx;
123 struct snd_dmaengine_dai_dma_data dma_params_rx;
124 /* regcache for SRPC */
125 u32 regcache_srpc;
126 };
127
128 static struct fsl_spdif_soc_data fsl_spdif_vf610 = {
129 .imx = false,
130 .shared_root_clock = false,
131 };
132
133 static struct fsl_spdif_soc_data fsl_spdif_imx35 = {
134 .imx = true,
135 .shared_root_clock = false,
136 };
137
138 static struct fsl_spdif_soc_data fsl_spdif_imx6sx = {
139 .imx = true,
140 .shared_root_clock = true,
141 };
142
143 /* Check if clk is a root clock that does not share clock source with others */
fsl_spdif_can_set_clk_rate(struct fsl_spdif_priv * spdif,int clk)144 static inline bool fsl_spdif_can_set_clk_rate(struct fsl_spdif_priv *spdif, int clk)
145 {
146 return (clk == STC_TXCLK_SPDIF_ROOT) && !spdif->soc->shared_root_clock;
147 }
148
149 /* DPLL locked and lock loss interrupt handler */
spdif_irq_dpll_lock(struct fsl_spdif_priv * spdif_priv)150 static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv)
151 {
152 struct regmap *regmap = spdif_priv->regmap;
153 struct platform_device *pdev = spdif_priv->pdev;
154 u32 locked;
155
156 regmap_read(regmap, REG_SPDIF_SRPC, &locked);
157 locked &= SRPC_DPLL_LOCKED;
158
159 dev_dbg(&pdev->dev, "isr: Rx dpll %s \n",
160 locked ? "locked" : "loss lock");
161
162 spdif_priv->dpll_locked = locked ? true : false;
163 }
164
165 /* Receiver found illegal symbol interrupt handler */
spdif_irq_sym_error(struct fsl_spdif_priv * spdif_priv)166 static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv)
167 {
168 struct regmap *regmap = spdif_priv->regmap;
169 struct platform_device *pdev = spdif_priv->pdev;
170
171 dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n");
172
173 /* Clear illegal symbol if DPLL unlocked since no audio stream */
174 if (!spdif_priv->dpll_locked)
175 regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0);
176 }
177
178 /* U/Q Channel receive register full */
spdif_irq_uqrx_full(struct fsl_spdif_priv * spdif_priv,char name)179 static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char name)
180 {
181 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
182 struct regmap *regmap = spdif_priv->regmap;
183 struct platform_device *pdev = spdif_priv->pdev;
184 u32 *pos, size, val, reg;
185
186 switch (name) {
187 case 'U':
188 pos = &ctrl->upos;
189 size = SPDIF_UBITS_SIZE;
190 reg = REG_SPDIF_SRU;
191 break;
192 case 'Q':
193 pos = &ctrl->qpos;
194 size = SPDIF_QSUB_SIZE;
195 reg = REG_SPDIF_SRQ;
196 break;
197 default:
198 dev_err(&pdev->dev, "unsupported channel name\n");
199 return;
200 }
201
202 dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name);
203
204 if (*pos >= size * 2) {
205 *pos = 0;
206 } else if (unlikely((*pos % size) + 3 > size)) {
207 dev_err(&pdev->dev, "User bit receive buffer overflow\n");
208 return;
209 }
210
211 regmap_read(regmap, reg, &val);
212 ctrl->subcode[*pos++] = val >> 16;
213 ctrl->subcode[*pos++] = val >> 8;
214 ctrl->subcode[*pos++] = val;
215 }
216
217 /* U/Q Channel sync found */
spdif_irq_uq_sync(struct fsl_spdif_priv * spdif_priv)218 static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv)
219 {
220 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
221 struct platform_device *pdev = spdif_priv->pdev;
222
223 dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n");
224
225 /* U/Q buffer reset */
226 if (ctrl->qpos == 0)
227 return;
228
229 /* Set ready to this buffer */
230 ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1;
231 }
232
233 /* U/Q Channel framing error */
spdif_irq_uq_err(struct fsl_spdif_priv * spdif_priv)234 static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv)
235 {
236 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
237 struct regmap *regmap = spdif_priv->regmap;
238 struct platform_device *pdev = spdif_priv->pdev;
239 u32 val;
240
241 dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n");
242
243 /* Read U/Q data to clear the irq and do buffer reset */
244 regmap_read(regmap, REG_SPDIF_SRU, &val);
245 regmap_read(regmap, REG_SPDIF_SRQ, &val);
246
247 /* Drop this U/Q buffer */
248 ctrl->ready_buf = 0;
249 ctrl->upos = 0;
250 ctrl->qpos = 0;
251 }
252
253 /* Get spdif interrupt status and clear the interrupt */
spdif_intr_status_clear(struct fsl_spdif_priv * spdif_priv)254 static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv)
255 {
256 struct regmap *regmap = spdif_priv->regmap;
257 u32 val, val2;
258
259 regmap_read(regmap, REG_SPDIF_SIS, &val);
260 regmap_read(regmap, REG_SPDIF_SIE, &val2);
261
262 regmap_write(regmap, REG_SPDIF_SIC, val & val2);
263
264 return val;
265 }
266
spdif_isr(int irq,void * devid)267 static irqreturn_t spdif_isr(int irq, void *devid)
268 {
269 struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid;
270 struct platform_device *pdev = spdif_priv->pdev;
271 u32 sis;
272
273 sis = spdif_intr_status_clear(spdif_priv);
274
275 if (sis & INT_DPLL_LOCKED)
276 spdif_irq_dpll_lock(spdif_priv);
277
278 if (sis & INT_TXFIFO_UNOV)
279 dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n");
280
281 if (sis & INT_TXFIFO_RESYNC)
282 dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n");
283
284 if (sis & INT_CNEW)
285 dev_dbg(&pdev->dev, "isr: cstatus new\n");
286
287 if (sis & INT_VAL_NOGOOD)
288 dev_dbg(&pdev->dev, "isr: validity flag no good\n");
289
290 if (sis & INT_SYM_ERR)
291 spdif_irq_sym_error(spdif_priv);
292
293 if (sis & INT_BIT_ERR)
294 dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n");
295
296 if (sis & INT_URX_FUL)
297 spdif_irq_uqrx_full(spdif_priv, 'U');
298
299 if (sis & INT_URX_OV)
300 dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n");
301
302 if (sis & INT_QRX_FUL)
303 spdif_irq_uqrx_full(spdif_priv, 'Q');
304
305 if (sis & INT_QRX_OV)
306 dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n");
307
308 if (sis & INT_UQ_SYNC)
309 spdif_irq_uq_sync(spdif_priv);
310
311 if (sis & INT_UQ_ERR)
312 spdif_irq_uq_err(spdif_priv);
313
314 if (sis & INT_RXFIFO_UNOV)
315 dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n");
316
317 if (sis & INT_RXFIFO_RESYNC)
318 dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n");
319
320 if (sis & INT_LOSS_LOCK)
321 spdif_irq_dpll_lock(spdif_priv);
322
323 /* FIXME: Write Tx FIFO to clear TxEm */
324 if (sis & INT_TX_EM)
325 dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n");
326
327 /* FIXME: Read Rx FIFO to clear RxFIFOFul */
328 if (sis & INT_RXFIFO_FUL)
329 dev_dbg(&pdev->dev, "isr: Rx FIFO full\n");
330
331 return IRQ_HANDLED;
332 }
333
spdif_softreset(struct fsl_spdif_priv * spdif_priv)334 static int spdif_softreset(struct fsl_spdif_priv *spdif_priv)
335 {
336 struct regmap *regmap = spdif_priv->regmap;
337 u32 val, cycle = 1000;
338
339 regcache_cache_bypass(regmap, true);
340
341 regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET);
342
343 /*
344 * RESET bit would be cleared after finishing its reset procedure,
345 * which typically lasts 8 cycles. 1000 cycles will keep it safe.
346 */
347 do {
348 regmap_read(regmap, REG_SPDIF_SCR, &val);
349 } while ((val & SCR_SOFT_RESET) && cycle--);
350
351 regcache_cache_bypass(regmap, false);
352 regcache_mark_dirty(regmap);
353 regcache_sync(regmap);
354
355 if (cycle)
356 return 0;
357 else
358 return -EBUSY;
359 }
360
spdif_set_cstatus(struct spdif_mixer_control * ctrl,u8 mask,u8 cstatus)361 static void spdif_set_cstatus(struct spdif_mixer_control *ctrl,
362 u8 mask, u8 cstatus)
363 {
364 ctrl->ch_status[3] &= ~mask;
365 ctrl->ch_status[3] |= cstatus & mask;
366 }
367
spdif_write_channel_status(struct fsl_spdif_priv * spdif_priv)368 static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv)
369 {
370 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
371 struct regmap *regmap = spdif_priv->regmap;
372 struct platform_device *pdev = spdif_priv->pdev;
373 u32 ch_status;
374
375 ch_status = (bitrev8(ctrl->ch_status[0]) << 16) |
376 (bitrev8(ctrl->ch_status[1]) << 8) |
377 bitrev8(ctrl->ch_status[2]);
378 regmap_write(regmap, REG_SPDIF_STCSCH, ch_status);
379
380 dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status);
381
382 ch_status = bitrev8(ctrl->ch_status[3]) << 16;
383 regmap_write(regmap, REG_SPDIF_STCSCL, ch_status);
384
385 dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status);
386 }
387
388 /* Set SPDIF PhaseConfig register for rx clock */
spdif_set_rx_clksrc(struct fsl_spdif_priv * spdif_priv,enum spdif_gainsel gainsel,int dpll_locked)389 static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv,
390 enum spdif_gainsel gainsel, int dpll_locked)
391 {
392 struct regmap *regmap = spdif_priv->regmap;
393 u8 clksrc = spdif_priv->rxclk_src;
394
395 if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX)
396 return -EINVAL;
397
398 regmap_update_bits(regmap, REG_SPDIF_SRPC,
399 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
400 SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel));
401
402 return 0;
403 }
404
spdif_set_sample_rate(struct snd_pcm_substream * substream,int sample_rate)405 static int spdif_set_sample_rate(struct snd_pcm_substream *substream,
406 int sample_rate)
407 {
408 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
409 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
410 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
411 struct regmap *regmap = spdif_priv->regmap;
412 struct platform_device *pdev = spdif_priv->pdev;
413 unsigned long csfs = 0;
414 u32 stc, mask, rate;
415 u16 sysclk_df;
416 u8 clk, txclk_df;
417 int ret;
418
419 switch (sample_rate) {
420 case 32000:
421 rate = SPDIF_TXRATE_32000;
422 csfs = IEC958_AES3_CON_FS_32000;
423 break;
424 case 44100:
425 rate = SPDIF_TXRATE_44100;
426 csfs = IEC958_AES3_CON_FS_44100;
427 break;
428 case 48000:
429 rate = SPDIF_TXRATE_48000;
430 csfs = IEC958_AES3_CON_FS_48000;
431 break;
432 case 96000:
433 rate = SPDIF_TXRATE_96000;
434 csfs = IEC958_AES3_CON_FS_96000;
435 break;
436 case 192000:
437 rate = SPDIF_TXRATE_192000;
438 csfs = IEC958_AES3_CON_FS_192000;
439 break;
440 default:
441 dev_err(&pdev->dev, "unsupported sample rate %d\n", sample_rate);
442 return -EINVAL;
443 }
444
445 clk = spdif_priv->txclk_src[rate];
446 if (clk >= STC_TXCLK_SRC_MAX) {
447 dev_err(&pdev->dev, "tx clock source is out of range\n");
448 return -EINVAL;
449 }
450
451 txclk_df = spdif_priv->txclk_df[rate];
452 if (txclk_df == 0) {
453 dev_err(&pdev->dev, "the txclk_df can't be zero\n");
454 return -EINVAL;
455 }
456
457 sysclk_df = spdif_priv->sysclk_df[rate];
458
459 if (!fsl_spdif_can_set_clk_rate(spdif_priv, clk))
460 goto clk_set_bypass;
461
462 /* The S/PDIF block needs a clock of 64 * fs * txclk_df */
463 ret = clk_set_rate(spdif_priv->txclk[rate],
464 64 * sample_rate * txclk_df);
465 if (ret) {
466 dev_err(&pdev->dev, "failed to set tx clock rate\n");
467 return ret;
468 }
469
470 clk_set_bypass:
471 dev_dbg(&pdev->dev, "expected clock rate = %d\n",
472 (64 * sample_rate * txclk_df * sysclk_df));
473 dev_dbg(&pdev->dev, "actual clock rate = %ld\n",
474 clk_get_rate(spdif_priv->txclk[rate]));
475
476 /* set fs field in consumer channel status */
477 spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs);
478
479 /* select clock source and divisor */
480 stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) |
481 STC_TXCLK_DF(txclk_df) | STC_SYSCLK_DF(sysclk_df);
482 mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK |
483 STC_TXCLK_DF_MASK | STC_SYSCLK_DF_MASK;
484 regmap_update_bits(regmap, REG_SPDIF_STC, mask, stc);
485
486 dev_dbg(&pdev->dev, "set sample rate to %dHz for %dHz playback\n",
487 spdif_priv->txrate[rate], sample_rate);
488
489 return 0;
490 }
491
fsl_spdif_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)492 static int fsl_spdif_startup(struct snd_pcm_substream *substream,
493 struct snd_soc_dai *cpu_dai)
494 {
495 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
496 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
497 struct platform_device *pdev = spdif_priv->pdev;
498 struct regmap *regmap = spdif_priv->regmap;
499 u32 scr, mask;
500 int ret;
501
502 /* Reset module and interrupts only for first initialization */
503 if (!snd_soc_dai_active(cpu_dai)) {
504 ret = spdif_softreset(spdif_priv);
505 if (ret) {
506 dev_err(&pdev->dev, "failed to soft reset\n");
507 return ret;
508 }
509
510 /* Disable all the interrupts */
511 regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0);
512 }
513
514 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
515 scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL |
516 SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP |
517 SCR_TXFIFO_FSEL_IF8;
518 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
519 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
520 SCR_TXFIFO_FSEL_MASK;
521 } else {
522 scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC;
523 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
524 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
525 }
526 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
527
528 /* Power up SPDIF module */
529 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0);
530
531 return 0;
532 }
533
fsl_spdif_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)534 static void fsl_spdif_shutdown(struct snd_pcm_substream *substream,
535 struct snd_soc_dai *cpu_dai)
536 {
537 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
538 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
539 struct regmap *regmap = spdif_priv->regmap;
540 u32 scr, mask;
541
542 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
543 scr = 0;
544 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
545 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
546 SCR_TXFIFO_FSEL_MASK;
547 /* Disable TX clock */
548 regmap_update_bits(regmap, REG_SPDIF_STC, STC_TXCLK_ALL_EN_MASK, 0);
549 } else {
550 scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO;
551 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
552 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
553 }
554 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
555
556 /* Power down SPDIF module only if tx&rx are both inactive */
557 if (!snd_soc_dai_active(cpu_dai)) {
558 spdif_intr_status_clear(spdif_priv);
559 regmap_update_bits(regmap, REG_SPDIF_SCR,
560 SCR_LOW_POWER, SCR_LOW_POWER);
561 }
562 }
563
fsl_spdif_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)564 static int fsl_spdif_hw_params(struct snd_pcm_substream *substream,
565 struct snd_pcm_hw_params *params,
566 struct snd_soc_dai *dai)
567 {
568 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
569 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
570 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
571 struct platform_device *pdev = spdif_priv->pdev;
572 u32 sample_rate = params_rate(params);
573 int ret = 0;
574
575 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
576 ret = spdif_set_sample_rate(substream, sample_rate);
577 if (ret) {
578 dev_err(&pdev->dev, "%s: set sample rate failed: %d\n",
579 __func__, sample_rate);
580 return ret;
581 }
582 spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK,
583 IEC958_AES3_CON_CLOCK_1000PPM);
584 spdif_write_channel_status(spdif_priv);
585 } else {
586 /* Setup rx clock source */
587 ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1);
588 }
589
590 return ret;
591 }
592
fsl_spdif_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)593 static int fsl_spdif_trigger(struct snd_pcm_substream *substream,
594 int cmd, struct snd_soc_dai *dai)
595 {
596 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
597 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
598 struct regmap *regmap = spdif_priv->regmap;
599 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
600 u32 intr = SIE_INTR_FOR(tx);
601 u32 dmaen = SCR_DMA_xX_EN(tx);
602
603 switch (cmd) {
604 case SNDRV_PCM_TRIGGER_START:
605 case SNDRV_PCM_TRIGGER_RESUME:
606 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
607 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr);
608 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen);
609 break;
610 case SNDRV_PCM_TRIGGER_STOP:
611 case SNDRV_PCM_TRIGGER_SUSPEND:
612 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
613 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0);
614 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0);
615 break;
616 default:
617 return -EINVAL;
618 }
619
620 return 0;
621 }
622
623 static const struct snd_soc_dai_ops fsl_spdif_dai_ops = {
624 .startup = fsl_spdif_startup,
625 .hw_params = fsl_spdif_hw_params,
626 .trigger = fsl_spdif_trigger,
627 .shutdown = fsl_spdif_shutdown,
628 };
629
630
631 /*
632 * FSL SPDIF IEC958 controller(mixer) functions
633 *
634 * Channel status get/put control
635 * User bit value get/put control
636 * Valid bit value get control
637 * DPLL lock status get control
638 * User bit sync mode selection control
639 */
640
fsl_spdif_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)641 static int fsl_spdif_info(struct snd_kcontrol *kcontrol,
642 struct snd_ctl_elem_info *uinfo)
643 {
644 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
645 uinfo->count = 1;
646
647 return 0;
648 }
649
fsl_spdif_pb_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * uvalue)650 static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol,
651 struct snd_ctl_elem_value *uvalue)
652 {
653 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
654 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
655 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
656
657 uvalue->value.iec958.status[0] = ctrl->ch_status[0];
658 uvalue->value.iec958.status[1] = ctrl->ch_status[1];
659 uvalue->value.iec958.status[2] = ctrl->ch_status[2];
660 uvalue->value.iec958.status[3] = ctrl->ch_status[3];
661
662 return 0;
663 }
664
fsl_spdif_pb_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * uvalue)665 static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol,
666 struct snd_ctl_elem_value *uvalue)
667 {
668 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
669 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
670 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
671
672 ctrl->ch_status[0] = uvalue->value.iec958.status[0];
673 ctrl->ch_status[1] = uvalue->value.iec958.status[1];
674 ctrl->ch_status[2] = uvalue->value.iec958.status[2];
675 ctrl->ch_status[3] = uvalue->value.iec958.status[3];
676
677 spdif_write_channel_status(spdif_priv);
678
679 return 0;
680 }
681
682 /* Get channel status from SPDIF_RX_CCHAN register */
fsl_spdif_capture_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)683 static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol,
684 struct snd_ctl_elem_value *ucontrol)
685 {
686 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
687 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
688 struct regmap *regmap = spdif_priv->regmap;
689 u32 cstatus, val;
690
691 regmap_read(regmap, REG_SPDIF_SIS, &val);
692 if (!(val & INT_CNEW))
693 return -EAGAIN;
694
695 regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus);
696 ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF;
697 ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF;
698 ucontrol->value.iec958.status[2] = cstatus & 0xFF;
699
700 regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus);
701 ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF;
702 ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF;
703 ucontrol->value.iec958.status[5] = cstatus & 0xFF;
704
705 /* Clear intr */
706 regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW);
707
708 return 0;
709 }
710
711 /*
712 * Get User bits (subcode) from chip value which readed out
713 * in UChannel register.
714 */
fsl_spdif_subcode_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)715 static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol,
716 struct snd_ctl_elem_value *ucontrol)
717 {
718 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
719 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
720 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
721 unsigned long flags;
722 int ret = -EAGAIN;
723
724 spin_lock_irqsave(&ctrl->ctl_lock, flags);
725 if (ctrl->ready_buf) {
726 int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE;
727 memcpy(&ucontrol->value.iec958.subcode[0],
728 &ctrl->subcode[idx], SPDIF_UBITS_SIZE);
729 ret = 0;
730 }
731 spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
732
733 return ret;
734 }
735
736 /* Q-subcode information. The byte size is SPDIF_UBITS_SIZE/8 */
fsl_spdif_qinfo(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)737 static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol,
738 struct snd_ctl_elem_info *uinfo)
739 {
740 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
741 uinfo->count = SPDIF_QSUB_SIZE;
742
743 return 0;
744 }
745
746 /* Get Q subcode from chip value which readed out in QChannel register */
fsl_spdif_qget(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)747 static int fsl_spdif_qget(struct snd_kcontrol *kcontrol,
748 struct snd_ctl_elem_value *ucontrol)
749 {
750 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
751 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
752 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
753 unsigned long flags;
754 int ret = -EAGAIN;
755
756 spin_lock_irqsave(&ctrl->ctl_lock, flags);
757 if (ctrl->ready_buf) {
758 int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE;
759 memcpy(&ucontrol->value.bytes.data[0],
760 &ctrl->qsub[idx], SPDIF_QSUB_SIZE);
761 ret = 0;
762 }
763 spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
764
765 return ret;
766 }
767
768 /* Valid bit information */
fsl_spdif_vbit_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)769 static int fsl_spdif_vbit_info(struct snd_kcontrol *kcontrol,
770 struct snd_ctl_elem_info *uinfo)
771 {
772 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
773 uinfo->count = 1;
774 uinfo->value.integer.min = 0;
775 uinfo->value.integer.max = 1;
776
777 return 0;
778 }
779
780 /* Get valid good bit from interrupt status register */
fsl_spdif_rx_vbit_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)781 static int fsl_spdif_rx_vbit_get(struct snd_kcontrol *kcontrol,
782 struct snd_ctl_elem_value *ucontrol)
783 {
784 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
785 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
786 struct regmap *regmap = spdif_priv->regmap;
787 u32 val;
788
789 regmap_read(regmap, REG_SPDIF_SIS, &val);
790 ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0;
791 regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD);
792
793 return 0;
794 }
795
fsl_spdif_tx_vbit_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)796 static int fsl_spdif_tx_vbit_get(struct snd_kcontrol *kcontrol,
797 struct snd_ctl_elem_value *ucontrol)
798 {
799 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
800 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
801 struct regmap *regmap = spdif_priv->regmap;
802 u32 val;
803
804 regmap_read(regmap, REG_SPDIF_SCR, &val);
805 val = (val & SCR_VAL_MASK) >> SCR_VAL_OFFSET;
806 val = 1 - val;
807 ucontrol->value.integer.value[0] = val;
808
809 return 0;
810 }
811
fsl_spdif_tx_vbit_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)812 static int fsl_spdif_tx_vbit_put(struct snd_kcontrol *kcontrol,
813 struct snd_ctl_elem_value *ucontrol)
814 {
815 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
816 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
817 struct regmap *regmap = spdif_priv->regmap;
818 u32 val = (1 - ucontrol->value.integer.value[0]) << SCR_VAL_OFFSET;
819
820 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_VAL_MASK, val);
821
822 return 0;
823 }
824
825 /* DPLL lock information */
fsl_spdif_rxrate_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)826 static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol,
827 struct snd_ctl_elem_info *uinfo)
828 {
829 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
830 uinfo->count = 1;
831 uinfo->value.integer.min = 16000;
832 uinfo->value.integer.max = 96000;
833
834 return 0;
835 }
836
837 static u32 gainsel_multi[GAINSEL_MULTI_MAX] = {
838 24, 16, 12, 8, 6, 4, 3,
839 };
840
841 /* Get RX data clock rate given the SPDIF bus_clk */
spdif_get_rxclk_rate(struct fsl_spdif_priv * spdif_priv,enum spdif_gainsel gainsel)842 static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv,
843 enum spdif_gainsel gainsel)
844 {
845 struct regmap *regmap = spdif_priv->regmap;
846 struct platform_device *pdev = spdif_priv->pdev;
847 u64 tmpval64, busclk_freq = 0;
848 u32 freqmeas, phaseconf;
849 u8 clksrc;
850
851 regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas);
852 regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf);
853
854 clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf;
855
856 /* Get bus clock from system */
857 if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED))
858 busclk_freq = clk_get_rate(spdif_priv->sysclk);
859
860 /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */
861 tmpval64 = (u64) busclk_freq * freqmeas;
862 do_div(tmpval64, gainsel_multi[gainsel] * 1024);
863 do_div(tmpval64, 128 * 1024);
864
865 dev_dbg(&pdev->dev, "FreqMeas: %d\n", freqmeas);
866 dev_dbg(&pdev->dev, "BusclkFreq: %lld\n", busclk_freq);
867 dev_dbg(&pdev->dev, "RxRate: %lld\n", tmpval64);
868
869 return (int)tmpval64;
870 }
871
872 /*
873 * Get DPLL lock or not info from stable interrupt status register.
874 * User application must use this control to get locked,
875 * then can do next PCM operation
876 */
fsl_spdif_rxrate_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)877 static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol,
878 struct snd_ctl_elem_value *ucontrol)
879 {
880 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
881 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
882 int rate = 0;
883
884 if (spdif_priv->dpll_locked)
885 rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL);
886
887 ucontrol->value.integer.value[0] = rate;
888
889 return 0;
890 }
891
892 /* User bit sync mode info */
fsl_spdif_usync_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)893 static int fsl_spdif_usync_info(struct snd_kcontrol *kcontrol,
894 struct snd_ctl_elem_info *uinfo)
895 {
896 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
897 uinfo->count = 1;
898 uinfo->value.integer.min = 0;
899 uinfo->value.integer.max = 1;
900
901 return 0;
902 }
903
904 /*
905 * User bit sync mode:
906 * 1 CD User channel subcode
907 * 0 Non-CD data
908 */
fsl_spdif_usync_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)909 static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol,
910 struct snd_ctl_elem_value *ucontrol)
911 {
912 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
913 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
914 struct regmap *regmap = spdif_priv->regmap;
915 u32 val;
916
917 regmap_read(regmap, REG_SPDIF_SRCD, &val);
918 ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0;
919
920 return 0;
921 }
922
923 /*
924 * User bit sync mode:
925 * 1 CD User channel subcode
926 * 0 Non-CD data
927 */
fsl_spdif_usync_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)928 static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol,
929 struct snd_ctl_elem_value *ucontrol)
930 {
931 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
932 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
933 struct regmap *regmap = spdif_priv->regmap;
934 u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET;
935
936 regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val);
937
938 return 0;
939 }
940
941 /* FSL SPDIF IEC958 controller defines */
942 static struct snd_kcontrol_new fsl_spdif_ctrls[] = {
943 /* Status cchanel controller */
944 {
945 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
946 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
947 .access = SNDRV_CTL_ELEM_ACCESS_READ |
948 SNDRV_CTL_ELEM_ACCESS_WRITE |
949 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
950 .info = fsl_spdif_info,
951 .get = fsl_spdif_pb_get,
952 .put = fsl_spdif_pb_put,
953 },
954 {
955 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
956 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
957 .access = SNDRV_CTL_ELEM_ACCESS_READ |
958 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
959 .info = fsl_spdif_info,
960 .get = fsl_spdif_capture_get,
961 },
962 /* User bits controller */
963 {
964 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
965 .name = "IEC958 Subcode Capture Default",
966 .access = SNDRV_CTL_ELEM_ACCESS_READ |
967 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
968 .info = fsl_spdif_info,
969 .get = fsl_spdif_subcode_get,
970 },
971 {
972 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
973 .name = "IEC958 Q-subcode Capture Default",
974 .access = SNDRV_CTL_ELEM_ACCESS_READ |
975 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
976 .info = fsl_spdif_qinfo,
977 .get = fsl_spdif_qget,
978 },
979 /* Valid bit error controller */
980 {
981 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
982 .name = "IEC958 RX V-Bit Errors",
983 .access = SNDRV_CTL_ELEM_ACCESS_READ |
984 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
985 .info = fsl_spdif_vbit_info,
986 .get = fsl_spdif_rx_vbit_get,
987 },
988 {
989 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
990 .name = "IEC958 TX V-Bit",
991 .access = SNDRV_CTL_ELEM_ACCESS_READ |
992 SNDRV_CTL_ELEM_ACCESS_WRITE |
993 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
994 .info = fsl_spdif_vbit_info,
995 .get = fsl_spdif_tx_vbit_get,
996 .put = fsl_spdif_tx_vbit_put,
997 },
998 /* DPLL lock info get controller */
999 {
1000 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1001 .name = "RX Sample Rate",
1002 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1003 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1004 .info = fsl_spdif_rxrate_info,
1005 .get = fsl_spdif_rxrate_get,
1006 },
1007 /* User bit sync mode set/get controller */
1008 {
1009 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1010 .name = "IEC958 USyncMode CDText",
1011 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1012 SNDRV_CTL_ELEM_ACCESS_WRITE |
1013 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1014 .info = fsl_spdif_usync_info,
1015 .get = fsl_spdif_usync_get,
1016 .put = fsl_spdif_usync_put,
1017 },
1018 };
1019
fsl_spdif_dai_probe(struct snd_soc_dai * dai)1020 static int fsl_spdif_dai_probe(struct snd_soc_dai *dai)
1021 {
1022 struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai);
1023
1024 snd_soc_dai_init_dma_data(dai, &spdif_private->dma_params_tx,
1025 &spdif_private->dma_params_rx);
1026
1027 snd_soc_add_dai_controls(dai, fsl_spdif_ctrls, ARRAY_SIZE(fsl_spdif_ctrls));
1028
1029 /*Clear the val bit for Tx*/
1030 regmap_update_bits(spdif_private->regmap, REG_SPDIF_SCR,
1031 SCR_VAL_MASK, SCR_VAL_CLEAR);
1032
1033 return 0;
1034 }
1035
1036 static struct snd_soc_dai_driver fsl_spdif_dai = {
1037 .probe = &fsl_spdif_dai_probe,
1038 .playback = {
1039 .stream_name = "CPU-Playback",
1040 .channels_min = 2,
1041 .channels_max = 2,
1042 .rates = FSL_SPDIF_RATES_PLAYBACK,
1043 .formats = FSL_SPDIF_FORMATS_PLAYBACK,
1044 },
1045 .capture = {
1046 .stream_name = "CPU-Capture",
1047 .channels_min = 2,
1048 .channels_max = 2,
1049 .rates = FSL_SPDIF_RATES_CAPTURE,
1050 .formats = FSL_SPDIF_FORMATS_CAPTURE,
1051 },
1052 .ops = &fsl_spdif_dai_ops,
1053 };
1054
1055 static const struct snd_soc_component_driver fsl_spdif_component = {
1056 .name = "fsl-spdif",
1057 };
1058
1059 /* FSL SPDIF REGMAP */
1060 static const struct reg_default fsl_spdif_reg_defaults[] = {
1061 {REG_SPDIF_SCR, 0x00000400},
1062 {REG_SPDIF_SRCD, 0x00000000},
1063 {REG_SPDIF_SIE, 0x00000000},
1064 {REG_SPDIF_STL, 0x00000000},
1065 {REG_SPDIF_STR, 0x00000000},
1066 {REG_SPDIF_STCSCH, 0x00000000},
1067 {REG_SPDIF_STCSCL, 0x00000000},
1068 {REG_SPDIF_STC, 0x00020f00},
1069 };
1070
fsl_spdif_readable_reg(struct device * dev,unsigned int reg)1071 static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg)
1072 {
1073 switch (reg) {
1074 case REG_SPDIF_SCR:
1075 case REG_SPDIF_SRCD:
1076 case REG_SPDIF_SRPC:
1077 case REG_SPDIF_SIE:
1078 case REG_SPDIF_SIS:
1079 case REG_SPDIF_SRL:
1080 case REG_SPDIF_SRR:
1081 case REG_SPDIF_SRCSH:
1082 case REG_SPDIF_SRCSL:
1083 case REG_SPDIF_SRU:
1084 case REG_SPDIF_SRQ:
1085 case REG_SPDIF_STCSCH:
1086 case REG_SPDIF_STCSCL:
1087 case REG_SPDIF_SRFM:
1088 case REG_SPDIF_STC:
1089 return true;
1090 default:
1091 return false;
1092 }
1093 }
1094
fsl_spdif_volatile_reg(struct device * dev,unsigned int reg)1095 static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg)
1096 {
1097 switch (reg) {
1098 case REG_SPDIF_SRPC:
1099 case REG_SPDIF_SIS:
1100 case REG_SPDIF_SRL:
1101 case REG_SPDIF_SRR:
1102 case REG_SPDIF_SRCSH:
1103 case REG_SPDIF_SRCSL:
1104 case REG_SPDIF_SRU:
1105 case REG_SPDIF_SRQ:
1106 case REG_SPDIF_SRFM:
1107 return true;
1108 default:
1109 return false;
1110 }
1111 }
1112
fsl_spdif_writeable_reg(struct device * dev,unsigned int reg)1113 static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg)
1114 {
1115 switch (reg) {
1116 case REG_SPDIF_SCR:
1117 case REG_SPDIF_SRCD:
1118 case REG_SPDIF_SRPC:
1119 case REG_SPDIF_SIE:
1120 case REG_SPDIF_SIC:
1121 case REG_SPDIF_STL:
1122 case REG_SPDIF_STR:
1123 case REG_SPDIF_STCSCH:
1124 case REG_SPDIF_STCSCL:
1125 case REG_SPDIF_STC:
1126 return true;
1127 default:
1128 return false;
1129 }
1130 }
1131
1132 static const struct regmap_config fsl_spdif_regmap_config = {
1133 .reg_bits = 32,
1134 .reg_stride = 4,
1135 .val_bits = 32,
1136
1137 .max_register = REG_SPDIF_STC,
1138 .reg_defaults = fsl_spdif_reg_defaults,
1139 .num_reg_defaults = ARRAY_SIZE(fsl_spdif_reg_defaults),
1140 .readable_reg = fsl_spdif_readable_reg,
1141 .volatile_reg = fsl_spdif_volatile_reg,
1142 .writeable_reg = fsl_spdif_writeable_reg,
1143 .cache_type = REGCACHE_FLAT,
1144 };
1145
fsl_spdif_txclk_caldiv(struct fsl_spdif_priv * spdif_priv,struct clk * clk,u64 savesub,enum spdif_txrate index,bool round)1146 static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv,
1147 struct clk *clk, u64 savesub,
1148 enum spdif_txrate index, bool round)
1149 {
1150 static const u32 rate[] = { 32000, 44100, 48000, 96000, 192000 };
1151 bool is_sysclk = clk_is_match(clk, spdif_priv->sysclk);
1152 u64 rate_ideal, rate_actual, sub;
1153 u32 arate;
1154 u16 sysclk_dfmin, sysclk_dfmax, sysclk_df;
1155 u8 txclk_df;
1156
1157 /* The sysclk has an extra divisor [2, 512] */
1158 sysclk_dfmin = is_sysclk ? 2 : 1;
1159 sysclk_dfmax = is_sysclk ? 512 : 1;
1160
1161 for (sysclk_df = sysclk_dfmin; sysclk_df <= sysclk_dfmax; sysclk_df++) {
1162 for (txclk_df = 1; txclk_df <= 128; txclk_df++) {
1163 rate_ideal = rate[index] * txclk_df * 64ULL;
1164 if (round)
1165 rate_actual = clk_round_rate(clk, rate_ideal);
1166 else
1167 rate_actual = clk_get_rate(clk);
1168
1169 arate = rate_actual / 64;
1170 arate /= txclk_df * sysclk_df;
1171
1172 if (arate == rate[index]) {
1173 /* We are lucky */
1174 savesub = 0;
1175 spdif_priv->txclk_df[index] = txclk_df;
1176 spdif_priv->sysclk_df[index] = sysclk_df;
1177 spdif_priv->txrate[index] = arate;
1178 goto out;
1179 } else if (arate / rate[index] == 1) {
1180 /* A little bigger than expect */
1181 sub = (u64)(arate - rate[index]) * 100000;
1182 do_div(sub, rate[index]);
1183 if (sub >= savesub)
1184 continue;
1185 savesub = sub;
1186 spdif_priv->txclk_df[index] = txclk_df;
1187 spdif_priv->sysclk_df[index] = sysclk_df;
1188 spdif_priv->txrate[index] = arate;
1189 } else if (rate[index] / arate == 1) {
1190 /* A little smaller than expect */
1191 sub = (u64)(rate[index] - arate) * 100000;
1192 do_div(sub, rate[index]);
1193 if (sub >= savesub)
1194 continue;
1195 savesub = sub;
1196 spdif_priv->txclk_df[index] = txclk_df;
1197 spdif_priv->sysclk_df[index] = sysclk_df;
1198 spdif_priv->txrate[index] = arate;
1199 }
1200 }
1201 }
1202
1203 out:
1204 return savesub;
1205 }
1206
fsl_spdif_probe_txclk(struct fsl_spdif_priv * spdif_priv,enum spdif_txrate index)1207 static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv,
1208 enum spdif_txrate index)
1209 {
1210 static const u32 rate[] = { 32000, 44100, 48000, 96000, 192000 };
1211 struct platform_device *pdev = spdif_priv->pdev;
1212 struct device *dev = &pdev->dev;
1213 u64 savesub = 100000, ret;
1214 struct clk *clk;
1215 char tmp[16];
1216 int i;
1217
1218 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
1219 sprintf(tmp, "rxtx%d", i);
1220 clk = devm_clk_get(&pdev->dev, tmp);
1221 if (IS_ERR(clk)) {
1222 dev_err(dev, "no rxtx%d clock in devicetree\n", i);
1223 return PTR_ERR(clk);
1224 }
1225 if (!clk_get_rate(clk))
1226 continue;
1227
1228 ret = fsl_spdif_txclk_caldiv(spdif_priv, clk, savesub, index,
1229 fsl_spdif_can_set_clk_rate(spdif_priv, i));
1230 if (savesub == ret)
1231 continue;
1232
1233 savesub = ret;
1234 spdif_priv->txclk[index] = clk;
1235 spdif_priv->txclk_src[index] = i;
1236
1237 /* To quick catch a divisor, we allow a 0.1% deviation */
1238 if (savesub < 100)
1239 break;
1240 }
1241
1242 dev_dbg(&pdev->dev, "use rxtx%d as tx clock source for %dHz sample rate\n",
1243 spdif_priv->txclk_src[index], rate[index]);
1244 dev_dbg(&pdev->dev, "use txclk df %d for %dHz sample rate\n",
1245 spdif_priv->txclk_df[index], rate[index]);
1246 if (clk_is_match(spdif_priv->txclk[index], spdif_priv->sysclk))
1247 dev_dbg(&pdev->dev, "use sysclk df %d for %dHz sample rate\n",
1248 spdif_priv->sysclk_df[index], rate[index]);
1249 dev_dbg(&pdev->dev, "the best rate for %dHz sample rate is %dHz\n",
1250 rate[index], spdif_priv->txrate[index]);
1251
1252 return 0;
1253 }
1254
fsl_spdif_probe(struct platform_device * pdev)1255 static int fsl_spdif_probe(struct platform_device *pdev)
1256 {
1257 struct fsl_spdif_priv *spdif_priv;
1258 struct spdif_mixer_control *ctrl;
1259 struct resource *res;
1260 void __iomem *regs;
1261 int irq, ret, i;
1262
1263 spdif_priv = devm_kzalloc(&pdev->dev, sizeof(*spdif_priv), GFP_KERNEL);
1264 if (!spdif_priv)
1265 return -ENOMEM;
1266
1267 spdif_priv->pdev = pdev;
1268
1269 spdif_priv->soc = of_device_get_match_data(&pdev->dev);
1270 if (!spdif_priv->soc) {
1271 dev_err(&pdev->dev, "failed to get soc data\n");
1272 return -ENODEV;
1273 }
1274
1275 /* Initialize this copy of the CPU DAI driver structure */
1276 memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai));
1277 spdif_priv->cpu_dai_drv.name = dev_name(&pdev->dev);
1278
1279 /* Get the addresses and IRQ */
1280 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1281 regs = devm_ioremap_resource(&pdev->dev, res);
1282 if (IS_ERR(regs))
1283 return PTR_ERR(regs);
1284
1285 spdif_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
1286 "core", regs, &fsl_spdif_regmap_config);
1287 if (IS_ERR(spdif_priv->regmap)) {
1288 dev_err(&pdev->dev, "regmap init failed\n");
1289 return PTR_ERR(spdif_priv->regmap);
1290 }
1291
1292 irq = platform_get_irq(pdev, 0);
1293 if (irq < 0)
1294 return irq;
1295
1296 ret = devm_request_irq(&pdev->dev, irq, spdif_isr, 0,
1297 dev_name(&pdev->dev), spdif_priv);
1298 if (ret) {
1299 dev_err(&pdev->dev, "could not claim irq %u\n", irq);
1300 return ret;
1301 }
1302
1303 /* Get system clock for rx clock rate calculation */
1304 spdif_priv->sysclk = devm_clk_get(&pdev->dev, "rxtx5");
1305 if (IS_ERR(spdif_priv->sysclk)) {
1306 dev_err(&pdev->dev, "no sys clock (rxtx5) in devicetree\n");
1307 return PTR_ERR(spdif_priv->sysclk);
1308 }
1309
1310 /* Get core clock for data register access via DMA */
1311 spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core");
1312 if (IS_ERR(spdif_priv->coreclk)) {
1313 dev_err(&pdev->dev, "no core clock in devicetree\n");
1314 return PTR_ERR(spdif_priv->coreclk);
1315 }
1316
1317 spdif_priv->spbaclk = devm_clk_get(&pdev->dev, "spba");
1318 if (IS_ERR(spdif_priv->spbaclk))
1319 dev_warn(&pdev->dev, "no spba clock in devicetree\n");
1320
1321 /* Select clock source for rx/tx clock */
1322 spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rxtx1");
1323 if (IS_ERR(spdif_priv->rxclk)) {
1324 dev_err(&pdev->dev, "no rxtx1 clock in devicetree\n");
1325 return PTR_ERR(spdif_priv->rxclk);
1326 }
1327 spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC;
1328
1329 for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
1330 ret = fsl_spdif_probe_txclk(spdif_priv, i);
1331 if (ret)
1332 return ret;
1333 }
1334
1335 /* Initial spinlock for control data */
1336 ctrl = &spdif_priv->fsl_spdif_control;
1337 spin_lock_init(&ctrl->ctl_lock);
1338
1339 /* Init tx channel status default value */
1340 ctrl->ch_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT |
1341 IEC958_AES0_CON_EMPHASIS_5015;
1342 ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID;
1343 ctrl->ch_status[2] = 0x00;
1344 ctrl->ch_status[3] = IEC958_AES3_CON_FS_44100 |
1345 IEC958_AES3_CON_CLOCK_1000PPM;
1346
1347 spdif_priv->dpll_locked = false;
1348
1349 spdif_priv->dma_params_tx.maxburst = FSL_SPDIF_TXFIFO_WML;
1350 spdif_priv->dma_params_rx.maxburst = FSL_SPDIF_RXFIFO_WML;
1351 spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL;
1352 spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL;
1353
1354 /* Register with ASoC */
1355 dev_set_drvdata(&pdev->dev, spdif_priv);
1356 pm_runtime_enable(&pdev->dev);
1357 regcache_cache_only(spdif_priv->regmap, true);
1358
1359 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_spdif_component,
1360 &spdif_priv->cpu_dai_drv, 1);
1361 if (ret) {
1362 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1363 goto err_pm_disable;
1364 }
1365
1366 ret = imx_pcm_dma_init(pdev, IMX_SPDIF_DMABUF_SIZE);
1367 if (ret) {
1368 dev_err_probe(&pdev->dev, ret, "imx_pcm_dma_init failed\n");
1369 goto err_pm_disable;
1370 }
1371
1372 return ret;
1373
1374 err_pm_disable:
1375 pm_runtime_disable(&pdev->dev);
1376 return ret;
1377 }
1378
fsl_spdif_remove(struct platform_device * pdev)1379 static int fsl_spdif_remove(struct platform_device *pdev)
1380 {
1381 pm_runtime_disable(&pdev->dev);
1382
1383 return 0;
1384 }
1385
1386 #ifdef CONFIG_PM
fsl_spdif_runtime_suspend(struct device * dev)1387 static int fsl_spdif_runtime_suspend(struct device *dev)
1388 {
1389 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev);
1390 int i;
1391
1392 /* Disable all the interrupts */
1393 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SIE, 0xffffff, 0);
1394
1395 regmap_read(spdif_priv->regmap, REG_SPDIF_SRPC,
1396 &spdif_priv->regcache_srpc);
1397 regcache_cache_only(spdif_priv->regmap, true);
1398
1399 clk_disable_unprepare(spdif_priv->rxclk);
1400
1401 for (i = 0; i < SPDIF_TXRATE_MAX; i++)
1402 clk_disable_unprepare(spdif_priv->txclk[i]);
1403
1404 if (!IS_ERR(spdif_priv->spbaclk))
1405 clk_disable_unprepare(spdif_priv->spbaclk);
1406 clk_disable_unprepare(spdif_priv->coreclk);
1407
1408 return 0;
1409 }
1410
fsl_spdif_runtime_resume(struct device * dev)1411 static int fsl_spdif_runtime_resume(struct device *dev)
1412 {
1413 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev);
1414 int ret;
1415 int i;
1416
1417 ret = clk_prepare_enable(spdif_priv->coreclk);
1418 if (ret) {
1419 dev_err(dev, "failed to enable core clock\n");
1420 return ret;
1421 }
1422
1423 if (!IS_ERR(spdif_priv->spbaclk)) {
1424 ret = clk_prepare_enable(spdif_priv->spbaclk);
1425 if (ret) {
1426 dev_err(dev, "failed to enable spba clock\n");
1427 goto disable_core_clk;
1428 }
1429 }
1430
1431 for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
1432 ret = clk_prepare_enable(spdif_priv->txclk[i]);
1433 if (ret)
1434 goto disable_tx_clk;
1435 }
1436
1437 ret = clk_prepare_enable(spdif_priv->rxclk);
1438 if (ret)
1439 goto disable_tx_clk;
1440
1441 regcache_cache_only(spdif_priv->regmap, false);
1442 regcache_mark_dirty(spdif_priv->regmap);
1443
1444 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SRPC,
1445 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
1446 spdif_priv->regcache_srpc);
1447
1448 ret = regcache_sync(spdif_priv->regmap);
1449 if (ret)
1450 goto disable_rx_clk;
1451
1452 return 0;
1453
1454 disable_rx_clk:
1455 clk_disable_unprepare(spdif_priv->rxclk);
1456 disable_tx_clk:
1457 for (i--; i >= 0; i--)
1458 clk_disable_unprepare(spdif_priv->txclk[i]);
1459 if (!IS_ERR(spdif_priv->spbaclk))
1460 clk_disable_unprepare(spdif_priv->spbaclk);
1461 disable_core_clk:
1462 clk_disable_unprepare(spdif_priv->coreclk);
1463
1464 return ret;
1465 }
1466 #endif /* CONFIG_PM */
1467
1468 static const struct dev_pm_ops fsl_spdif_pm = {
1469 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1470 pm_runtime_force_resume)
1471 SET_RUNTIME_PM_OPS(fsl_spdif_runtime_suspend, fsl_spdif_runtime_resume,
1472 NULL)
1473 };
1474
1475 static const struct of_device_id fsl_spdif_dt_ids[] = {
1476 { .compatible = "fsl,imx35-spdif", .data = &fsl_spdif_imx35, },
1477 { .compatible = "fsl,vf610-spdif", .data = &fsl_spdif_vf610, },
1478 { .compatible = "fsl,imx6sx-spdif", .data = &fsl_spdif_imx6sx, },
1479 {}
1480 };
1481 MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids);
1482
1483 static struct platform_driver fsl_spdif_driver = {
1484 .driver = {
1485 .name = "fsl-spdif-dai",
1486 .of_match_table = fsl_spdif_dt_ids,
1487 .pm = &fsl_spdif_pm,
1488 },
1489 .probe = fsl_spdif_probe,
1490 .remove = fsl_spdif_remove,
1491 };
1492
1493 module_platform_driver(fsl_spdif_driver);
1494
1495 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1496 MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver");
1497 MODULE_LICENSE("GPL v2");
1498 MODULE_ALIAS("platform:fsl-spdif-dai");
1499