1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * rv1106_codec.c - Rockchip RV1106 SoC Codec Driver
4 *
5 * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
6 */
7
8 #include <linux/clk.h>
9 #include <linux/device.h>
10 #include <linux/delay.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/of_gpio.h>
13 #include <linux/of_platform.h>
14 #include <linux/platform_device.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/regmap.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/reset.h>
19 #include <linux/rockchip/grf.h>
20 #include <sound/pcm_params.h>
21 #include <sound/soc.h>
22 #include <sound/tlv.h>
23
24 #include "rv1106_codec.h"
25
26 #if defined(CONFIG_DEBUG_FS)
27 #include <linux/fs.h>
28 #include <linux/debugfs.h>
29 #include <linux/seq_file.h>
30 #endif
31
32 #define CODEC_DRV_NAME "rv1106-acodec"
33
34 #define PERI_GRF_PERI_CON1 0x004
35 #define ACODEC_AD2DA_LOOP_MSK (1 << 23)
36 #define ACODEC_AD2DA_LOOP_EN (1 << 7)
37 #define ACODEC_AD2DA_LOOP_DIS (1 << 7)
38 /* Control the i2s sdo sdi interface that connect to internal acodec
39 * 1: connect to internal acodec
40 * 0: connect to external acodec
41 */
42 #define ACODEC_MSK (1 << 22)
43 #define ACODEC_EN (1 << 6)
44 #define ACODEC_DIS (0 << 6)
45
46 #define LR(b, x, v) (((1 << b) & x) ? v : 0)
47 #define L(x, v) LR(0, x, v)
48 #define R(x, v) LR(1, x, v)
49
50 #define ADCL (1 << 0)
51 #define ADCR (1 << 1)
52
53 #define NOT_SPECIFIED (-1)
54
55 enum soc_id_e {
56 SOC_RV1103 = 0x1103,
57 SOC_RV1106 = 0x1106,
58 };
59
60 enum adc_mode_e {
61 DIFF_ADCL = 0, /* Differential ADCL, the ADCR is not used */
62 SING_ADCL, /* Single-end ADCL, the ADCR is not used */
63 DIFF_ADCR, /* Differential ADCR, the ADCL is not used */
64 SING_ADCR, /* Single-end ADCR, the ADCL is not used */
65 SING_ADCLR, /* Single-end ADCL and ADCR */
66 DIFF_ADCLR, /* Differential ADCL and ADCR (Not supported on rv1103 codec) */
67 ADC_MODE_NUM,
68 };
69
70 struct rv1106_codec_priv {
71 const struct device *plat_dev;
72 struct device dev;
73 struct reset_control *reset;
74 struct regmap *regmap;
75 struct regmap *grf;
76 struct clk *pclk_acodec;
77 struct clk *mclk_acodec;
78 struct clk *mclk_cpu;
79 struct gpio_desc *pa_ctl_gpio;
80 struct snd_soc_component *component;
81
82 enum adc_mode_e adc_mode;
83 enum soc_id_e soc_id;
84
85 u32 pa_ctl_delay_ms;
86 u32 micbias_volt;
87
88 /* AGC L/R Off/on */
89 unsigned int agc_l;
90 unsigned int agc_r;
91
92 /* AGC L/R Approximate Sample Rate */
93 unsigned int agc_asr_l;
94 unsigned int agc_asr_r;
95
96 /* ADC MIC Mute/Work */
97 unsigned int mic_mute_l;
98 unsigned int mic_mute_r;
99
100 /* For the high pass filter */
101 unsigned int hpf_cutoff;
102
103 /* Specify init gains after codec startup */
104 unsigned int init_mic_gain;
105 unsigned int init_alc_gain;
106 unsigned int init_lineout_gain;
107
108 bool adc_enable;
109 bool dac_enable;
110 bool micbias_enable;
111 bool micbias_used;
112
113 #if defined(CONFIG_DEBUG_FS)
114 struct dentry *dbg_codec;
115 #endif
116 };
117
118 static const DECLARE_TLV_DB_SCALE(rv1106_codec_alc_agc_gain_tlv,
119 -1800, 150, 2850);
120 static const DECLARE_TLV_DB_SCALE(rv1106_codec_alc_agc_max_gain_tlv,
121 -1350, 600, 2850);
122 static const DECLARE_TLV_DB_SCALE(rv1106_codec_alc_agc_min_gain_tlv,
123 -1800, 600, 2400);
124 static const DECLARE_TLV_DB_SCALE(rv1106_codec_adc_alc_gain_tlv,
125 -900, 150, 3750);
126 static const DECLARE_TLV_DB_SCALE(rv1106_codec_adc_dig_gain_tlv,
127 -9750, 50, 3000);
128 static const DECLARE_TLV_DB_SCALE(rv1106_codec_dac_lineout_gain_tlv,
129 -3900, 150, 600);
130
131 static const DECLARE_TLV_DB_RANGE(rv1106_codec_adc_mic_gain_tlv,
132 1, 1, TLV_DB_SCALE_ITEM(0, 0, 0),
133 2, 2, TLV_DB_SCALE_ITEM(2000, 0, 0),
134 3, 3, TLV_DB_SCALE_ITEM(1200, 0, 0),
135 );
136
137 static const DECLARE_TLV_DB_RANGE(rv1106_codec_dac_hpmix_gain_tlv,
138 1, 2, TLV_DB_SCALE_ITEM(0, 600, 0),
139 );
140
141 static int check_micbias(int volt);
142
143 static int rv1106_codec_adc_enable(struct rv1106_codec_priv *rv1106);
144 static int rv1106_codec_adc_disable(struct rv1106_codec_priv *rv1106);
145
146 static int rv1106_codec_micbias_enable(struct rv1106_codec_priv *rv1106,
147 int micbias_volt);
148 static int rv1106_codec_hpmix_gain_get(struct snd_kcontrol *kcontrol,
149 struct snd_ctl_elem_value *ucontrol);
150 static int rv1106_codec_hpmix_gain_put(struct snd_kcontrol *kcontrol,
151 struct snd_ctl_elem_value *ucontrol);
152 static int rv1106_codec_micbias_disable(struct rv1106_codec_priv *rv1106);
153 static int rv1106_codec_hpf_get(struct snd_kcontrol *kcontrol,
154 struct snd_ctl_elem_value *ucontrol);
155 static int rv1106_codec_hpf_put(struct snd_kcontrol *kcontrol,
156 struct snd_ctl_elem_value *ucontrol);
157 static int rv1106_codec_adc_mode_get(struct snd_kcontrol *kcontrol,
158 struct snd_ctl_elem_value *ucontrol);
159 static int rv1106_codec_adc_mode_put(struct snd_kcontrol *kcontrol,
160 struct snd_ctl_elem_value *ucontrol);
161 static int rv1106_codec_agc_get(struct snd_kcontrol *kcontrol,
162 struct snd_ctl_elem_value *ucontrol);
163 static int rv1106_codec_agc_put(struct snd_kcontrol *kcontrol,
164 struct snd_ctl_elem_value *ucontrol);
165 static int rv1106_codec_agc_asr_get(struct snd_kcontrol *kcontrol,
166 struct snd_ctl_elem_value *ucontrol);
167 static int rv1106_codec_agc_asr_put(struct snd_kcontrol *kcontrol,
168 struct snd_ctl_elem_value *ucontrol);
169 static int rv1106_codec_mic_mute_get(struct snd_kcontrol *kcontrol,
170 struct snd_ctl_elem_value *ucontrol);
171 static int rv1106_codec_mic_mute_put(struct snd_kcontrol *kcontrol,
172 struct snd_ctl_elem_value *ucontrol);
173 static int rv1106_codec_mic_gain_get(struct snd_kcontrol *kcontrol,
174 struct snd_ctl_elem_value *ucontrol);
175 static int rv1106_codec_mic_gain_put(struct snd_kcontrol *kcontrol,
176 struct snd_ctl_elem_value *ucontrol);
177 static int rv1106_codec_micbias_volts_get(struct snd_kcontrol *kcontrol,
178 struct snd_ctl_elem_value *ucontrol);
179 static int rv1106_codec_micbias_volts_put(struct snd_kcontrol *kcontrol,
180 struct snd_ctl_elem_value *ucontrol);
181 static int rv1106_codec_main_micbias_get(struct snd_kcontrol *kcontrol,
182 struct snd_ctl_elem_value *ucontrol);
183 static int rv1106_codec_main_micbias_put(struct snd_kcontrol *kcontrol,
184 struct snd_ctl_elem_value *ucontrol);
185
186 static const char *offon_text[2] = {
187 [0] = "Off",
188 [1] = "On",
189 };
190
191 static const char *mute_text[2] = {
192 [0] = "Work",
193 [1] = "Mute",
194 };
195
196 /* ADC MICBIAS Volt */
197 #define MICBIAS_VOLT_NUM 8
198
199 #define MICBIAS_VREFx0_8 0
200 #define MICBIAS_VREFx0_825 1
201 #define MICBIAS_VREFx0_85 2
202 #define MICBIAS_VREFx0_875 3
203 #define MICBIAS_VREFx0_9 4
204 #define MICBIAS_VREFx0_925 5
205 #define MICBIAS_VREFx0_95 6
206 #define MICBIAS_VREFx0_975 7
207
208 static const char *micbias_volts_enum_array[MICBIAS_VOLT_NUM] = {
209 [MICBIAS_VREFx0_8] = "VREFx0_8",
210 [MICBIAS_VREFx0_825] = "VREFx0_825",
211 [MICBIAS_VREFx0_85] = "VREFx0_85",
212 [MICBIAS_VREFx0_875] = "VREFx0_875",
213 [MICBIAS_VREFx0_9] = "VREFx0_9",
214 [MICBIAS_VREFx0_925] = "VREFx0_925",
215 [MICBIAS_VREFx0_95] = "VREFx0_95",
216 [MICBIAS_VREFx0_975] = "VREFx0_975",
217 };
218
219 static const char *adc_mode_enum_array[ADC_MODE_NUM] = {
220 [DIFF_ADCL] = "DiffadcL",
221 [SING_ADCL] = "SingadcL",
222 [DIFF_ADCR] = "DiffadcR",
223 [SING_ADCR] = "SingadcR",
224 [SING_ADCLR] = "SingadcLR",
225 [DIFF_ADCLR] = "DiffadcLR",
226 };
227
228 static const struct soc_enum rv1106_adc_mode_enum_array[] = {
229 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(adc_mode_enum_array), adc_mode_enum_array),
230 };
231
232 static const struct soc_enum rv1106_micbias_volts_enum_array[] = {
233 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(micbias_volts_enum_array), micbias_volts_enum_array),
234 };
235
236 /* ADC MICBIAS Main Switch */
237 static const struct soc_enum rv1106_main_micbias_enum_array[] = {
238 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(offon_text), offon_text),
239 };
240
241 static const struct soc_enum rv1106_hpf_enum_array[] = {
242 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(offon_text), offon_text),
243 };
244
245 /* ALC AGC Switch */
246 static const struct soc_enum rv1106_agc_enum_array[] = {
247 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(offon_text), offon_text),
248 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(offon_text), offon_text),
249 };
250
251 /* ADC MIC Mute/Work Switch */
252 static const struct soc_enum rv1106_mic_mute_enum_array[] = {
253 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(mute_text), mute_text),
254 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(mute_text), mute_text),
255 };
256
257 /* ALC AGC Approximate Sample Rate */
258 #define AGC_ASR_NUM 8
259
260 #define AGC_ASR_96KHZ 0
261 #define AGC_ASR_48KHZ 1
262 #define AGC_ASR_44_1KHZ 2
263 #define AGC_ASR_32KHZ 3
264 #define AGC_ASR_24KHZ 4
265 #define AGC_ASR_16KHZ 5
266 #define AGC_ASR_12KHZ 6
267 #define AGC_ASR_8KHZ 7
268
269 static const char *agc_asr_text[AGC_ASR_NUM] = {
270 [AGC_ASR_96KHZ] = "96KHz",
271 [AGC_ASR_48KHZ] = "48KHz",
272 [AGC_ASR_44_1KHZ] = "44.1KHz",
273 [AGC_ASR_32KHZ] = "32KHz",
274 [AGC_ASR_24KHZ] = "24KHz",
275 [AGC_ASR_16KHZ] = "16KHz",
276 [AGC_ASR_12KHZ] = "12KHz",
277 [AGC_ASR_8KHZ] = "8KHz",
278 };
279
280 static const struct soc_enum rv1106_agc_asr_enum_array[] = {
281 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(agc_asr_text), agc_asr_text),
282 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(agc_asr_text), agc_asr_text),
283 };
284
285 static const struct snd_kcontrol_new rv1106_codec_dapm_controls[] = {
286 /* ADC MIC */
287 SOC_SINGLE_EXT_TLV("ADC MIC Left Gain",
288 ACODEC_ADC_ANA_CTL2,
289 ACODEC_ADC_L_MIC_GAIN_SFT,
290 ACODEC_ADC_MIC_GAIN_MAX,
291 0,
292 rv1106_codec_mic_gain_get,
293 rv1106_codec_mic_gain_put,
294 rv1106_codec_adc_mic_gain_tlv),
295 SOC_SINGLE_EXT_TLV("ADC MIC Right Gain",
296 ACODEC_ADC_ANA_CTL2,
297 ACODEC_ADC_R_MIC_GAIN_SFT,
298 ACODEC_ADC_MIC_GAIN_MAX,
299 0,
300 rv1106_codec_mic_gain_get,
301 rv1106_codec_mic_gain_put,
302 rv1106_codec_adc_mic_gain_tlv),
303
304 /* ADC ALC */
305 SOC_SINGLE_RANGE_TLV("ADC ALC Left Volume",
306 ACODEC_ADC_ANA_CTL4,
307 ACODEC_ADC_L_ALC_GAIN_SFT,
308 ACODEC_ADC_L_ALC_GAIN_MIN,
309 ACODEC_ADC_L_ALC_GAIN_MAX,
310 0, rv1106_codec_adc_alc_gain_tlv),
311 SOC_SINGLE_RANGE_TLV("ADC ALC Right Volume",
312 ACODEC_ADC_ANA_CTL5,
313 ACODEC_ADC_R_ALC_GAIN_SFT,
314 ACODEC_ADC_R_ALC_GAIN_MIN,
315 ACODEC_ADC_R_ALC_GAIN_MAX,
316 0, rv1106_codec_adc_alc_gain_tlv),
317
318 /* ADC Digital Volume */
319 SOC_SINGLE_RANGE_TLV("ADC Digital Left Volume",
320 ACODEC_ADC_L_DIG_VOL,
321 ACODEC_ADC_L_DIG_VOL_SFT,
322 ACODEC_ADC_L_DIG_VOL_MIN,
323 ACODEC_ADC_L_DIG_VOL_MAX,
324 0, rv1106_codec_adc_dig_gain_tlv),
325 SOC_SINGLE_RANGE_TLV("ADC Digital Right Volume",
326 ACODEC_ADC_R_DIG_VOL,
327 ACODEC_ADC_R_DIG_VOL_SFT,
328 ACODEC_ADC_R_DIG_VOL_MIN,
329 ACODEC_ADC_R_DIG_VOL_MAX,
330 0, rv1106_codec_adc_dig_gain_tlv),
331
332 /* ADC High Pass Filter */
333 SOC_ENUM_EXT("ADC HPF Cut-off", rv1106_hpf_enum_array[0],
334 rv1106_codec_hpf_get, rv1106_codec_hpf_put),
335
336 /* ALC AGC Group */
337 SOC_SINGLE_RANGE_TLV("ALC AGC Left Volume",
338 ACODEC_ADC_PGA_AGC_L_CTL3,
339 ACODEC_AGC_PGA_GAIN_SFT,
340 ACODEC_AGC_PGA_GAIN_MIN,
341 ACODEC_AGC_PGA_GAIN_MAX,
342 0, rv1106_codec_alc_agc_gain_tlv),
343 SOC_SINGLE_RANGE_TLV("ALC AGC Right Volume",
344 ACODEC_ADC_PGA_AGC_R_CTL3,
345 ACODEC_AGC_PGA_GAIN_SFT,
346 ACODEC_AGC_PGA_GAIN_MIN,
347 ACODEC_AGC_PGA_GAIN_MAX,
348 0, rv1106_codec_alc_agc_gain_tlv),
349
350 /* ALC AGC MAX */
351 SOC_SINGLE_RANGE_TLV("ALC AGC Left Max Volume",
352 ACODEC_ADC_PGA_AGC_L_CTL9,
353 ACODEC_AGC_MAX_GAIN_PGA_SFT,
354 ACODEC_AGC_MAX_GAIN_PGA_MIN,
355 ACODEC_AGC_MAX_GAIN_PGA_MAX,
356 0, rv1106_codec_alc_agc_max_gain_tlv),
357 SOC_SINGLE_RANGE_TLV("ALC AGC Right Max Volume",
358 ACODEC_ADC_PGA_AGC_R_CTL9,
359 ACODEC_AGC_MAX_GAIN_PGA_SFT,
360 ACODEC_AGC_MAX_GAIN_PGA_MIN,
361 ACODEC_AGC_MAX_GAIN_PGA_MAX,
362 0, rv1106_codec_alc_agc_max_gain_tlv),
363
364 /* ALC AGC MIN */
365 SOC_SINGLE_RANGE_TLV("ALC AGC Left Min Volume",
366 ACODEC_ADC_PGA_AGC_L_CTL9,
367 ACODEC_AGC_MIN_GAIN_PGA_SFT,
368 ACODEC_AGC_MIN_GAIN_PGA_MIN,
369 ACODEC_AGC_MIN_GAIN_PGA_MAX,
370 0, rv1106_codec_alc_agc_min_gain_tlv),
371 SOC_SINGLE_RANGE_TLV("ALC AGC Right Min Volume",
372 ACODEC_ADC_PGA_AGC_R_CTL9,
373 ACODEC_AGC_MIN_GAIN_PGA_SFT,
374 ACODEC_AGC_MIN_GAIN_PGA_MIN,
375 ACODEC_AGC_MIN_GAIN_PGA_MAX,
376 0, rv1106_codec_alc_agc_min_gain_tlv),
377
378 /* ALC AGC Switch */
379 SOC_ENUM_EXT("ALC AGC Left Switch", rv1106_agc_enum_array[0],
380 rv1106_codec_agc_get, rv1106_codec_agc_put),
381 SOC_ENUM_EXT("ALC AGC Right Switch", rv1106_agc_enum_array[1],
382 rv1106_codec_agc_get, rv1106_codec_agc_put),
383
384 /* ALC AGC Approximate Sample Rate */
385 SOC_ENUM_EXT("AGC Left Approximate Sample Rate", rv1106_agc_asr_enum_array[0],
386 rv1106_codec_agc_asr_get, rv1106_codec_agc_asr_put),
387 SOC_ENUM_EXT("AGC Right Approximate Sample Rate", rv1106_agc_asr_enum_array[1],
388 rv1106_codec_agc_asr_get, rv1106_codec_agc_asr_put),
389
390 /* ADC Mode */
391 SOC_ENUM_EXT("ADC Mode", rv1106_adc_mode_enum_array[0],
392 rv1106_codec_adc_mode_get, rv1106_codec_adc_mode_put),
393
394 /* ADC MICBIAS Voltage */
395 SOC_ENUM_EXT("ADC MICBIAS Voltage", rv1106_micbias_volts_enum_array[0],
396 rv1106_codec_micbias_volts_get, rv1106_codec_micbias_volts_put),
397
398 /* ADC Main MICBIAS Switch */
399 SOC_ENUM_EXT("ADC Main MICBIAS", rv1106_main_micbias_enum_array[0],
400 rv1106_codec_main_micbias_get, rv1106_codec_main_micbias_put),
401
402 /* ADC MIC Mute/Work Switch */
403 SOC_ENUM_EXT("ADC MIC Left Switch", rv1106_mic_mute_enum_array[0],
404 rv1106_codec_mic_mute_get, rv1106_codec_mic_mute_put),
405 SOC_ENUM_EXT("ADC MIC Right Switch", rv1106_mic_mute_enum_array[1],
406 rv1106_codec_mic_mute_get, rv1106_codec_mic_mute_put),
407
408 /* DAC LINEOUT */
409 SOC_SINGLE_RANGE_TLV("DAC LINEOUT Volume",
410 ACODEC_DAC_ANA_CTL2,
411 ACODEC_DAC_LINEOUT_GAIN_SFT,
412 ACODEC_DAC_LINEOUT_GAIN_MIN,
413 ACODEC_DAC_LINEOUT_GAIN_MAX,
414 0, rv1106_codec_dac_lineout_gain_tlv),
415
416 /* DAC HPMIX */
417 SOC_SINGLE_EXT_TLV("DAC HPMIX Volume",
418 ACODEC_DAC_HPMIX_CTL,
419 ACODEC_DAC_HPMIX_GAIN_SFT,
420 ACODEC_DAC_HPMIX_GAIN_MAX,
421 0,
422 rv1106_codec_hpmix_gain_get,
423 rv1106_codec_hpmix_gain_put,
424 rv1106_codec_dac_hpmix_gain_tlv),
425 };
426
using_adc_lr(enum adc_mode_e adc_mode)427 static unsigned int using_adc_lr(enum adc_mode_e adc_mode)
428 {
429 if (adc_mode >= SING_ADCLR && adc_mode <= DIFF_ADCLR)
430 return (ADCL | ADCR);
431 else if (adc_mode >= DIFF_ADCR && adc_mode <= SING_ADCR)
432 return ADCR;
433 else
434 return ADCL;
435 }
436
using_adc_diff(enum adc_mode_e adc_mode)437 static bool using_adc_diff(enum adc_mode_e adc_mode)
438 {
439 if (adc_mode == DIFF_ADCL ||
440 adc_mode == DIFF_ADCR ||
441 adc_mode == DIFF_ADCLR)
442 return true;
443 else
444 return false;
445 }
446
check_adc_mode(struct rv1106_codec_priv * rv1106)447 static int check_adc_mode(struct rv1106_codec_priv *rv1106)
448 {
449 if (rv1106->soc_id == SOC_RV1103 &&
450 (rv1106->adc_mode == DIFF_ADCLR ||
451 rv1106->adc_mode == DIFF_ADCR)) {
452 dev_err(rv1106->plat_dev,
453 "%s: Differential mode rv1103 only supports 'DiffadcL'\n", __func__);
454 return -EINVAL;
455 }
456
457 return 0;
458 }
459
rv1106_codec_adc_mode_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)460 static int rv1106_codec_adc_mode_get(struct snd_kcontrol *kcontrol,
461 struct snd_ctl_elem_value *ucontrol)
462 {
463 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
464 struct rv1106_codec_priv *rv1106 = snd_soc_component_get_drvdata(component);
465
466 ucontrol->value.integer.value[0] = rv1106->adc_mode;
467
468 return 0;
469 }
470
rv1106_codec_adc_mode_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)471 static int rv1106_codec_adc_mode_put(struct snd_kcontrol *kcontrol,
472 struct snd_ctl_elem_value *ucontrol)
473 {
474 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
475 struct rv1106_codec_priv *rv1106 = snd_soc_component_get_drvdata(component);
476 unsigned int last_mode = rv1106->adc_mode;
477
478 rv1106->adc_mode = ucontrol->value.integer.value[0];
479 if (check_adc_mode(rv1106)) {
480 dev_err(rv1106->plat_dev,
481 "%s - something error checking ADC mode\n", __func__);
482 rv1106->adc_mode = last_mode;
483 return 0;
484 }
485
486 return 0;
487 }
488
rv1106_codec_agc_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)489 static int rv1106_codec_agc_get(struct snd_kcontrol *kcontrol,
490 struct snd_ctl_elem_value *ucontrol)
491 {
492 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
493 struct rv1106_codec_priv *rv1106 = snd_soc_component_get_drvdata(component);
494 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
495
496 if (e->shift_l)
497 ucontrol->value.integer.value[0] = rv1106->agc_r;
498 else
499 ucontrol->value.integer.value[0] = rv1106->agc_l;
500
501 return 0;
502 }
503
rv1106_codec_agc_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)504 static int rv1106_codec_agc_put(struct snd_kcontrol *kcontrol,
505 struct snd_ctl_elem_value *ucontrol)
506 {
507 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
508 struct rv1106_codec_priv *rv1106 = snd_soc_component_get_drvdata(component);
509 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
510 unsigned int value = ucontrol->value.integer.value[0];
511
512 if (value) {
513 /* ALC AGC On */
514 if (e->shift_l) {
515 /* ALC AGC Right On */
516 regmap_update_bits(rv1106->regmap, ACODEC_ADC_PGA_AGC_R_CTL9,
517 ACODEC_AGC_FUNC_SEL_MSK,
518 ACODEC_AGC_FUNC_SEL_EN);
519 regmap_update_bits(rv1106->regmap, ACODEC_ADC_HPF_PGA_CTL,
520 ACODEC_ADC_R_PGA_MSK,
521 ACODEC_ADC_PGA_ALCR_EN);
522
523 rv1106->agc_r = 1;
524 } else {
525 /* ALC AGC Left On */
526 regmap_update_bits(rv1106->regmap, ACODEC_ADC_PGA_AGC_L_CTL9,
527 ACODEC_AGC_FUNC_SEL_MSK,
528 ACODEC_AGC_FUNC_SEL_EN);
529 regmap_update_bits(rv1106->regmap, ACODEC_ADC_HPF_PGA_CTL,
530 ACODEC_ADC_L_PGA_MSK,
531 ACODEC_ADC_PGA_ALCL_EN);
532
533 rv1106->agc_l = 1;
534 }
535 } else {
536 /* ALC AGC Off */
537 if (e->shift_l) {
538 /* ALC AGC Right Off */
539 regmap_update_bits(rv1106->regmap, ACODEC_ADC_PGA_AGC_R_CTL9,
540 ACODEC_AGC_FUNC_SEL_MSK,
541 ACODEC_AGC_FUNC_SEL_DIS);
542 regmap_update_bits(rv1106->regmap, ACODEC_ADC_HPF_PGA_CTL,
543 ACODEC_ADC_R_PGA_MSK,
544 ACODEC_ADC_PGA_ALCR_DIS);
545
546 rv1106->agc_r = 0;
547 } else {
548 /* ALC AGC Left Off */
549 regmap_update_bits(rv1106->regmap, ACODEC_ADC_PGA_AGC_L_CTL9,
550 ACODEC_AGC_FUNC_SEL_MSK,
551 ACODEC_AGC_FUNC_SEL_DIS);
552 regmap_update_bits(rv1106->regmap, ACODEC_ADC_HPF_PGA_CTL,
553 ACODEC_ADC_L_PGA_MSK,
554 ACODEC_ADC_PGA_ALCL_DIS);
555
556 rv1106->agc_l = 0;
557 }
558 }
559
560 return 0;
561 }
562
rv1106_codec_agc_asr_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)563 static int rv1106_codec_agc_asr_get(struct snd_kcontrol *kcontrol,
564 struct snd_ctl_elem_value *ucontrol)
565 {
566 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
567 struct rv1106_codec_priv *rv1106 = snd_soc_component_get_drvdata(component);
568 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
569 unsigned int value;
570
571 if (e->shift_l) {
572 regmap_read(rv1106->regmap, ACODEC_ADC_PGA_AGC_R_CTL4, &value);
573 rv1106->agc_asr_r = value >> ACODEC_AGC_APPROX_RATE_SFT;
574 ucontrol->value.integer.value[0] = rv1106->agc_asr_r;
575 } else {
576 regmap_read(rv1106->regmap, ACODEC_ADC_PGA_AGC_L_CTL4, &value);
577 rv1106->agc_asr_l = value >> ACODEC_AGC_APPROX_RATE_SFT;
578 ucontrol->value.integer.value[0] = rv1106->agc_asr_l;
579 }
580
581 return 0;
582 }
583
rv1106_codec_agc_asr_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)584 static int rv1106_codec_agc_asr_put(struct snd_kcontrol *kcontrol,
585 struct snd_ctl_elem_value *ucontrol)
586 {
587 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
588 struct rv1106_codec_priv *rv1106 = snd_soc_component_get_drvdata(component);
589 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
590 unsigned int value;
591
592 value = ucontrol->value.integer.value[0] << ACODEC_AGC_APPROX_RATE_SFT;
593
594 if (e->shift_l) {
595 /* ALC AGC Right Approximate Sample Rate */
596 regmap_update_bits(rv1106->regmap, ACODEC_ADC_PGA_AGC_R_CTL4,
597 ACODEC_AGC_APPROX_RATE_MSK,
598 value);
599 rv1106->agc_asr_r = ucontrol->value.integer.value[0];
600 } else {
601 /* ALC AGC Left Approximate Sample Rate */
602 regmap_update_bits(rv1106->regmap, ACODEC_ADC_PGA_AGC_L_CTL4,
603 ACODEC_AGC_APPROX_RATE_MSK,
604 value);
605 rv1106->agc_asr_l = ucontrol->value.integer.value[0];
606 }
607
608 return 0;
609 }
610
rv1106_codec_mic_mute_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)611 static int rv1106_codec_mic_mute_get(struct snd_kcontrol *kcontrol,
612 struct snd_ctl_elem_value *ucontrol)
613 {
614 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
615 struct rv1106_codec_priv *rv1106 = snd_soc_component_get_drvdata(component);
616 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
617 unsigned int value;
618
619 if (e->shift_l) {
620 /* ADC MIC Right Mute/Work Infos */
621 regmap_read(rv1106->regmap, ACODEC_ADC_BIST_MODE_SEL, &value);
622 rv1106->mic_mute_r = (value & ACODEC_ADC_R_BIST_SINE) >>
623 ACODEC_ADC_R_BIST_SFT;
624 ucontrol->value.integer.value[0] = rv1106->mic_mute_r;
625 } else {
626 /* ADC MIC Left Mute/Work Infos */
627 regmap_read(rv1106->regmap, ACODEC_ADC_BIST_MODE_SEL, &value);
628 rv1106->mic_mute_l = (value & ACODEC_ADC_L_BIST_SINE) >>
629 ACODEC_ADC_L_BIST_SFT;
630 ucontrol->value.integer.value[0] = rv1106->mic_mute_l;
631 }
632
633 return 0;
634 }
635
rv1106_codec_mic_mute_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)636 static int rv1106_codec_mic_mute_put(struct snd_kcontrol *kcontrol,
637 struct snd_ctl_elem_value *ucontrol)
638 {
639 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
640 struct rv1106_codec_priv *rv1106 = snd_soc_component_get_drvdata(component);
641 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
642 unsigned int value;
643
644 if (e->shift_l) {
645 /* ADC MIC Right Mute/Work Configuration */
646 value = ucontrol->value.integer.value[0] << ACODEC_ADC_R_BIST_SFT;
647 regmap_update_bits(rv1106->regmap, ACODEC_ADC_BIST_MODE_SEL,
648 ACODEC_ADC_R_BIST_SINE,
649 value);
650 rv1106->mic_mute_r = ucontrol->value.integer.value[0];
651 } else {
652 /* ADC MIC Left Mute/Work Configuration */
653 value = ucontrol->value.integer.value[0] << ACODEC_ADC_L_BIST_SFT;
654 regmap_update_bits(rv1106->regmap, ACODEC_ADC_BIST_MODE_SEL,
655 ACODEC_ADC_L_BIST_SINE,
656 value);
657 rv1106->mic_mute_l = ucontrol->value.integer.value[0];
658 }
659
660 return 0;
661 }
662
rv1106_codec_micbias_volts_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)663 static int rv1106_codec_micbias_volts_get(struct snd_kcontrol *kcontrol,
664 struct snd_ctl_elem_value *ucontrol)
665 {
666 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
667 struct rv1106_codec_priv *rv1106 = snd_soc_component_get_drvdata(component);
668
669 ucontrol->value.integer.value[0] = rv1106->micbias_volt;
670
671 return 0;
672 }
673
rv1106_codec_micbias_volts_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)674 static int rv1106_codec_micbias_volts_put(struct snd_kcontrol *kcontrol,
675 struct snd_ctl_elem_value *ucontrol)
676 {
677 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
678 struct rv1106_codec_priv *rv1106 = snd_soc_component_get_drvdata(component);
679 unsigned int volt = ucontrol->value.integer.value[0];
680 int ret;
681
682 ret = check_micbias(volt);
683 if (ret < 0) {
684 dev_err(rv1106->plat_dev, "Invalid micbias volt: %d\n",
685 volt);
686 return ret;
687 }
688
689 regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL0,
690 ACODEC_ADC_LEVEL_RANGE_MICBIAS_MSK,
691 volt);
692
693 rv1106->micbias_volt = volt;
694
695 return 0;
696 }
697
rv1106_codec_main_micbias_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)698 static int rv1106_codec_main_micbias_get(struct snd_kcontrol *kcontrol,
699 struct snd_ctl_elem_value *ucontrol)
700 {
701 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
702 struct rv1106_codec_priv *rv1106 = snd_soc_component_get_drvdata(component);
703
704 ucontrol->value.integer.value[0] = rv1106->micbias_enable;
705
706 return 0;
707 }
708
rv1106_codec_main_micbias_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)709 static int rv1106_codec_main_micbias_put(struct snd_kcontrol *kcontrol,
710 struct snd_ctl_elem_value *ucontrol)
711 {
712 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
713 struct rv1106_codec_priv *rv1106 = snd_soc_component_get_drvdata(component);
714 unsigned int on = ucontrol->value.integer.value[0];
715
716 if (on) {
717 if (!rv1106->micbias_enable)
718 rv1106_codec_micbias_enable(rv1106, rv1106->micbias_volt);
719 } else {
720 if (rv1106->micbias_enable)
721 rv1106_codec_micbias_disable(rv1106);
722 }
723
724 return 0;
725 }
726
rv1106_codec_mic_gain_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)727 static int rv1106_codec_mic_gain_get(struct snd_kcontrol *kcontrol,
728 struct snd_ctl_elem_value *ucontrol)
729 {
730 return snd_soc_get_volsw_range(kcontrol, ucontrol);
731 }
732
rv1106_codec_mic_gain_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)733 static int rv1106_codec_mic_gain_put(struct snd_kcontrol *kcontrol,
734 struct snd_ctl_elem_value *ucontrol)
735 {
736 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
737 struct rv1106_codec_priv *rv1106 = snd_soc_component_get_drvdata(component);
738 unsigned int index = ucontrol->value.integer.value[0];
739
740 /*
741 * From the TRM, the gain of MIC Boost only supports:
742 * 0dB (index == 1)
743 * 20dB(index == 2)
744 * 12dB(index == 3)
745 */
746 if ((index < ACODEC_ADC_MIC_GAIN_MIN) ||
747 (index > ACODEC_ADC_MIC_GAIN_MAX)) {
748 dev_err(rv1106->plat_dev, "%s: invalid mic gain index: %d\n",
749 __func__, index);
750 return -EINVAL;
751 }
752
753 return snd_soc_put_volsw_range(kcontrol, ucontrol);
754 }
755
rv1106_codec_hpf_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)756 static int rv1106_codec_hpf_get(struct snd_kcontrol *kcontrol,
757 struct snd_ctl_elem_value *ucontrol)
758 {
759 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
760 struct rv1106_codec_priv *rv1106 = snd_soc_component_get_drvdata(component);
761 unsigned int value;
762
763 regmap_read(rv1106->regmap, ACODEC_ADC_HPF_PGA_CTL, &value);
764 if (value & ACODEC_ADC_HPF_MSK)
765 rv1106->hpf_cutoff = 1;
766 else
767 rv1106->hpf_cutoff = 0;
768
769 ucontrol->value.integer.value[0] = rv1106->hpf_cutoff;
770
771 return 0;
772 }
773
rv1106_codec_hpf_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)774 static int rv1106_codec_hpf_put(struct snd_kcontrol *kcontrol,
775 struct snd_ctl_elem_value *ucontrol)
776 {
777 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
778 struct rv1106_codec_priv *rv1106 = snd_soc_component_get_drvdata(component);
779 unsigned int value = ucontrol->value.integer.value[0];
780
781 if (value) {
782 /* Enable high pass filter for ADCs */
783 regmap_update_bits(rv1106->regmap, ACODEC_ADC_HPF_PGA_CTL,
784 ACODEC_ADC_HPF_MSK,
785 ACODEC_ADC_HPF_EN);
786 } else {
787 /* Disable high pass filter for ADCs. */
788 regmap_update_bits(rv1106->regmap, ACODEC_ADC_HPF_PGA_CTL,
789 ACODEC_ADC_HPF_MSK,
790 ACODEC_ADC_HPF_DIS);
791 }
792
793 rv1106->hpf_cutoff = value;
794
795 return 0;
796 }
797
rv1106_codec_pa_ctrl(struct rv1106_codec_priv * rv1106,bool on)798 static void rv1106_codec_pa_ctrl(struct rv1106_codec_priv *rv1106, bool on)
799 {
800 if (!rv1106->pa_ctl_gpio)
801 return;
802
803 if (on) {
804 gpiod_direction_output(rv1106->pa_ctl_gpio, on);
805 msleep(rv1106->pa_ctl_delay_ms);
806 } else {
807 gpiod_direction_output(rv1106->pa_ctl_gpio, on);
808 }
809 }
810
rv1106_codec_reset(struct snd_soc_component * component)811 static int rv1106_codec_reset(struct snd_soc_component *component)
812 {
813 struct rv1106_codec_priv *rv1106 = snd_soc_component_get_drvdata(component);
814
815 reset_control_assert(rv1106->reset);
816 usleep_range(10000, 11000); /* estimated value */
817 reset_control_deassert(rv1106->reset);
818
819 regmap_write(rv1106->regmap, ACODEC_GLB_CON, 0x00);
820 usleep_range(10000, 11000); /* estimated value */
821 regmap_write(rv1106->regmap, ACODEC_GLB_CON,
822 ACODEC_CODEC_SYS_WORK |
823 ACODEC_CODEC_CORE_WORK);
824
825 return 0;
826 }
827
rv1106_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)828 static int rv1106_set_bias_level(struct snd_soc_component *component,
829 enum snd_soc_bias_level level)
830 {
831 struct rv1106_codec_priv *rv1106 = snd_soc_component_get_drvdata(component);
832
833 switch (level) {
834 case SND_SOC_BIAS_ON:
835 break;
836 case SND_SOC_BIAS_PREPARE:
837 break;
838 case SND_SOC_BIAS_STANDBY:
839 regcache_cache_only(rv1106->regmap, false);
840 regcache_sync(rv1106->regmap);
841 break;
842 case SND_SOC_BIAS_OFF:
843 break;
844 }
845
846 return 0;
847 }
848
rv1106_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)849 static int rv1106_set_dai_fmt(struct snd_soc_dai *codec_dai,
850 unsigned int fmt)
851 {
852 struct snd_soc_component *component = codec_dai->component;
853 struct rv1106_codec_priv *rv1106 = snd_soc_component_get_drvdata(component);
854 unsigned int adc_aif1 = 0, adc_aif2 = 0, dac_aif1 = 0, dac_aif2 = 0;
855
856 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
857 case SND_SOC_DAIFMT_CBS_CFS:
858 adc_aif2 |= ACODEC_ADC_IO_MODE_SLAVE;
859 adc_aif2 |= ACODEC_ADC_MODE_SLAVE;
860 dac_aif2 |= ACODEC_DAC_IO_MODE_SLAVE;
861 dac_aif2 |= ACODEC_DAC_MODE_SLAVE;
862 break;
863 case SND_SOC_DAIFMT_CBM_CFM:
864 adc_aif2 |= ACODEC_ADC_IO_MODE_MASTER;
865 adc_aif2 |= ACODEC_ADC_MODE_MASTER;
866 dac_aif2 |= ACODEC_DAC_IO_MODE_MASTER;
867 dac_aif2 |= ACODEC_DAC_MODE_MASTER;
868 break;
869 default:
870 return -EINVAL;
871 }
872
873 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
874 case SND_SOC_DAIFMT_DSP_A:
875 adc_aif1 |= ACODEC_ADC_I2S_MODE_PCM;
876 dac_aif1 |= ACODEC_DAC_I2S_MODE_PCM;
877 break;
878 case SND_SOC_DAIFMT_I2S:
879 adc_aif1 |= ACODEC_ADC_I2S_MODE_I2S;
880 dac_aif1 |= ACODEC_DAC_I2S_MODE_I2S;
881 break;
882 case SND_SOC_DAIFMT_RIGHT_J:
883 adc_aif1 |= ACODEC_ADC_I2S_MODE_RJ;
884 dac_aif1 |= ACODEC_DAC_I2S_MODE_RJ;
885 break;
886 case SND_SOC_DAIFMT_LEFT_J:
887 adc_aif1 |= ACODEC_ADC_I2S_MODE_LJ;
888 dac_aif1 |= ACODEC_DAC_I2S_MODE_LJ;
889 break;
890 default:
891 return -EINVAL;
892 }
893
894 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
895 case SND_SOC_DAIFMT_NB_NF:
896 adc_aif1 |= ACODEC_ADC_I2S_LRC_POL_NORMAL;
897 adc_aif2 |= ACODEC_ADC_I2S_BIT_CLK_POL_NORMAL;
898 dac_aif1 |= ACODEC_DAC_I2S_LRC_POL_NORMAL;
899 dac_aif2 |= ACODEC_DAC_I2S_BIT_CLK_POL_NORMAL;
900 break;
901 case SND_SOC_DAIFMT_IB_IF:
902 adc_aif1 |= ACODEC_ADC_I2S_LRC_POL_REVERSAL;
903 adc_aif2 |= ACODEC_ADC_I2S_BIT_CLK_POL_REVERSAL;
904 dac_aif1 |= ACODEC_DAC_I2S_LRC_POL_REVERSAL;
905 dac_aif2 |= ACODEC_DAC_I2S_BIT_CLK_POL_REVERSAL;
906 break;
907 case SND_SOC_DAIFMT_IB_NF:
908 adc_aif1 |= ACODEC_ADC_I2S_LRC_POL_NORMAL;
909 adc_aif2 |= ACODEC_ADC_I2S_BIT_CLK_POL_REVERSAL;
910 dac_aif1 |= ACODEC_DAC_I2S_LRC_POL_NORMAL;
911 dac_aif2 |= ACODEC_DAC_I2S_BIT_CLK_POL_REVERSAL;
912 break;
913 case SND_SOC_DAIFMT_NB_IF:
914 adc_aif1 |= ACODEC_ADC_I2S_LRC_POL_REVERSAL;
915 adc_aif2 |= ACODEC_ADC_I2S_BIT_CLK_POL_NORMAL;
916 dac_aif1 |= ACODEC_DAC_I2S_LRC_POL_REVERSAL;
917 dac_aif2 |= ACODEC_DAC_I2S_BIT_CLK_POL_NORMAL;
918 break;
919 default:
920 return -EINVAL;
921 }
922
923 regmap_update_bits(rv1106->regmap, ACODEC_ADC_I2S_CTL0,
924 ACODEC_ADC_I2S_LRC_POL_MSK |
925 ACODEC_ADC_I2S_MODE_MSK,
926 adc_aif1);
927 regmap_update_bits(rv1106->regmap, ACODEC_ADC_I2S_CTL1,
928 ACODEC_ADC_IO_MODE_MSK |
929 ACODEC_ADC_MODE_MSK |
930 ACODEC_ADC_I2S_BIT_CLK_POL_MSK,
931 adc_aif2);
932
933 regmap_update_bits(rv1106->regmap, ACODEC_DAC_I2S_CTL0,
934 ACODEC_DAC_I2S_LRC_POL_MSK |
935 ACODEC_DAC_I2S_MODE_MSK,
936 dac_aif1);
937 regmap_update_bits(rv1106->regmap, ACODEC_ADC_I2S_CTL1,
938 ACODEC_DAC_IO_MODE_MSK |
939 ACODEC_DAC_MODE_MSK |
940 ACODEC_DAC_I2S_BIT_CLK_POL_MSK,
941 dac_aif2);
942
943 return 0;
944 }
945
rv1106_codec_dac_dig_config(struct rv1106_codec_priv * rv1106,struct snd_pcm_hw_params * params)946 static int rv1106_codec_dac_dig_config(struct rv1106_codec_priv *rv1106,
947 struct snd_pcm_hw_params *params)
948 {
949 unsigned int dac_aif1 = 0, dac_aif2 = 0;
950
951 switch (params_format(params)) {
952 case SNDRV_PCM_FORMAT_S16_LE:
953 dac_aif1 |= ACODEC_DAC_I2S_VALID_LEN_16BITS;
954 break;
955 case SNDRV_PCM_FORMAT_S20_3LE:
956 dac_aif1 |= ACODEC_DAC_I2S_VALID_LEN_20BITS;
957 break;
958 case SNDRV_PCM_FORMAT_S24_LE:
959 dac_aif1 |= ACODEC_DAC_I2S_VALID_LEN_24BITS;
960 break;
961 case SNDRV_PCM_FORMAT_S32_LE:
962 dac_aif1 |= ACODEC_DAC_I2S_VALID_LEN_32BITS;
963 break;
964 default:
965 return -EINVAL;
966 }
967
968 dac_aif1 |= ACODEC_DAC_I2S_LR_NORMAL;
969 dac_aif2 |= ACODEC_DAC_I2S_WORK;
970
971 regmap_update_bits(rv1106->regmap, ACODEC_DAC_I2S_CTL0,
972 ACODEC_DAC_I2S_VALID_LEN_MSK |
973 ACODEC_DAC_I2S_LR_MSK,
974 dac_aif1);
975 regmap_update_bits(rv1106->regmap, ACODEC_DAC_I2S_CTL1,
976 ACODEC_DAC_I2S_MSK,
977 dac_aif2);
978
979 return 0;
980 }
981
rv1106_codec_adc_dig_config(struct rv1106_codec_priv * rv1106,struct snd_pcm_hw_params * params)982 static int rv1106_codec_adc_dig_config(struct rv1106_codec_priv *rv1106,
983 struct snd_pcm_hw_params *params)
984 {
985 unsigned int adc_aif1 = 0, adc_aif2 = 0;
986
987 switch (params_format(params)) {
988 case SNDRV_PCM_FORMAT_S16_LE:
989 adc_aif1 |= ACODEC_ADC_I2S_VALID_LEN_16BITS;
990 break;
991 case SNDRV_PCM_FORMAT_S20_3LE:
992 adc_aif1 |= ACODEC_ADC_I2S_VALID_LEN_20BITS;
993 break;
994 case SNDRV_PCM_FORMAT_S24_LE:
995 adc_aif1 |= ACODEC_ADC_I2S_VALID_LEN_24BITS;
996 break;
997 case SNDRV_PCM_FORMAT_S32_LE:
998 adc_aif1 |= ACODEC_ADC_I2S_VALID_LEN_32BITS;
999 break;
1000 default:
1001 return -EINVAL;
1002 }
1003
1004 adc_aif1 |= ACODEC_ADC_I2S_DATA_SEL_NORMAL;
1005 adc_aif2 |= ACODEC_ADC_I2S_WORK;
1006
1007 regmap_update_bits(rv1106->regmap, ACODEC_ADC_I2S_CTL0,
1008 ACODEC_ADC_I2S_VALID_LEN_MSK |
1009 ACODEC_ADC_I2S_DATA_SEL_MSK,
1010 adc_aif1);
1011 regmap_update_bits(rv1106->regmap, ACODEC_ADC_I2S_CTL1,
1012 ACODEC_ADC_I2S_MSK,
1013 adc_aif2);
1014
1015 return 0;
1016 }
1017
rv1106_mute_stream(struct snd_soc_dai * dai,int mute,int stream)1018 static int rv1106_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
1019 {
1020 struct snd_soc_component *component = dai->component;
1021 struct rv1106_codec_priv *rv1106 = snd_soc_component_get_drvdata(component);
1022
1023 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1024 if (mute) {
1025 /* Mute DAC HPMIX/LINEOUT */
1026 regmap_update_bits(rv1106->regmap,
1027 ACODEC_DAC_ANA_CTL1,
1028 ACODEC_DAC_L_LINEOUT_MUTE_MSK,
1029 ACODEC_DAC_L_LINEOUT_MUTE);
1030 regmap_update_bits(rv1106->regmap,
1031 ACODEC_DAC_HPMIX_CTL,
1032 ACODEC_DAC_HPMIX_MUTE_MSK,
1033 ACODEC_DAC_HPMIX_MUTE);
1034 rv1106_codec_pa_ctrl(rv1106, false);
1035 } else {
1036 /* Unmute DAC HPMIX/LINEOUT */
1037 regmap_update_bits(rv1106->regmap,
1038 ACODEC_DAC_HPMIX_CTL,
1039 ACODEC_DAC_HPMIX_MUTE_MSK,
1040 ACODEC_DAC_HPMIX_WORK);
1041 regmap_update_bits(rv1106->regmap,
1042 ACODEC_DAC_L_LINEOUT_MUTE_MSK,
1043 ACODEC_DAC_MUTE_MSK,
1044 ACODEC_DAC_L_LINEOUT_WORK);
1045 rv1106_codec_pa_ctrl(rv1106, true);
1046 }
1047 }
1048
1049 return 0;
1050 }
1051
rv1106_codec_dac_enable(struct rv1106_codec_priv * rv1106)1052 static int rv1106_codec_dac_enable(struct rv1106_codec_priv *rv1106)
1053 {
1054 /* Step 01 */
1055 regmap_update_bits(rv1106->regmap, ACODEC_DAC_ANA_CTL0,
1056 ACODEC_DAC_IBIAS_MSK,
1057 ACODEC_DAC_IBIAS_EN);
1058 udelay(20);
1059
1060 /* Step 02 */
1061 regmap_update_bits(rv1106->regmap, ACODEC_DAC_ANA_CTL0,
1062 ACODEC_DAC_L_REF_VOL_BUF_MSK,
1063 ACODEC_DAC_L_REF_VOL_BUF_EN);
1064 /* Waiting the stable reference voltage */
1065 usleep_range(1000, 2000);
1066
1067 /* Step 03 */
1068 regmap_update_bits(rv1106->regmap, ACODEC_DAC_ANA_CTL1,
1069 ACODEC_DAC_L_LINEOUT_MSK,
1070 ACODEC_DAC_L_LINEOUT_EN);
1071 udelay(20);
1072
1073 /* Step 04 */
1074 regmap_update_bits(rv1106->regmap, ACODEC_DAC_ANA_CTL1,
1075 ACODEC_DAC_L_LINEOUT_SIGNAL_MSK,
1076 ACODEC_DAC_L_LINEOUT_SIGNAL_WORK);
1077 udelay(20);
1078
1079 /* Step 05 */
1080 regmap_update_bits(rv1106->regmap, ACODEC_DAC_HPMIX_CTL,
1081 ACODEC_DAC_HPMIX_MSK,
1082 ACODEC_DAC_HPMIX_EN);
1083 udelay(20);
1084
1085 /* Step 06 */
1086 regmap_update_bits(rv1106->regmap, ACODEC_DAC_HPMIX_CTL,
1087 ACODEC_DAC_HPMIX_MDL_MSK,
1088 ACODEC_DAC_HPMIX_MDL_WORK);
1089 udelay(20);
1090
1091 /* Step 07 */
1092 regmap_update_bits(rv1106->regmap, ACODEC_DAC_HPMIX_CTL,
1093 ACODEC_DAC_HPMIX_SEL_MSK,
1094 ACODEC_DAC_HPMIX_I2S);
1095 /* Waiting HPMIX be stable */
1096 usleep_range(18000, 20000);
1097
1098 /* Step 08 */
1099 regmap_update_bits(rv1106->regmap, ACODEC_DAC_ANA_CTL0,
1100 ACODEC_DAC_L_REF_VOL_MSK,
1101 ACODEC_DAC_L_REF_VOL_EN);
1102 udelay(20);
1103
1104 /* Step 09 */
1105 regmap_update_bits(rv1106->regmap, ACODEC_DAC_ANA_CTL0,
1106 ACODEC_DAC_L_CLK_MSK,
1107 ACODEC_DAC_L_CLK_EN);
1108 udelay(20);
1109
1110 /* Step 10 */
1111 regmap_update_bits(rv1106->regmap, ACODEC_DAC_ANA_CTL0,
1112 ACODEC_DAC_SRC_SIGNAL_MSK,
1113 ACODEC_DAC_SRC_SIGNAL_EN);
1114 udelay(20);
1115
1116 /* Step 11 */
1117 regmap_update_bits(rv1106->regmap, ACODEC_DAC_ANA_CTL0,
1118 ACODEC_DAC_L_SIGNAL_MSK,
1119 ACODEC_DAC_L_SIGNAL_WORK);
1120 udelay(20);
1121
1122 /* Step 12 */
1123 regmap_update_bits(rv1106->regmap, ACODEC_DAC_HPMIX_CTL,
1124 ACODEC_DAC_HPMIX_MUTE_MSK,
1125 ACODEC_DAC_HPMIX_WORK);
1126 udelay(20);
1127
1128 /* Step 13 */
1129 regmap_update_bits(rv1106->regmap, ACODEC_DAC_ANA_CTL1,
1130 ACODEC_DAC_L_LINEOUT_MUTE_MSK,
1131 ACODEC_DAC_L_LINEOUT_WORK);
1132
1133 /* Skip setting gains that Step 14/15 */
1134
1135 rv1106->dac_enable = true;
1136 return 0;
1137 }
1138
rv1106_codec_dac_disable(struct rv1106_codec_priv * rv1106)1139 static int rv1106_codec_dac_disable(struct rv1106_codec_priv *rv1106)
1140 {
1141 /* Step 01 */
1142 /* Skip cleaning the gain to GAIN_LINEOUTL */
1143
1144 /* Step 02 */
1145 regmap_update_bits(rv1106->regmap, ACODEC_DAC_ANA_CTL1,
1146 ACODEC_DAC_L_LINEOUT_MUTE_MSK,
1147 ACODEC_DAC_L_LINEOUT_MUTE);
1148
1149 /* Step 03 */
1150 regmap_update_bits(rv1106->regmap, ACODEC_DAC_ANA_CTL1,
1151 ACODEC_DAC_L_LINEOUT_SIGNAL_MSK,
1152 ACODEC_DAC_L_LINEOUT_SIGNAL_INIT);
1153 /* Step 04 */
1154 regmap_update_bits(rv1106->regmap, ACODEC_DAC_ANA_CTL1,
1155 ACODEC_DAC_L_LINEOUT_MSK,
1156 ACODEC_DAC_L_LINEOUT_DIS);
1157 /* Step 05 */
1158 regmap_update_bits(rv1106->regmap, ACODEC_DAC_HPMIX_CTL,
1159 ACODEC_DAC_HPMIX_MUTE_MSK,
1160 ACODEC_DAC_HPMIX_MUTE);
1161 /* Step 06 */
1162 regmap_update_bits(rv1106->regmap, ACODEC_DAC_HPMIX_CTL,
1163 ACODEC_DAC_HPMIX_MDL_MSK,
1164 ACODEC_DAC_HPMIX_MDL_INIT);
1165 /* Step 07 */
1166 regmap_update_bits(rv1106->regmap, ACODEC_DAC_HPMIX_CTL,
1167 ACODEC_DAC_HPMIX_MSK,
1168 ACODEC_DAC_HPMIX_DIS);
1169 /* Step 08 */
1170 regmap_update_bits(rv1106->regmap, ACODEC_DAC_ANA_CTL0,
1171 ACODEC_DAC_SRC_SIGNAL_MSK,
1172 ACODEC_DAC_SRC_SIGNAL_DIS);
1173 /* Step 09 */
1174 regmap_update_bits(rv1106->regmap, ACODEC_DAC_ANA_CTL0,
1175 ACODEC_DAC_L_CLK_MSK,
1176 ACODEC_DAC_L_CLK_DIS);
1177
1178 /* Step 10 */
1179 regmap_update_bits(rv1106->regmap, ACODEC_DAC_ANA_CTL0,
1180 ACODEC_DAC_L_REF_VOL_MSK,
1181 ACODEC_DAC_L_REF_VOL_DIS);
1182 /* Step 11 */
1183 regmap_update_bits(rv1106->regmap, ACODEC_DAC_ANA_CTL0,
1184 ACODEC_DAC_L_REF_VOL_BUF_MSK,
1185 ACODEC_DAC_L_REF_VOL_BUF_DIS);
1186
1187 /* Step 12 */
1188 regmap_update_bits(rv1106->regmap, ACODEC_DAC_ANA_CTL0,
1189 ACODEC_DAC_IBIAS_MSK,
1190 ACODEC_DAC_IBIAS_DIS);
1191
1192 /* Step 13 */
1193 regmap_update_bits(rv1106->regmap, ACODEC_DAC_ANA_CTL0,
1194 ACODEC_DAC_L_SIGNAL_MSK,
1195 ACODEC_DAC_L_SIGNAL_INIT);
1196
1197
1198 rv1106->dac_enable = false;
1199
1200 return 0;
1201 }
1202
rv1106_codec_power_on(struct rv1106_codec_priv * rv1106)1203 static int rv1106_codec_power_on(struct rv1106_codec_priv *rv1106)
1204 {
1205 /* vendor step 1 */
1206 regmap_update_bits(rv1106->regmap, ACODEC_DAC_ANA_CTL0,
1207 ACODEC_DAC_L_REF_POP_SOUND_MSK,
1208 ACODEC_DAC_L_REF_POP_SOUND_WORK);
1209 /* vendor step 2. Charging */
1210 regmap_update_bits(rv1106->regmap, ACODEC_CURRENT_CHARGE_CTL,
1211 ACODEC_ADC_CURRENT_CHARGE_MSK,
1212 ACODEC_ADC_SEL_I(0xff));
1213 /* vendor step 3. Supply the power of the analog part. */
1214 /* vendor step 4 */
1215 regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL0,
1216 ACODEC_ADC_REF_VOL_MSK, ACODEC_ADC_REF_VOL_EN);
1217 /* vendor step 5. Wait charging completed */
1218 msleep(20);
1219 /* vendor step 6 */
1220 regmap_update_bits(rv1106->regmap, ACODEC_CURRENT_CHARGE_CTL,
1221 ACODEC_ADC_CURRENT_CHARGE_MSK,
1222 ACODEC_ADC_SEL_I(0x02));
1223 return 0;
1224 }
1225
rv1106_codec_power_off(struct rv1106_codec_priv * rv1106)1226 static int rv1106_codec_power_off(struct rv1106_codec_priv *rv1106)
1227 {
1228 /*
1229 * 0. Keep the power on and disable the DAC and ADC path.
1230 */
1231
1232 /* vendor step 1 */
1233 regmap_update_bits(rv1106->regmap, ACODEC_CURRENT_CHARGE_CTL,
1234 ACODEC_ADC_CURRENT_CHARGE_MSK,
1235 ACODEC_ADC_SEL_I(0xff));
1236 /* vendor step 3 */
1237 regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL0,
1238 ACODEC_ADC_REF_VOL_MSK,
1239 ACODEC_ADC_REF_VOL_DIS);
1240 /* vendor step 3. Wait until the voltage of VCM keep stable at AGND. */
1241 msleep(20);
1242
1243 return 0;
1244 }
1245
rv1106_codec_adc_i2s_route(struct rv1106_codec_priv * rv1106)1246 static int rv1106_codec_adc_i2s_route(struct rv1106_codec_priv *rv1106)
1247 {
1248 regmap_write(rv1106->grf, PERI_GRF_PERI_CON1,
1249 ACODEC_MSK | ACODEC_EN);
1250 return 0;
1251 }
1252
check_micbias(int volt)1253 static int check_micbias(int volt)
1254 {
1255 switch (volt) {
1256 case ACODEC_ADC_MICBIAS_VOLT_0_975:
1257 case ACODEC_ADC_MICBIAS_VOLT_0_95:
1258 case ACODEC_ADC_MICBIAS_VOLT_0_925:
1259 case ACODEC_ADC_MICBIAS_VOLT_0_9:
1260 case ACODEC_ADC_MICBIAS_VOLT_0_875:
1261 case ACODEC_ADC_MICBIAS_VOLT_0_85:
1262 case ACODEC_ADC_MICBIAS_VOLT_0_825:
1263 case ACODEC_ADC_MICBIAS_VOLT_0_8:
1264 return 0;
1265 }
1266
1267 return -EINVAL;
1268 }
1269
rv1106_codec_micbias_enable(struct rv1106_codec_priv * rv1106,int volt)1270 static int rv1106_codec_micbias_enable(struct rv1106_codec_priv *rv1106,
1271 int volt)
1272 {
1273 int ret;
1274
1275 if (!rv1106->micbias_used)
1276 return 0;
1277
1278 /* 0. Power up the ACODEC and keep the AVDDH stable */
1279
1280 /* vendor step 1 */
1281 ret = check_micbias(volt);
1282 if (ret < 0) {
1283 dev_err(rv1106->plat_dev, "This is an invalid volt: %d\n",
1284 volt);
1285 return ret;
1286 }
1287
1288 regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL0,
1289 ACODEC_ADC_LEVEL_RANGE_MICBIAS_MSK,
1290 volt);
1291
1292 /* vendor step 4 */
1293 regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL0,
1294 ACODEC_MICBIAS_MSK,
1295 ACODEC_MICBIAS_WORK);
1296
1297 /* waiting micbias stabled*/
1298 mdelay(20);
1299
1300 rv1106->micbias_enable = true;
1301
1302 return 0;
1303 }
1304
rv1106_codec_micbias_disable(struct rv1106_codec_priv * rv1106)1305 static int rv1106_codec_micbias_disable(struct rv1106_codec_priv *rv1106)
1306 {
1307 if (!rv1106->micbias_used)
1308 return 0;
1309
1310 /* Step 0. Enable the MICBIAS and keep the Audio Codec stable */
1311 /* Do nothing */
1312
1313 /* vendor step 1 */
1314 regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL0,
1315 ACODEC_MICBIAS_MSK,
1316 ACODEC_MICBIAS_RST);
1317
1318 rv1106->micbias_enable = false;
1319
1320 return 0;
1321 }
1322
rv1106_codec_hpmix_gain_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1323 static int rv1106_codec_hpmix_gain_get(struct snd_kcontrol *kcontrol,
1324 struct snd_ctl_elem_value *ucontrol)
1325 {
1326 return snd_soc_get_volsw_range(kcontrol, ucontrol);
1327 }
1328
rv1106_codec_hpmix_gain_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1329 static int rv1106_codec_hpmix_gain_put(struct snd_kcontrol *kcontrol,
1330 struct snd_ctl_elem_value *ucontrol)
1331 {
1332 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1333 struct rv1106_codec_priv *rv1106 = snd_soc_component_get_drvdata(component);
1334 unsigned int index = ucontrol->value.integer.value[0];
1335
1336 if ((index < ACODEC_DAC_HPMIX_GAIN_MIN) ||
1337 (index > ACODEC_DAC_HPMIX_GAIN_MAX)) {
1338 dev_err(rv1106->plat_dev, "%s: invalid gain index: %d\n",
1339 __func__, index);
1340 return -EINVAL;
1341 }
1342
1343 return snd_soc_put_volsw_range(kcontrol, ucontrol);
1344 }
1345
rv1106_codec_adc_enable(struct rv1106_codec_priv * rv1106)1346 static int rv1106_codec_adc_enable(struct rv1106_codec_priv *rv1106)
1347 {
1348 unsigned int lr = using_adc_lr(rv1106->adc_mode);
1349 bool is_diff = using_adc_diff(rv1106->adc_mode);
1350 unsigned int agc_func_en;
1351 int ret;
1352
1353 dev_dbg(rv1106->plat_dev, "%s: soc_id: 0x%x lr: %d is_diff: %d\n",
1354 __func__, rv1106->soc_id, lr, is_diff);
1355
1356 ret = check_adc_mode(rv1106);
1357 if (ret < 0) {
1358 dev_err(rv1106->plat_dev,
1359 "%s - something error checking ADC mode: %d\n",
1360 __func__, ret);
1361 return ret;
1362 }
1363
1364 /* vendor step 00 */
1365 if (rv1106->soc_id == SOC_RV1103 && rv1106->adc_mode == DIFF_ADCL) {
1366 /* The ADCL is differential mode on rv1103 */
1367 regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL3,
1368 ACODEC_ADC_L_MODE_SEL_MSK,
1369 ACODEC_ADC_L_FULL_DIFFER2);
1370 } else if (rv1106->soc_id == SOC_RV1106 && is_diff) {
1371 /* The differential mode on rv1106 */
1372 regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL3,
1373 L(lr, ACODEC_ADC_L_MODE_SEL_MSK) |
1374 R(lr, ACODEC_ADC_R_MODE_SEL_MSK),
1375 L(lr, ACODEC_ADC_L_FULL_DIFFER) |
1376 R(lr, ACODEC_ADC_R_FULL_DIFFER));
1377 } else {
1378 /* The single-end mode */
1379 regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL3,
1380 L(lr, ACODEC_ADC_L_MODE_SEL_MSK) |
1381 R(lr, ACODEC_ADC_R_MODE_SEL_MSK),
1382 L(lr, ACODEC_ADC_L_SINGLE_END) |
1383 R(lr, ACODEC_ADC_R_SINGLE_END));
1384 }
1385
1386 /* vendor step 01 */
1387 regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL1,
1388 L(lr, ACODEC_ADC_L_MIC_MSK) |
1389 R(lr, ACODEC_ADC_R_MIC_MSK),
1390 L(lr, ACODEC_ADC_L_MIC_WORK) |
1391 R(lr, ACODEC_ADC_R_MIC_WORK));
1392
1393 /* vendor step 02 */
1394 regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL0,
1395 ACODEC_ADC_IBIAS_MSK,
1396 ACODEC_ADC_IBIAS_EN);
1397
1398 /* vendor step 03 */
1399 regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL1,
1400 L(lr, ACODEC_ADC_L_REF_VOL_BUF_MSK) |
1401 R(lr, ACODEC_ADC_R_REF_VOL_BUF_MSK),
1402 L(lr, ACODEC_ADC_L_REF_VOL_BUF_EN) |
1403 R(lr, ACODEC_ADC_R_REF_VOL_BUF_EN));
1404 /* waiting VREF be stable */
1405 msleep(100);
1406
1407 /* vendor step 04 */
1408 regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL3,
1409 L(lr, ACODEC_MIC_L_MSK) |
1410 R(lr, ACODEC_MIC_R_MSK),
1411 L(lr, ACODEC_MIC_L_EN) |
1412 R(lr, ACODEC_MIC_R_EN));
1413
1414 /* vendor step 05 */
1415 regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL3,
1416 L(lr, ACODEC_ADC_L_MSK) |
1417 R(lr, ACODEC_ADC_R_MSK),
1418 L(lr, ACODEC_ADC_L_EN) |
1419 R(lr, ACODEC_ADC_R_EN));
1420
1421 /* vendor step 06 */
1422 regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL6,
1423 L(lr, ACODEC_ADC_L_CLK_MSK) |
1424 R(lr, ACODEC_ADC_R_CLK_MSK),
1425 L(lr, ACODEC_ADC_L_CLK_WORK) |
1426 R(lr, ACODEC_ADC_R_CLK_WORK));
1427
1428 /* vendor step 07 */
1429 regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL6,
1430 L(lr, ACODEC_ADC_L_WORK) |
1431 R(lr, ACODEC_ADC_R_WORK),
1432 L(lr, ACODEC_ADC_L_WORK) |
1433 R(lr, ACODEC_ADC_R_WORK));
1434
1435 /* vendor step 08 */
1436 regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL6,
1437 L(lr, ACODEC_ADC_L_SIGNAL_EN) |
1438 R(lr, ACODEC_ADC_R_SIGNAL_EN),
1439 L(lr, ACODEC_ADC_L_SIGNAL_EN) |
1440 R(lr, ACODEC_ADC_R_SIGNAL_EN));
1441
1442 /* vendor step 09 */
1443 regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL6,
1444 L(lr, ACODEC_ADC_L_ALC_MSK) |
1445 R(lr, ACODEC_ADC_R_ALC_MSK),
1446 L(lr, ACODEC_ADC_L_ALC_WORK) |
1447 R(lr, ACODEC_ADC_R_ALC_WORK));
1448
1449 /* vendor step 10 */
1450 regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL1,
1451 L(lr, ACODEC_ADC_L_MIC_SIGNAL_MSK) |
1452 R(lr, ACODEC_ADC_R_MIC_SIGNAL_MSK),
1453 L(lr, ACODEC_ADC_L_MIC_SIGNAL_WORK) |
1454 R(lr, ACODEC_ADC_R_MIC_SIGNAL_WORK));
1455
1456 /* vendor step 11, configure GAIN_MICL/R by user */
1457
1458 /* vendor step 12, configure GAIN_ALCL/R by user */
1459
1460 /* vendor step 13 */
1461 regmap_read(rv1106->regmap, ACODEC_ADC_ANA_CTL1, &agc_func_en);
1462 if (agc_func_en & ACODEC_AGC_FUNC_SEL_EN) {
1463 regmap_update_bits(rv1106->regmap,
1464 ACODEC_ADC_ANA_CTL1,
1465 L(lr, ACODEC_ADC_L_ZERO_CROSS_DET_MSK) |
1466 R(lr, ACODEC_ADC_R_ZERO_CROSS_DET_MSK),
1467 L(lr, ACODEC_ADC_L_ZERO_CROSS_DET_EN) |
1468 R(lr, ACODEC_ADC_R_ZERO_CROSS_DET_EN));
1469 }
1470
1471 rv1106->adc_enable = true;
1472
1473 return 0;
1474 }
1475
rv1106_codec_adc_disable(struct rv1106_codec_priv * rv1106)1476 static int rv1106_codec_adc_disable(struct rv1106_codec_priv *rv1106)
1477 {
1478 /* vendor step 1 */
1479 regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL1,
1480 ACODEC_ADC_L_ZERO_CROSS_DET_MSK |
1481 ACODEC_ADC_R_ZERO_CROSS_DET_MSK,
1482 ACODEC_ADC_L_ZERO_CROSS_DET_DIS |
1483 ACODEC_ADC_R_ZERO_CROSS_DET_DIS);
1484
1485 /* vendor step 2 */
1486 regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL6,
1487 ACODEC_ADC_L_WORK |
1488 ACODEC_ADC_R_WORK,
1489 ACODEC_ADC_L_INIT |
1490 ACODEC_ADC_R_INIT);
1491
1492 /* vendor step 3 */
1493 regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL6,
1494 ACODEC_ADC_L_CLK_WORK |
1495 ACODEC_ADC_R_CLK_WORK,
1496 ACODEC_ADC_L_CLK_RST |
1497 ACODEC_ADC_R_CLK_RST);
1498
1499 /* vendor step 4 */
1500 regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL3,
1501 ACODEC_ADC_L_MSK |
1502 ACODEC_ADC_R_MSK,
1503 ACODEC_ADC_L_DIS |
1504 ACODEC_ADC_R_DIS);
1505
1506 /* vendor step 5 */
1507 regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL3,
1508 ACODEC_MIC_L_MSK |
1509 ACODEC_MIC_R_MSK,
1510 ACODEC_MIC_L_DIS |
1511 ACODEC_MIC_R_DIS);
1512
1513 /* vendor step 6 */
1514 regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL1,
1515 ACODEC_ADC_L_REF_VOL_BUF_MSK |
1516 ACODEC_ADC_R_REF_VOL_BUF_MSK,
1517 ACODEC_ADC_L_REF_VOL_BUF_DIS |
1518 ACODEC_ADC_R_REF_VOL_BUF_DIS);
1519
1520 /* vendor step 7 */
1521 regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL0,
1522 ACODEC_ADC_IBIAS_MSK,
1523 ACODEC_ADC_IBIAS_DIS);
1524
1525 /* vendor step 8 */
1526 regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL6,
1527 ACODEC_ADC_L_SIGNAL_EN |
1528 ACODEC_ADC_R_SIGNAL_EN,
1529 ACODEC_ADC_L_SIGNAL_DIS |
1530 ACODEC_ADC_R_SIGNAL_DIS);
1531
1532 /* vendor step 9 */
1533 regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL6,
1534 ACODEC_ADC_L_ALC_MSK |
1535 ACODEC_ADC_R_ALC_MSK,
1536 ACODEC_ADC_L_ALC_INIT |
1537 ACODEC_ADC_R_ALC_INIT);
1538
1539 /* vendor step 10 */
1540 regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL1,
1541 ACODEC_ADC_L_MIC_SIGNAL_MSK |
1542 ACODEC_ADC_R_MIC_SIGNAL_MSK,
1543 ACODEC_ADC_L_MIC_SIGNAL_INIT |
1544 ACODEC_ADC_R_MIC_SIGNAL_INIT);
1545
1546 rv1106->adc_enable = false;
1547
1548 return 0;
1549 }
1550
rv1106_codec_open_capture(struct rv1106_codec_priv * rv1106)1551 static int rv1106_codec_open_capture(struct rv1106_codec_priv *rv1106)
1552 {
1553 rv1106_codec_adc_enable(rv1106);
1554
1555 return 0;
1556 }
1557
rv1106_codec_close_capture(struct rv1106_codec_priv * rv1106)1558 static int rv1106_codec_close_capture(struct rv1106_codec_priv *rv1106)
1559 {
1560 rv1106_codec_adc_disable(rv1106);
1561 return 0;
1562 }
1563
rv1106_codec_open_playback(struct rv1106_codec_priv * rv1106)1564 static int rv1106_codec_open_playback(struct rv1106_codec_priv *rv1106)
1565 {
1566 rv1106_codec_dac_enable(rv1106);
1567 return 0;
1568 }
1569
rv1106_codec_close_playback(struct rv1106_codec_priv * rv1106)1570 static int rv1106_codec_close_playback(struct rv1106_codec_priv *rv1106)
1571 {
1572 rv1106_codec_dac_disable(rv1106);
1573 return 0;
1574 }
1575
rv1106_codec_dlp_down(struct rv1106_codec_priv * rv1106)1576 static int rv1106_codec_dlp_down(struct rv1106_codec_priv *rv1106)
1577 {
1578 rv1106_codec_micbias_disable(rv1106);
1579 rv1106_codec_power_off(rv1106);
1580 return 0;
1581 }
1582
rv1106_codec_dlp_up(struct rv1106_codec_priv * rv1106)1583 static int rv1106_codec_dlp_up(struct rv1106_codec_priv *rv1106)
1584 {
1585 rv1106_codec_power_on(rv1106);
1586 rv1106_codec_micbias_enable(rv1106, rv1106->micbias_volt);
1587 return 0;
1588 }
1589
rv1106_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1590 static int rv1106_hw_params(struct snd_pcm_substream *substream,
1591 struct snd_pcm_hw_params *params,
1592 struct snd_soc_dai *dai)
1593 {
1594 struct snd_soc_component *component = dai->component;
1595 struct rv1106_codec_priv *rv1106 = snd_soc_component_get_drvdata(component);
1596
1597 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1598 rv1106_codec_open_playback(rv1106);
1599 rv1106_codec_dac_dig_config(rv1106, params);
1600 } else {
1601 rv1106_codec_open_capture(rv1106);
1602 rv1106_codec_adc_dig_config(rv1106, params);
1603 }
1604
1605 return 0;
1606 }
1607
rv1106_pcm_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1608 static void rv1106_pcm_shutdown(struct snd_pcm_substream *substream,
1609 struct snd_soc_dai *dai)
1610 {
1611 struct snd_soc_component *component = dai->component;
1612 struct rv1106_codec_priv *rv1106 = snd_soc_component_get_drvdata(component);
1613
1614 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1615 rv1106_codec_close_playback(rv1106);
1616 else
1617 rv1106_codec_close_capture(rv1106);
1618
1619 regcache_cache_only(rv1106->regmap, false);
1620 regcache_sync(rv1106->regmap);
1621 }
1622
1623 static const struct snd_soc_dai_ops rv1106_dai_ops = {
1624 .hw_params = rv1106_hw_params,
1625 .set_fmt = rv1106_set_dai_fmt,
1626 .mute_stream = rv1106_mute_stream,
1627 .shutdown = rv1106_pcm_shutdown,
1628 };
1629
1630 static struct snd_soc_dai_driver rv1106_dai[] = {
1631 {
1632 .name = "rv1106-hifi",
1633 .id = ACODEC_HIFI,
1634 .playback = {
1635 .stream_name = "HiFi Playback",
1636 .channels_min = 1,
1637 .channels_max = 2,
1638 .rates = SNDRV_PCM_RATE_8000_192000,
1639 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
1640 SNDRV_PCM_FMTBIT_S20_3LE |
1641 SNDRV_PCM_FMTBIT_S24_LE |
1642 SNDRV_PCM_FMTBIT_S32_LE),
1643 },
1644 .capture = {
1645 .stream_name = "HiFi Capture",
1646 .channels_min = 1,
1647 .channels_max = 4,
1648 .rates = SNDRV_PCM_RATE_8000_192000,
1649 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
1650 SNDRV_PCM_FMTBIT_S20_3LE |
1651 SNDRV_PCM_FMTBIT_S24_LE |
1652 SNDRV_PCM_FMTBIT_S32_LE),
1653 },
1654 .ops = &rv1106_dai_ops,
1655 },
1656 };
1657
rv1106_suspend(struct snd_soc_component * component)1658 static int rv1106_suspend(struct snd_soc_component *component)
1659 {
1660 struct rv1106_codec_priv *rv1106 = snd_soc_component_get_drvdata(component);
1661
1662 rv1106_codec_dlp_down(rv1106);
1663 clk_disable_unprepare(rv1106->mclk_acodec);
1664 clk_disable_unprepare(rv1106->pclk_acodec);
1665 rv1106_set_bias_level(component, SND_SOC_BIAS_OFF);
1666 return 0;
1667 }
1668
rv1106_resume(struct snd_soc_component * component)1669 static int rv1106_resume(struct snd_soc_component *component)
1670 {
1671 struct rv1106_codec_priv *rv1106 = snd_soc_component_get_drvdata(component);
1672 int ret = 0;
1673
1674 ret = clk_prepare_enable(rv1106->pclk_acodec);
1675 if (ret < 0) {
1676 dev_err(rv1106->plat_dev,
1677 "Failed to enable acodec pclk_acodec: %d\n", ret);
1678 goto out;
1679 }
1680
1681 ret = clk_prepare_enable(rv1106->mclk_acodec);
1682 if (ret < 0) {
1683 dev_err(rv1106->plat_dev,
1684 "Failed to enable acodec mclk_acodec: %d\n", ret);
1685 goto out;
1686 }
1687
1688 rv1106_codec_dlp_up(rv1106);
1689 out:
1690 rv1106_set_bias_level(component, SND_SOC_BIAS_STANDBY);
1691 return ret;
1692 }
1693
rv1106_codec_default_gains(struct rv1106_codec_priv * rv1106)1694 static int rv1106_codec_default_gains(struct rv1106_codec_priv *rv1106)
1695 {
1696 int gainl, gainr;
1697
1698 /**
1699 * MIC Gain
1700 * 0dB (0x01)
1701 * 20dB (0x02)
1702 * 12dB (0x03)
1703 */
1704 if (rv1106->init_mic_gain == NOT_SPECIFIED) {
1705 gainl = ACODEC_ADC_L_MIC_GAIN_0DB;
1706 gainr = ACODEC_ADC_R_MIC_GAIN_0DB;
1707 } else {
1708 gainl = ((rv1106->init_mic_gain >> 4) & 0x03) << ACODEC_ADC_L_MIC_GAIN_SFT;
1709 gainr = ((rv1106->init_mic_gain >> 0) & 0x03) << ACODEC_ADC_R_MIC_GAIN_SFT;
1710 }
1711
1712 /* Prepare ADC gains */
1713 /* vendor step 12, set MIC PGA default gains */
1714 regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL2,
1715 ACODEC_ADC_L_MIC_GAIN_MSK |
1716 ACODEC_ADC_R_MIC_GAIN_MSK,
1717 gainl | gainr);
1718
1719 /**
1720 * ALC Gain (0dB: 0x06)
1721 * min: -9.0dB (0x00)
1722 * max: +37.5dB (0x1f)
1723 * step: +1.5dB
1724 */
1725 if (rv1106->init_alc_gain == NOT_SPECIFIED) {
1726 gainl = ACODEC_ADC_L_ALC_GAIN_0DB;
1727 gainr = ACODEC_ADC_R_ALC_GAIN_0DB;
1728 } else {
1729 gainl = ((rv1106->init_alc_gain >> 4) & 0x1f);
1730 gainr = ((rv1106->init_alc_gain >> 0) & 0x1f);
1731 }
1732 /* vendor step 13, set ALC default gains */
1733 regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL4,
1734 ACODEC_ADC_L_ALC_GAIN_MSK,
1735 gainl);
1736 regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL5,
1737 ACODEC_ADC_R_ALC_GAIN_MSK,
1738 gainr);
1739
1740 /* Prepare DAC gains */
1741 /* Step 19, set LINEOUT default gains */
1742 regmap_update_bits(rv1106->regmap, ACODEC_DAC_GAIN_SEL,
1743 ACODEC_DAC_DIG_GAIN_MSK,
1744 ACODEC_DAC_DIG_GAIN(ACODEC_DAC_DIG_0DB)); /* The calibrated fixed gain */
1745 /**
1746 * Lineout Gain (0dB: 0x1a)
1747 * min: -39.0dB (0x00)
1748 * max: +6.0dB (0x1f)
1749 * step: +1.5dB
1750 */
1751 if (rv1106->init_lineout_gain == NOT_SPECIFIED)
1752 gainl = ACODEC_DAC_LINEOUT_GAIN_0DB;
1753 else
1754 gainl = rv1106->init_lineout_gain & 0x1f;
1755 regmap_update_bits(rv1106->regmap, ACODEC_DAC_ANA_CTL2,
1756 ACODEC_DAC_LINEOUT_GAIN_MSK,
1757 gainl);
1758 return 0;
1759 }
1760
rv1106_codec_check_micbias(struct rv1106_codec_priv * rv1106,struct device_node * np)1761 static int rv1106_codec_check_micbias(struct rv1106_codec_priv *rv1106,
1762 struct device_node *np)
1763 {
1764 /* Check internal of acodec micbias */
1765 rv1106->micbias_used =
1766 of_property_read_bool(np, "acodec,micbias");
1767
1768 /* Using 0.9*AVDD by default */
1769 rv1106->micbias_volt = ACODEC_ADC_MICBIAS_VOLT_0_9;
1770
1771 return 0;
1772 }
1773
rv1106_codec_dapm_controls_prepare(struct rv1106_codec_priv * rv1106)1774 static int rv1106_codec_dapm_controls_prepare(struct rv1106_codec_priv *rv1106)
1775 {
1776 rv1106->adc_mode = DIFF_ADCL;
1777 rv1106->hpf_cutoff = 0;
1778 rv1106->agc_l = 0;
1779 rv1106->agc_r = 0;
1780 rv1106->agc_asr_l = AGC_ASR_96KHZ;
1781 rv1106->agc_asr_r = AGC_ASR_96KHZ;
1782
1783 return 0;
1784 }
1785
rv1106_codec_prepare(struct rv1106_codec_priv * rv1106)1786 static int rv1106_codec_prepare(struct rv1106_codec_priv *rv1106)
1787 {
1788 /* Clear registers for ADC and DAC */
1789 rv1106_codec_close_playback(rv1106);
1790 rv1106_codec_close_capture(rv1106);
1791 rv1106_codec_default_gains(rv1106);
1792 rv1106_codec_dapm_controls_prepare(rv1106);
1793
1794 return 0;
1795 }
1796
rv1106_probe(struct snd_soc_component * component)1797 static int rv1106_probe(struct snd_soc_component *component)
1798 {
1799 struct rv1106_codec_priv *rv1106 = snd_soc_component_get_drvdata(component);
1800
1801 rv1106->component = component;
1802 rv1106_codec_reset(component);
1803 rv1106_codec_dlp_up(rv1106);
1804 rv1106_codec_prepare(rv1106);
1805
1806 regcache_cache_only(rv1106->regmap, false);
1807 regcache_sync(rv1106->regmap);
1808
1809 return 0;
1810 }
1811
rv1106_remove(struct snd_soc_component * component)1812 static void rv1106_remove(struct snd_soc_component *component)
1813 {
1814 struct rv1106_codec_priv *rv1106 = snd_soc_component_get_drvdata(component);
1815
1816 rv1106_codec_pa_ctrl(rv1106, false);
1817 rv1106_codec_micbias_disable(rv1106);
1818 rv1106_codec_power_off(rv1106);
1819 regcache_cache_only(rv1106->regmap, false);
1820 regcache_sync(rv1106->regmap);
1821 }
1822
1823 static const struct snd_soc_component_driver soc_codec_dev_rv1106 = {
1824 .probe = rv1106_probe,
1825 .remove = rv1106_remove,
1826 .suspend = rv1106_suspend,
1827 .resume = rv1106_resume,
1828 .set_bias_level = rv1106_set_bias_level,
1829 .controls = rv1106_codec_dapm_controls,
1830 .num_controls = ARRAY_SIZE(rv1106_codec_dapm_controls),
1831 };
1832
1833 /* Set the default value or reset value */
1834 static const struct reg_default rv1106_codec_reg_defaults[] = {
1835 { ACODEC_RESET_CTL, 0x03 },
1836 };
1837
rv1106_codec_write_read_reg(struct device * dev,unsigned int reg)1838 static bool rv1106_codec_write_read_reg(struct device *dev, unsigned int reg)
1839 {
1840 /* All registers can be read / write */
1841 return true;
1842 }
1843
rv1106_codec_volatile_reg(struct device * dev,unsigned int reg)1844 static bool rv1106_codec_volatile_reg(struct device *dev, unsigned int reg)
1845 {
1846 /* All registers can be read / write */
1847 return true;
1848 }
1849
1850 static const struct regmap_config rv1106_codec_regmap_config = {
1851 .reg_bits = 32,
1852 .reg_stride = 4,
1853 .val_bits = 32,
1854 .max_register = ACODEC_REG_MAX,
1855 .writeable_reg = rv1106_codec_write_read_reg,
1856 .readable_reg = rv1106_codec_write_read_reg,
1857 .volatile_reg = rv1106_codec_volatile_reg,
1858 .reg_defaults = rv1106_codec_reg_defaults,
1859 .num_reg_defaults = ARRAY_SIZE(rv1106_codec_reg_defaults),
1860 .cache_type = REGCACHE_FLAT,
1861 };
1862
adc_enable_show(struct device * dev,struct device_attribute * attr,char * buf)1863 static ssize_t adc_enable_show(struct device *dev,
1864 struct device_attribute *attr,
1865 char *buf)
1866 {
1867 struct rv1106_codec_priv *rv1106 =
1868 container_of(dev, struct rv1106_codec_priv, dev);
1869
1870 return sprintf(buf, "%d\n", rv1106->adc_enable);
1871 }
1872
adc_enable_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1873 static ssize_t adc_enable_store(struct device *dev,
1874 struct device_attribute *attr,
1875 const char *buf, size_t count)
1876 {
1877 struct rv1106_codec_priv *rv1106 =
1878 container_of(dev, struct rv1106_codec_priv, dev);
1879 unsigned long enable;
1880 int ret = kstrtoul(buf, 10, &enable);
1881
1882 if (ret < 0) {
1883 dev_err(dev, "Invalid enable: %ld, ret: %d\n",
1884 enable, ret);
1885 return -EINVAL;
1886 }
1887
1888 if (enable)
1889 rv1106_codec_open_capture(rv1106);
1890 else
1891 rv1106_codec_close_capture(rv1106);
1892
1893 dev_info(dev, "ADC enable: %ld\n", enable);
1894
1895 return count;
1896 }
1897
dac_enable_show(struct device * dev,struct device_attribute * attr,char * buf)1898 static ssize_t dac_enable_show(struct device *dev,
1899 struct device_attribute *attr,
1900 char *buf)
1901 {
1902 struct rv1106_codec_priv *rv1106 =
1903 container_of(dev, struct rv1106_codec_priv, dev);
1904
1905 return sprintf(buf, "%d\n", rv1106->dac_enable);
1906 }
1907
dac_enable_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1908 static ssize_t dac_enable_store(struct device *dev,
1909 struct device_attribute *attr,
1910 const char *buf, size_t count)
1911 {
1912 struct rv1106_codec_priv *rv1106 =
1913 container_of(dev, struct rv1106_codec_priv, dev);
1914 unsigned long enable;
1915 int ret = kstrtoul(buf, 10, &enable);
1916
1917 if (ret < 0) {
1918 dev_err(dev, "Invalid enable: %ld, ret: %d\n",
1919 enable, ret);
1920 return -EINVAL;
1921 }
1922
1923 if (enable)
1924 rv1106_codec_open_playback(rv1106);
1925 else
1926 rv1106_codec_close_playback(rv1106);
1927
1928 dev_info(dev, "DAC enable: %ld\n", enable);
1929
1930 return count;
1931 }
1932
1933 static const struct device_attribute acodec_attrs[] = {
1934 __ATTR_RW(adc_enable),
1935 __ATTR_RW(dac_enable),
1936 };
1937
rv1106_codec_device_release(struct device * dev)1938 static void rv1106_codec_device_release(struct device *dev)
1939 {
1940 /* Do nothing */
1941 }
1942
rv1106_codec_sysfs_init(struct platform_device * pdev,struct rv1106_codec_priv * rv1106)1943 static int rv1106_codec_sysfs_init(struct platform_device *pdev,
1944 struct rv1106_codec_priv *rv1106)
1945 {
1946 struct device *dev = &rv1106->dev;
1947 int i;
1948
1949 dev->release = rv1106_codec_device_release;
1950 dev->parent = &pdev->dev;
1951 set_dev_node(dev, dev_to_node(&pdev->dev));
1952 dev_set_name(dev, "acodec_attrs");
1953
1954 if (device_register(dev)) {
1955 dev_err(&pdev->dev,
1956 "Register 'acodec_attrs' failed\n");
1957 dev->parent = NULL;
1958 return -ENOMEM;
1959 }
1960
1961 for (i = 0; i < ARRAY_SIZE(acodec_attrs); i++) {
1962 if (device_create_file(dev, &acodec_attrs[i])) {
1963 dev_err(&pdev->dev,
1964 "Create 'acodec_attrs' failed\n");
1965 device_unregister(dev);
1966 return -ENOMEM;
1967 }
1968 }
1969
1970 return 0;
1971 }
1972
rv1106_codec_sysfs_exit(struct rv1106_codec_priv * rv1106)1973 static int rv1106_codec_sysfs_exit(struct rv1106_codec_priv *rv1106)
1974 {
1975 struct device *dev = &rv1106->dev;
1976 int i;
1977
1978 for (i = 0; i < ARRAY_SIZE(acodec_attrs); i++)
1979 device_remove_file(dev, &acodec_attrs[i]);
1980
1981 device_unregister(dev);
1982 return 0;
1983 }
1984
1985 #if defined(CONFIG_DEBUG_FS)
rv1106_codec_debugfs_reg_show(struct seq_file * s,void * v)1986 static int rv1106_codec_debugfs_reg_show(struct seq_file *s, void *v)
1987 {
1988 struct rv1106_codec_priv *rv1106 = s->private;
1989 unsigned int i;
1990 unsigned int val;
1991
1992 for (i = ACODEC_RESET_CTL; i <= ACODEC_ADC_PGA_AGC_R_CTL9; i += 4) {
1993 regmap_read(rv1106->regmap, i, &val);
1994 if (!(i % 16))
1995 seq_printf(s, "\nR:%04x: ", i);
1996 seq_printf(s, "%08x ", val);
1997 }
1998
1999 seq_puts(s, "\n");
2000
2001 return 0;
2002 }
2003
rv1106_codec_debugfs_reg_operate(struct file * file,const char __user * buf,size_t count,loff_t * ppos)2004 static ssize_t rv1106_codec_debugfs_reg_operate(struct file *file,
2005 const char __user *buf,
2006 size_t count, loff_t *ppos)
2007 {
2008 struct rv1106_codec_priv *rv1106 =
2009 ((struct seq_file *)file->private_data)->private;
2010 unsigned int reg, val;
2011 char op;
2012 char kbuf[32];
2013 int ret;
2014
2015 if (count >= sizeof(kbuf))
2016 return -EINVAL;
2017
2018 if (copy_from_user(kbuf, buf, count))
2019 return -EFAULT;
2020 kbuf[count] = '\0';
2021
2022 ret = sscanf(kbuf, "%c,%x,%x", &op, ®, &val);
2023 if (ret != 3) {
2024 pr_err("sscanf failed: %d\n", ret);
2025 return -EFAULT;
2026 }
2027
2028 if (op == 'w') {
2029 pr_info("Write reg: 0x%04x with val: 0x%08x\n", reg, val);
2030 regmap_write(rv1106->regmap, reg, val);
2031 regcache_cache_only(rv1106->regmap, false);
2032 regcache_sync(rv1106->regmap);
2033 pr_info("Read back reg: 0x%04x with val: 0x%08x\n", reg, val);
2034 } else if (op == 'r') {
2035 regmap_read(rv1106->regmap, reg, &val);
2036 pr_info("Read reg: 0x%04x with val: 0x%08x\n", reg, val);
2037 } else {
2038 pr_err("This is an invalid operation: %c\n", op);
2039 }
2040
2041 return count;
2042 }
2043
rv1106_codec_debugfs_open(struct inode * inode,struct file * file)2044 static int rv1106_codec_debugfs_open(struct inode *inode, struct file *file)
2045 {
2046 return single_open(file,
2047 rv1106_codec_debugfs_reg_show, inode->i_private);
2048 }
2049
2050 static const struct file_operations rv1106_codec_reg_debugfs_fops = {
2051 .owner = THIS_MODULE,
2052 .open = rv1106_codec_debugfs_open,
2053 .read = seq_read,
2054 .write = rv1106_codec_debugfs_reg_operate,
2055 .llseek = seq_lseek,
2056 .release = single_release,
2057 };
2058 #endif /* CONFIG_DEBUG_FS */
2059
2060 static const struct of_device_id rv1106_codec_of_match[] = {
2061 { .compatible = "rockchip,rv1103-codec", .data = (void *)SOC_RV1103},
2062 { .compatible = "rockchip,rv1106-codec", .data = (void *)SOC_RV1106},
2063 {},
2064 };
2065 MODULE_DEVICE_TABLE(of, rv1106_codec_of_match);
2066
rv1106_platform_probe(struct platform_device * pdev)2067 static int rv1106_platform_probe(struct platform_device *pdev)
2068 {
2069 const struct of_device_id *of_id;
2070 struct device_node *np = pdev->dev.of_node;
2071 struct rv1106_codec_priv *rv1106;
2072 struct resource *res;
2073 void __iomem *base;
2074 int ret;
2075
2076 rv1106 = devm_kzalloc(&pdev->dev, sizeof(*rv1106), GFP_KERNEL);
2077 if (!rv1106)
2078 return -ENOMEM;
2079
2080 of_id = of_match_device(rv1106_codec_of_match, &pdev->dev);
2081 if (of_id)
2082 rv1106->soc_id = (enum soc_id_e)of_id->data;
2083 dev_info(&pdev->dev, "current soc_id: rv%x\n", rv1106->soc_id);
2084
2085 rv1106->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
2086 if (IS_ERR(rv1106->grf))
2087 return dev_err_probe(&pdev->dev, PTR_ERR(rv1106->grf),
2088 "Missing 'rockchip,grf' property\n");
2089
2090 rv1106->plat_dev = &pdev->dev;
2091 rv1106->reset = devm_reset_control_get(&pdev->dev, "acodec-reset");
2092 if (IS_ERR(rv1106->reset)) {
2093 ret = PTR_ERR(rv1106->reset);
2094 if (ret != -ENOENT)
2095 return ret;
2096
2097 dev_dbg(&pdev->dev, "No reset control found\n");
2098 rv1106->reset = NULL;
2099 }
2100
2101 rv1106->init_mic_gain = NOT_SPECIFIED;
2102 of_property_read_u32(np, "init-mic-gain", &rv1106->init_mic_gain);
2103
2104 rv1106->init_alc_gain = NOT_SPECIFIED;
2105 of_property_read_u32(np, "init-alc-gain", &rv1106->init_alc_gain);
2106
2107 rv1106->init_lineout_gain = NOT_SPECIFIED;
2108 of_property_read_u32(np, "init-lineout-gain", &rv1106->init_lineout_gain);
2109
2110 rv1106->pa_ctl_gpio = devm_gpiod_get_optional(&pdev->dev, "pa-ctl",
2111 GPIOD_OUT_LOW);
2112 if (IS_ERR(rv1106->pa_ctl_gpio))
2113 return dev_err_probe(&pdev->dev, PTR_ERR(rv1106->pa_ctl_gpio),
2114 "Unable to claim gpio pa-ctl\n");
2115
2116 if (rv1106->pa_ctl_gpio)
2117 of_property_read_u32(np, "pa-ctl-delay-ms",
2118 &rv1106->pa_ctl_delay_ms);
2119
2120 dev_info(&pdev->dev, "%s pa_ctl_gpio and pa_ctl_delay_ms: %d\n",
2121 rv1106->pa_ctl_gpio ? "Use" : "No use",
2122 rv1106->pa_ctl_delay_ms);
2123
2124 /* Close external PA during startup. */
2125 rv1106_codec_pa_ctrl(rv1106, false);
2126
2127 rv1106->pclk_acodec = devm_clk_get(&pdev->dev, "pclk_acodec");
2128 if (IS_ERR(rv1106->pclk_acodec))
2129 return dev_err_probe(&pdev->dev, PTR_ERR(rv1106->pclk_acodec),
2130 "Can't get acodec pclk_acodec\n");
2131
2132 rv1106->mclk_acodec = devm_clk_get(&pdev->dev, "mclk_acodec");
2133 if (IS_ERR(rv1106->mclk_acodec))
2134 return dev_err_probe(&pdev->dev, PTR_ERR(rv1106->mclk_acodec),
2135 "Can't get acodec mclk_acodec\n");
2136
2137 rv1106->mclk_cpu = devm_clk_get(&pdev->dev, "mclk_cpu");
2138 if (IS_ERR(rv1106->mclk_cpu))
2139 return dev_err_probe(&pdev->dev, PTR_ERR(rv1106->mclk_cpu),
2140 "Can't get acodec mclk_cpu\n");
2141
2142 ret = rv1106_codec_sysfs_init(pdev, rv1106);
2143 if (ret < 0)
2144 return dev_err_probe(&pdev->dev, ret, "Sysfs init failed\n");
2145
2146 #if defined(CONFIG_DEBUG_FS)
2147 rv1106->dbg_codec = debugfs_create_dir(CODEC_DRV_NAME, NULL);
2148 if (IS_ERR(rv1106->dbg_codec))
2149 dev_err(&pdev->dev,
2150 "Failed to create debugfs dir for rv1106!\n");
2151 else
2152 debugfs_create_file("reg", 0644, rv1106->dbg_codec,
2153 rv1106, &rv1106_codec_reg_debugfs_fops);
2154 #endif
2155
2156 ret = clk_prepare_enable(rv1106->pclk_acodec);
2157 if (ret < 0) {
2158 dev_err(&pdev->dev, "Failed to enable acodec pclk_acodec: %d\n", ret);
2159 goto failed_2;
2160 }
2161
2162 ret = clk_prepare_enable(rv1106->mclk_acodec);
2163 if (ret < 0) {
2164 dev_err(&pdev->dev, "Failed to enable acodec mclk_acodec: %d\n", ret);
2165 goto failed_1;
2166 }
2167
2168 /**
2169 * In PERICRU_PERICLKSEL_CON08, the mclk_acodec_t/rx_div are div 4
2170 * by default, we need to calibrate once, make the div is 1 and keep
2171 * the rate of mclk_acodec is the same with mclk_i2s.
2172 *
2173 * FIXME: need to handle div dynamically if the DSMAUDIO is enabled.
2174 */
2175 clk_set_rate(rv1106->mclk_acodec, clk_get_rate(rv1106->mclk_cpu));
2176
2177 rv1106_codec_check_micbias(rv1106, np);
2178
2179 ret = rv1106_codec_adc_i2s_route(rv1106);
2180 if (ret < 0) {
2181 dev_err(&pdev->dev, "Failed to route ADC to i2s: %d\n",
2182 ret);
2183 goto failed;
2184 }
2185
2186 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2187 base = devm_ioremap_resource(&pdev->dev, res);
2188 if (IS_ERR(base)) {
2189 ret = PTR_ERR(base);
2190 dev_err(&pdev->dev, "Failed to ioremap resource\n");
2191 goto failed;
2192 }
2193
2194 rv1106->regmap = devm_regmap_init_mmio(&pdev->dev, base,
2195 &rv1106_codec_regmap_config);
2196 if (IS_ERR(rv1106->regmap)) {
2197 ret = PTR_ERR(rv1106->regmap);
2198 dev_err(&pdev->dev, "Failed to regmap mmio\n");
2199 goto failed;
2200 }
2201
2202 platform_set_drvdata(pdev, rv1106);
2203 ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_dev_rv1106,
2204 rv1106_dai, ARRAY_SIZE(rv1106_dai));
2205 if (ret < 0) {
2206 dev_err(&pdev->dev, "Failed to register codec: %d\n", ret);
2207 goto failed;
2208 }
2209
2210 return ret;
2211
2212 failed:
2213 clk_disable_unprepare(rv1106->mclk_acodec);
2214 failed_1:
2215 clk_disable_unprepare(rv1106->pclk_acodec);
2216 failed_2:
2217 #if defined(CONFIG_DEBUG_FS)
2218 debugfs_remove_recursive(rv1106->dbg_codec);
2219 #endif
2220 rv1106_codec_sysfs_exit(rv1106);
2221
2222 return ret;
2223 }
2224
rv1106_platform_remove(struct platform_device * pdev)2225 static int rv1106_platform_remove(struct platform_device *pdev)
2226 {
2227 struct rv1106_codec_priv *rv1106 =
2228 (struct rv1106_codec_priv *)platform_get_drvdata(pdev);
2229
2230 clk_disable_unprepare(rv1106->mclk_acodec);
2231 clk_disable_unprepare(rv1106->pclk_acodec);
2232 #if defined(CONFIG_DEBUG_FS)
2233 debugfs_remove_recursive(rv1106->dbg_codec);
2234 #endif
2235 rv1106_codec_sysfs_exit(rv1106);
2236
2237 return 0;
2238 }
2239
2240 static struct platform_driver rv1106_codec_driver = {
2241 .driver = {
2242 .name = CODEC_DRV_NAME,
2243 .of_match_table = of_match_ptr(rv1106_codec_of_match),
2244 },
2245 .probe = rv1106_platform_probe,
2246 .remove = rv1106_platform_remove,
2247 };
2248 module_platform_driver(rv1106_codec_driver);
2249
2250 MODULE_DESCRIPTION("ASoC RV1106 Codec Driver");
2251 MODULE_AUTHOR("Jason Zhu <jason.zhu@rock-chips.com>");
2252 MODULE_LICENSE("GPL");
2253