1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Rockchip Audio Codec Digital Interface
4 *
5 * Copyright (C) 2020 Rockchip Electronics Co.,Ltd
6 *
7 */
8
9 #include <linux/module.h>
10 #include <linux/device.h>
11 #include <linux/delay.h>
12 #include <linux/of.h>
13 #include <linux/of_gpio.h>
14 #include <linux/of_platform.h>
15 #include <linux/clk.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/regmap.h>
20 #include <linux/reset.h>
21 #include <sound/pcm_params.h>
22 #include <sound/dmaengine_pcm.h>
23 #include <sound/tlv.h>
24 #include "rk_codec_digital.h"
25
26 #define RK3568_GRF_SOC_CON2 (0x0508)
27 #define RK3588_GRF_SOC_CON6 (0x0318)
28 #define RV1106_GRF_SOC_CON1 (0x0004)
29 #define RV1126_GRF_SOC_CON2 (0x0008)
30
31 struct rk_codec_digital_soc_data {
32 int (*init)(struct device *dev);
33 void (*deinit)(struct device *dev);
34 };
35
36 struct rk_codec_digital_priv {
37 struct regmap *grf;
38 struct regmap *regmap;
39 struct clk *clk_adc;
40 struct clk *clk_dac;
41 struct clk *clk_i2c;
42 struct clk *pclk;
43 bool pwmout;
44 bool sync;
45 unsigned int pa_ctl_delay_ms;
46 struct gpio_desc *pa_ctl;
47 struct reset_control *rc;
48 const struct rk_codec_digital_soc_data *data;
49 };
50
51 /* ADC digital gain */
52 static const DECLARE_TLV_DB_SCALE(adc_tlv, -95625, 375, 0);
53 /* PGA gain */
54 static const DECLARE_TLV_DB_SCALE(pga_tlv, -18, 3, 0);
55 /* DAC digital gain */
56 static const DECLARE_TLV_DB_SCALE(dac_tlv, -95625, 375, 0);
57
58 /* ADC Cutoff Freq for High Pass Filter */
59 static const char * const adc_hpf_cutoff_text[] = {
60 "3.79Hz", "60Hz", "243Hz", "493Hz",
61 };
62
63 static SOC_ENUM_SINGLE_DECL(adc_hpf_cutoff_enum, ADCHPFCF, 0,
64 adc_hpf_cutoff_text);
65
66 /* DAC Cutoff for High Pass Filter */
67 static const char * const dac_hpf_cutoff_text[] = {
68 "80Hz", "100Hz", "120Hz", "140Hz",
69 };
70
71 static SOC_ENUM_SINGLE_DECL(dac_hpf_cutoff_enum, DACHPF, 4,
72 dac_hpf_cutoff_text);
73
74 static const char * const pa_ctl[] = {"Off", "On"};
75
76 static const struct soc_enum pa_enum =
77 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(pa_ctl), pa_ctl);
78
rk_codec_digital_adc_vol_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)79 static int rk_codec_digital_adc_vol_get(struct snd_kcontrol *kcontrol,
80 struct snd_ctl_elem_value *ucontrol)
81 {
82 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
83 struct soc_mixer_control *mc =
84 (struct soc_mixer_control *)kcontrol->private_value;
85 unsigned int val = snd_soc_component_read(component, mc->reg);
86 unsigned int sign = snd_soc_component_read(component, ADCVOGP);
87 unsigned int mask = (1 << fls(mc->max)) - 1;
88 unsigned int shift = mc->shift;
89 int mid = mc->max / 2;
90 int uv;
91
92 switch (mc->reg) {
93 case ADCVOLL0:
94 sign &= ACDCDIG_ADCVOGP_VOLGPL0_MASK;
95 break;
96 case ADCVOLL1:
97 sign &= ACDCDIG_ADCVOGP_VOLGPL1_MASK;
98 break;
99 case ADCVOLR0:
100 sign &= ACDCDIG_ADCVOGP_VOLGPR0_MASK;
101 break;
102 default:
103 return -EINVAL;
104 }
105
106 uv = (val >> shift) & mask;
107 if (sign)
108 uv = mid + uv;
109 else
110 uv = mid - uv;
111
112 ucontrol->value.integer.value[0] = uv;
113
114 return 0;
115 }
116
rk_codec_digital_adc_vol_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)117 static int rk_codec_digital_adc_vol_put(struct snd_kcontrol *kcontrol,
118 struct snd_ctl_elem_value *ucontrol)
119 {
120 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
121 struct soc_mixer_control *mc =
122 (struct soc_mixer_control *)kcontrol->private_value;
123 unsigned int reg = mc->reg;
124 unsigned int shift = mc->shift;
125 unsigned int mask = (1 << fls(mc->max)) - 1;
126 unsigned int val, val_mask, sign, sign_mask;
127 int uv = ucontrol->value.integer.value[0];
128 int min = mc->min;
129 int mid = mc->max / 2;
130 bool pos = (uv > mid);
131
132 switch (mc->reg) {
133 case ADCVOLL0:
134 sign_mask = ACDCDIG_ADCVOGP_VOLGPL0_MASK;
135 sign = pos ? ACDCDIG_ADCVOGP_VOLGPL0_POS : ACDCDIG_ADCVOGP_VOLGPL0_NEG;
136 break;
137 case ADCVOLL1:
138 sign_mask = ACDCDIG_ADCVOGP_VOLGPL1_MASK;
139 sign = pos ? ACDCDIG_ADCVOGP_VOLGPL1_POS : ACDCDIG_ADCVOGP_VOLGPL1_NEG;
140 break;
141 case ADCVOLR0:
142 sign_mask = ACDCDIG_ADCVOGP_VOLGPR0_MASK;
143 sign = pos ? ACDCDIG_ADCVOGP_VOLGPR0_POS : ACDCDIG_ADCVOGP_VOLGPR0_NEG;
144 break;
145 default:
146 return -EINVAL;
147 }
148
149 uv = pos ? (uv - mid) : (mid - uv);
150
151 val = ((uv + min) & mask);
152 val_mask = mask << shift;
153 val = val << shift;
154
155 snd_soc_component_update_bits(component, reg, val_mask, val);
156 snd_soc_component_update_bits(component, ADCVOGP, sign_mask, sign);
157
158 return 0;
159 }
160
rk_codec_digital_dac_vol_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)161 static int rk_codec_digital_dac_vol_get(struct snd_kcontrol *kcontrol,
162 struct snd_ctl_elem_value *ucontrol)
163 {
164 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
165 struct soc_mixer_control *mc =
166 (struct soc_mixer_control *)kcontrol->private_value;
167 unsigned int val = snd_soc_component_read(component, mc->reg);
168 unsigned int sign = snd_soc_component_read(component, DACVOGP);
169 unsigned int mask = (1 << fls(mc->max)) - 1;
170 unsigned int shift = mc->shift;
171 int mid = mc->max / 2;
172 int uv;
173
174 uv = (val >> shift) & mask;
175 if (sign)
176 uv = mid + uv;
177 else
178 uv = mid - uv;
179
180 ucontrol->value.integer.value[0] = uv;
181 ucontrol->value.integer.value[1] = uv;
182
183 return 0;
184 }
185
rk_codec_digital_dac_vol_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)186 static int rk_codec_digital_dac_vol_put(struct snd_kcontrol *kcontrol,
187 struct snd_ctl_elem_value *ucontrol)
188 {
189 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
190 struct soc_mixer_control *mc =
191 (struct soc_mixer_control *)kcontrol->private_value;
192 unsigned int reg = mc->reg;
193 unsigned int rreg = mc->rreg;
194 unsigned int shift = mc->shift;
195 unsigned int mask = (1 << fls(mc->max)) - 1;
196 unsigned int val, val_mask, sign;
197 int uv = ucontrol->value.integer.value[0];
198 int min = mc->min;
199 int mid = mc->max / 2;
200
201 if (uv > mid) {
202 sign = ACDCDIG_DACVOGP_VOLGPL0_POS | ACDCDIG_DACVOGP_VOLGPR0_POS;
203 uv = uv - mid;
204 } else {
205 sign = ACDCDIG_DACVOGP_VOLGPL0_NEG | ACDCDIG_DACVOGP_VOLGPR0_NEG;
206 uv = mid - uv;
207 }
208
209 val = ((uv + min) & mask);
210 val_mask = mask << shift;
211 val = val << shift;
212
213 snd_soc_component_update_bits(component, reg, val_mask, val);
214 snd_soc_component_update_bits(component, rreg, val_mask, val);
215 snd_soc_component_write(component, DACVOGP, sign);
216
217 return 0;
218 }
219
rk_codec_digital_dac_pa_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)220 static int rk_codec_digital_dac_pa_get(struct snd_kcontrol *kcontrol,
221 struct snd_ctl_elem_value *ucontrol)
222 {
223 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
224 struct rk_codec_digital_priv *rcd = snd_soc_component_get_drvdata(component);
225
226 if (!rcd->pa_ctl)
227 return -EINVAL;
228
229 ucontrol->value.enumerated.item[0] = gpiod_get_value(rcd->pa_ctl);
230
231 return 0;
232 }
233
rk_codec_digital_dac_pa_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)234 static int rk_codec_digital_dac_pa_put(struct snd_kcontrol *kcontrol,
235 struct snd_ctl_elem_value *ucontrol)
236 {
237 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
238 struct rk_codec_digital_priv *rcd = snd_soc_component_get_drvdata(component);
239
240 if (!rcd->pa_ctl)
241 return -EINVAL;
242
243 gpiod_set_value(rcd->pa_ctl, ucontrol->value.enumerated.item[0]);
244
245 return 0;
246 }
247
248 static const struct snd_kcontrol_new rk_codec_digital_snd_controls[] = {
249 SOC_SINGLE_EXT_TLV("ADCL0 Digital Volume",
250 ADCVOLL0, 0, 0X1fe, 0,
251 rk_codec_digital_adc_vol_get,
252 rk_codec_digital_adc_vol_put,
253 adc_tlv),
254 SOC_SINGLE_EXT_TLV("ADCL1 Digital Volume",
255 ADCVOLL1, 0, 0x1fe, 0,
256 rk_codec_digital_adc_vol_get,
257 rk_codec_digital_adc_vol_put,
258 adc_tlv),
259 SOC_SINGLE_EXT_TLV("ADCR0 Digital Volume",
260 ADCVOLR0, 0, 0x1fe, 0,
261 rk_codec_digital_adc_vol_get,
262 rk_codec_digital_adc_vol_put,
263 adc_tlv),
264
265 SOC_SINGLE_TLV("ADCL0 PGA Gain",
266 ADCPGL0, 0, 0Xf, 0, pga_tlv),
267 SOC_SINGLE_TLV("ADCL1 PGA Gain",
268 ADCPGL1, 0, 0xf, 0, pga_tlv),
269 SOC_SINGLE_TLV("ADCR0 PGA Gain",
270 ADCPGR0, 0, 0xf, 0, pga_tlv),
271
272 SOC_DOUBLE_R_EXT_TLV("DAC Digital Volume",
273 DACVOLL0, DACVOLR0, 0, 0x1fe, 0,
274 rk_codec_digital_dac_vol_get,
275 rk_codec_digital_dac_vol_put,
276 dac_tlv),
277
278 SOC_ENUM("ADC HPF Cutoff", adc_hpf_cutoff_enum),
279 SOC_SINGLE("ADC L0 HPF Switch", ADCHPFEN, 0, 1, 0),
280 SOC_SINGLE("ADC R0 HPF Switch", ADCHPFEN, 1, 1, 0),
281 SOC_SINGLE("ADC L1 HPF Switch", ADCHPFEN, 2, 1, 0),
282
283 SOC_ENUM("DAC HPF Cutoff", dac_hpf_cutoff_enum),
284 SOC_SINGLE("DAC HPF Switch", DACHPF, 0, 1, 0),
285 SOC_ENUM_EXT("Power Amplifier", pa_enum,
286 rk_codec_digital_dac_pa_get,
287 rk_codec_digital_dac_pa_put),
288 };
289
rk_codec_digital_reset(struct rk_codec_digital_priv * rcd)290 static void rk_codec_digital_reset(struct rk_codec_digital_priv *rcd)
291 {
292 if (IS_ERR(rcd->rc))
293 return;
294
295 reset_control_assert(rcd->rc);
296 udelay(1);
297 reset_control_deassert(rcd->rc);
298 }
299
300 /*
301 * ACDC_CLK D2A_CLK D2A_SYNC Sample rates supported
302 * 49.152MHz 49.152MHz 6.144MHz 12/24/48/96/192kHz
303 * 45.154MHz 45.154MHz 5.644MHz 11.025/22.05/44.1/88.2/176.4kHz
304 * 32.768MHz 32.768MHz 4.096MHz 8/16/32/64/128kHz
305 *
306 */
rk_codec_digital_get_clk(unsigned int samplerate,unsigned int * mclk,unsigned int * sclk)307 static void rk_codec_digital_get_clk(unsigned int samplerate,
308 unsigned int *mclk,
309 unsigned int *sclk)
310 {
311 switch (samplerate) {
312 case 12000:
313 case 24000:
314 case 48000:
315 case 96000:
316 case 192000:
317 *mclk = 49152000;
318 *sclk = 6144000;
319 break;
320 case 11025:
321 case 22050:
322 case 44100:
323 case 88200:
324 case 176400:
325 *mclk = 45158400;
326 *sclk = 5644800;
327 break;
328 case 8000:
329 case 16000:
330 case 32000:
331 case 64000:
332 case 128000:
333 *mclk = 32768000;
334 *sclk = 4096000;
335 break;
336 default:
337 *mclk = 0;
338 *sclk = 0;
339 break;
340 }
341 }
342
rk_codec_digital_enable_clk_adc(struct rk_codec_digital_priv * rcd)343 static void rk_codec_digital_enable_clk_adc(struct rk_codec_digital_priv *rcd)
344 {
345 regmap_update_bits(rcd->regmap, ADCCLKCTRL,
346 ACDCDIG_ADCCLKCTRL_CIC_DS_RATIO_MASK |
347 ACDCDIG_ADCCLKCTRL_ADC_CKE_MASK |
348 ACDCDIG_ADCCLKCTRL_I2STX_CKE_MASK |
349 ACDCDIG_ADCCLKCTRL_CKE_BCLKTX_MASK |
350 ACDCDIG_ADCCLKCTRL_FILTER_GATE_EN_MASK |
351 ACDCDIG_ADCCLKCTRL_ADC_SYNC_ENA_MASK,
352 ACDCDIG_ADCCLKCTRL_CIC_DS_RATIO_16 |
353 ACDCDIG_ADCCLKCTRL_ADC_CKE_EN |
354 ACDCDIG_ADCCLKCTRL_I2STX_CKE_EN |
355 ACDCDIG_ADCCLKCTRL_CKE_BCLKTX_EN |
356 ACDCDIG_ADCCLKCTRL_FILTER_GATE_EN |
357 ACDCDIG_ADCCLKCTRL_ADC_SYNC_ENA_EN);
358 }
359
rk_codec_digital_enable_clk_dac(struct rk_codec_digital_priv * rcd)360 static void rk_codec_digital_enable_clk_dac(struct rk_codec_digital_priv *rcd)
361 {
362 regmap_update_bits(rcd->regmap, DACCLKCTRL,
363 ACDCDIG_DACCLKCTRL_DAC_CKE_MASK |
364 ACDCDIG_DACCLKCTRL_I2SRX_CKE_MASK |
365 ACDCDIG_DACCLKCTRL_CKE_BCLKRX_MASK |
366 ACDCDIG_DACCLKCTRL_DAC_SYNC_ENA_MASK |
367 ACDCDIG_DACCLKCTRL_DAC_MODE_ATTENU_MASK,
368 ACDCDIG_DACCLKCTRL_DAC_CKE_EN |
369 ACDCDIG_DACCLKCTRL_I2SRX_CKE_EN |
370 ACDCDIG_DACCLKCTRL_CKE_BCLKRX_EN |
371 ACDCDIG_DACCLKCTRL_DAC_SYNC_ENA_EN |
372 ACDCDIG_DACCLKCTRL_DAC_MODE_ATTENU_EN);
373 }
374
rk_codec_digital_set_clk_sync(struct rk_codec_digital_priv * rcd,unsigned int mclk,unsigned int sclk,unsigned int bclk)375 static int rk_codec_digital_set_clk_sync(struct rk_codec_digital_priv *rcd,
376 unsigned int mclk,
377 unsigned int sclk,
378 unsigned int bclk)
379 {
380 unsigned int div_sync, div_bclk;
381
382 div_bclk = DIV_ROUND_CLOSEST(mclk, bclk);
383 div_sync = DIV_ROUND_CLOSEST(mclk, sclk);
384
385 clk_set_rate(rcd->clk_adc, mclk);
386 clk_set_rate(rcd->clk_dac, mclk);
387
388 /* select clock sync is from ADC. */
389 regmap_update_bits(rcd->regmap, SYSCTRL0,
390 ACDCDIG_SYSCTRL0_SYNC_MODE_MASK |
391 ACDCDIG_SYSCTRL0_CLK_COM_SEL_MASK,
392 ACDCDIG_SYSCTRL0_SYNC_MODE_SYNC |
393 ACDCDIG_SYSCTRL0_CLK_COM_SEL_ADC);
394
395 regmap_update_bits(rcd->regmap, ADCINT_DIV,
396 ACDCDIG_ADCINT_DIV_INT_DIV_CON_MASK,
397 ACDCDIG_ADCINT_DIV_INT_DIV_CON(div_sync));
398 regmap_update_bits(rcd->regmap, DACINT_DIV,
399 ACDCDIG_DACINT_DIV_INT_DIV_CON_MASK,
400 ACDCDIG_DACINT_DIV_INT_DIV_CON(div_sync));
401
402 rk_codec_digital_enable_clk_adc(rcd);
403 rk_codec_digital_enable_clk_dac(rcd);
404
405 regmap_update_bits(rcd->regmap, DACSCLKRXINT_DIV,
406 ACDCDIG_DACSCLKRXINT_DIV_SCKRXDIV_MASK,
407 ACDCDIG_DACSCLKRXINT_DIV_SCKRXDIV(div_bclk));
408 regmap_update_bits(rcd->regmap, I2S_CKR0,
409 ACDCDIG_I2S_CKR0_RSD_MASK,
410 ACDCDIG_I2S_CKR0_RSD_64);
411 regmap_update_bits(rcd->regmap, ADCSCLKTXINT_DIV,
412 ACDCDIG_ADCSCLKTXINT_DIV_SCKTXDIV_MASK,
413 ACDCDIG_ADCSCLKTXINT_DIV_SCKTXDIV(div_bclk));
414 regmap_update_bits(rcd->regmap, I2S_CKR0,
415 ACDCDIG_I2S_CKR0_TSD_MASK,
416 ACDCDIG_I2S_CKR0_TSD_64);
417
418 return 0;
419 }
420
rk_codec_digital_set_clk(struct rk_codec_digital_priv * rcd,struct snd_pcm_substream * substream,unsigned int samplerate)421 static int rk_codec_digital_set_clk(struct rk_codec_digital_priv *rcd,
422 struct snd_pcm_substream *substream,
423 unsigned int samplerate)
424 {
425 unsigned int mclk, sclk, bclk;
426 unsigned int div_sync, div_bclk;
427
428 rk_codec_digital_get_clk(samplerate, &mclk, &sclk);
429 if (!mclk || !sclk)
430 return -EINVAL;
431
432 bclk = 64 * samplerate;
433 div_bclk = DIV_ROUND_CLOSEST(mclk, bclk);
434 div_sync = DIV_ROUND_CLOSEST(mclk, sclk);
435
436 if (rcd->sync)
437 return rk_codec_digital_set_clk_sync(rcd, mclk, sclk, bclk);
438
439 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
440 clk_set_rate(rcd->clk_dac, mclk);
441
442 regmap_update_bits(rcd->regmap, DACINT_DIV,
443 ACDCDIG_DACINT_DIV_INT_DIV_CON_MASK,
444 ACDCDIG_DACINT_DIV_INT_DIV_CON(div_sync));
445
446 rk_codec_digital_enable_clk_dac(rcd);
447
448 regmap_update_bits(rcd->regmap, DACSCLKRXINT_DIV,
449 ACDCDIG_DACSCLKRXINT_DIV_SCKRXDIV_MASK,
450 ACDCDIG_DACSCLKRXINT_DIV_SCKRXDIV(div_bclk));
451 regmap_update_bits(rcd->regmap, I2S_CKR0,
452 ACDCDIG_I2S_CKR0_RSD_MASK,
453 ACDCDIG_I2S_CKR0_RSD_64);
454 } else {
455 clk_set_rate(rcd->clk_adc, mclk);
456
457 regmap_update_bits(rcd->regmap, ADCINT_DIV,
458 ACDCDIG_ADCINT_DIV_INT_DIV_CON_MASK,
459 ACDCDIG_ADCINT_DIV_INT_DIV_CON(div_sync));
460
461 rk_codec_digital_enable_clk_adc(rcd);
462 regmap_update_bits(rcd->regmap, ADCSCLKTXINT_DIV,
463 ACDCDIG_ADCSCLKTXINT_DIV_SCKTXDIV_MASK,
464 ACDCDIG_ADCSCLKTXINT_DIV_SCKTXDIV(div_bclk));
465 regmap_update_bits(rcd->regmap, I2S_CKR0,
466 ACDCDIG_I2S_CKR0_TSD_MASK,
467 ACDCDIG_I2S_CKR0_TSD_64);
468 }
469
470 return 0;
471 }
472
rk_codec_digital_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)473 static int rk_codec_digital_set_dai_fmt(struct snd_soc_dai *dai,
474 unsigned int fmt)
475 {
476 struct rk_codec_digital_priv *rcd =
477 snd_soc_component_get_drvdata(dai->component);
478 unsigned int mask = 0, val = 0;
479
480 /* master mode only */
481 regmap_update_bits(rcd->regmap, I2S_CKR1,
482 ACDCDIG_I2S_CKR1_MSS_MASK,
483 ACDCDIG_I2S_CKR1_MSS_MASTER);
484
485 mask = ACDCDIG_I2S_CKR1_CKP_MASK |
486 ACDCDIG_I2S_CKR1_RLP_MASK |
487 ACDCDIG_I2S_CKR1_TLP_MASK;
488
489 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
490 case SND_SOC_DAIFMT_NB_NF:
491 val = ACDCDIG_I2S_CKR1_CKP_NORMAL |
492 ACDCDIG_I2S_CKR1_RLP_NORMAL |
493 ACDCDIG_I2S_CKR1_TLP_NORMAL;
494 break;
495 case SND_SOC_DAIFMT_IB_IF:
496 val = ACDCDIG_I2S_CKR1_CKP_INVERTED |
497 ACDCDIG_I2S_CKR1_RLP_INVERTED |
498 ACDCDIG_I2S_CKR1_TLP_INVERTED;
499 break;
500 case SND_SOC_DAIFMT_IB_NF:
501 val = ACDCDIG_I2S_CKR1_CKP_INVERTED |
502 ACDCDIG_I2S_CKR1_RLP_NORMAL |
503 ACDCDIG_I2S_CKR1_TLP_NORMAL;
504 break;
505 case SND_SOC_DAIFMT_NB_IF:
506 val = ACDCDIG_I2S_CKR1_CKP_NORMAL |
507 ACDCDIG_I2S_CKR1_RLP_INVERTED |
508 ACDCDIG_I2S_CKR1_TLP_INVERTED;
509 break;
510 default:
511 return -EINVAL;
512 }
513
514 regmap_update_bits(rcd->regmap, I2S_CKR1, mask, val);
515
516 return 0;
517 }
518
rk_codec_digital_enable_sync(struct rk_codec_digital_priv * rcd)519 static int rk_codec_digital_enable_sync(struct rk_codec_digital_priv *rcd)
520 {
521 regmap_update_bits(rcd->regmap, I2S_XFER,
522 ACDCDIG_I2S_XFER_RXS_MASK |
523 ACDCDIG_I2S_XFER_TXS_MASK,
524 ACDCDIG_I2S_XFER_RXS_START |
525 ACDCDIG_I2S_XFER_TXS_START);
526
527 regmap_update_bits(rcd->regmap, SYSCTRL0,
528 ACDCDIG_SYSCTRL0_GLB_CKE_MASK,
529 ACDCDIG_SYSCTRL0_GLB_CKE_EN);
530
531 regmap_update_bits(rcd->regmap, ADCDIGEN,
532 ACDCDIG_ADCDIGEN_ADC_GLBEN_MASK |
533 ACDCDIG_ADCDIGEN_ADCEN_L2_MASK |
534 ACDCDIG_ADCDIGEN_ADCEN_L0R1_MASK,
535 ACDCDIG_ADCDIGEN_ADC_GLBEN_EN |
536 ACDCDIG_ADCDIGEN_ADCEN_L2_EN |
537 ACDCDIG_ADCDIGEN_ADCEN_L0R1_EN);
538
539 regmap_update_bits(rcd->regmap, DACDIGEN,
540 ACDCDIG_DACDIGEN_DAC_GLBEN_MASK |
541 ACDCDIG_DACDIGEN_DACEN_L0R1_MASK,
542 ACDCDIG_DACDIGEN_DAC_GLBEN_EN |
543 ACDCDIG_DACDIGEN_DACEN_L0R1_EN);
544
545 return 0;
546 }
547
rk_codec_digital_disable_sync(struct rk_codec_digital_priv * rcd)548 static int rk_codec_digital_disable_sync(struct rk_codec_digital_priv *rcd)
549 {
550 regmap_update_bits(rcd->regmap, I2S_XFER,
551 ACDCDIG_I2S_XFER_RXS_MASK |
552 ACDCDIG_I2S_XFER_TXS_MASK,
553 ACDCDIG_I2S_XFER_RXS_STOP |
554 ACDCDIG_I2S_XFER_TXS_STOP);
555
556 regmap_update_bits(rcd->regmap, I2S_CLR,
557 ACDCDIG_I2S_CLR_RXC_MASK |
558 ACDCDIG_I2S_CLR_TXC_MASK,
559 ACDCDIG_I2S_CLR_RXC_CLR |
560 ACDCDIG_I2S_CLR_TXC_CLR);
561
562 regmap_update_bits(rcd->regmap, SYSCTRL0,
563 ACDCDIG_SYSCTRL0_GLB_CKE_MASK,
564 ACDCDIG_SYSCTRL0_GLB_CKE_DIS);
565
566 regmap_update_bits(rcd->regmap, ADCDIGEN,
567 ACDCDIG_ADCDIGEN_ADC_GLBEN_MASK |
568 ACDCDIG_ADCDIGEN_ADCEN_L2_MASK |
569 ACDCDIG_ADCDIGEN_ADCEN_L0R1_MASK,
570 ACDCDIG_ADCDIGEN_ADC_GLBEN_DIS |
571 ACDCDIG_ADCDIGEN_ADCEN_L2_DIS |
572 ACDCDIG_ADCDIGEN_ADCEN_L0R1_DIS);
573
574 regmap_update_bits(rcd->regmap, DACDIGEN,
575 ACDCDIG_DACDIGEN_DAC_GLBEN_MASK |
576 ACDCDIG_DACDIGEN_DACEN_L0R1_MASK,
577 ACDCDIG_DACDIGEN_DAC_GLBEN_DIS |
578 ACDCDIG_DACDIGEN_DACEN_L0R1_DIS);
579
580 return 0;
581 }
582
rk_codec_digital_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)583 static int rk_codec_digital_hw_params(struct snd_pcm_substream *substream,
584 struct snd_pcm_hw_params *params,
585 struct snd_soc_dai *dai)
586 {
587 struct rk_codec_digital_priv *rcd =
588 snd_soc_component_get_drvdata(dai->component);
589 unsigned int srt = 0, val = 0;
590
591 rk_codec_digital_set_clk(rcd, substream, params_rate(params));
592
593 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
594 switch (params_rate(params)) {
595 case 8000:
596 case 11025:
597 case 12000:
598 srt = 0;
599 break;
600 case 16000:
601 case 22050:
602 case 24000:
603 srt = 1;
604 break;
605 case 32000:
606 case 44100:
607 case 48000:
608 srt = 2;
609 break;
610 case 64000:
611 case 88200:
612 case 96000:
613 srt = 3;
614 break;
615 case 128000:
616 case 176400:
617 case 192000:
618 srt = 4;
619 break;
620 default:
621 return -EINVAL;
622 }
623
624 regmap_update_bits(rcd->regmap, DACCFG1,
625 ACDCDIG_DACCFG1_DACSRT_MASK,
626 ACDCDIG_DACCFG1_DACSRT(srt));
627
628 switch (params_format(params)) {
629 case SNDRV_PCM_FORMAT_S16_LE:
630 val = 16;
631 break;
632 case SNDRV_PCM_FORMAT_S24_LE:
633 case SNDRV_PCM_FORMAT_S32_LE:
634 val = 24;
635 break;
636 default:
637 return -EINVAL;
638 }
639
640 regmap_update_bits(rcd->regmap, I2S_RXCR0,
641 ACDCDIG_I2S_RXCR0_VDW_MASK,
642 ACDCDIG_I2S_RXCR0_VDW(val));
643 if (rcd->pwmout)
644 regmap_update_bits(rcd->regmap, DACPWM_CTRL,
645 ACDCDIG_DACPWM_CTRL_PWM_MODE_CKE_MASK |
646 ACDCDIG_DACPWM_CTRL_PWM_EN_MASK,
647 ACDCDIG_DACPWM_CTRL_PWM_MODE_CKE_EN |
648 ACDCDIG_DACPWM_CTRL_PWM_EN);
649 } else {
650 switch (params_rate(params)) {
651 case 8000:
652 case 11025:
653 case 12000:
654 srt = 0;
655 break;
656 case 16000:
657 case 22050:
658 case 24000:
659 srt = 1;
660 break;
661 case 32000:
662 srt = 2;
663 break;
664 case 44100:
665 case 48000:
666 srt = 3;
667 break;
668 case 64000:
669 case 88200:
670 case 96000:
671 srt = 4;
672 break;
673 case 128000:
674 case 176400:
675 case 192000:
676 srt = 5;
677 break;
678 default:
679 return -EINVAL;
680 }
681
682 regmap_update_bits(rcd->regmap, ADCCFG1,
683 ACDCDIG_ADCCFG1_ADCSRT_MASK,
684 ACDCDIG_ADCCFG1_ADCSRT(srt));
685
686 switch (params_format(params)) {
687 case SNDRV_PCM_FORMAT_S16_LE:
688 val = 16;
689 break;
690 case SNDRV_PCM_FORMAT_S24_LE:
691 case SNDRV_PCM_FORMAT_S32_LE:
692 val = 24;
693 break;
694 default:
695 return -EINVAL;
696 }
697
698 regmap_update_bits(rcd->regmap, I2S_TXCR0,
699 ACDCDIG_I2S_TXCR0_VDW_MASK,
700 ACDCDIG_I2S_TXCR0_VDW(val));
701
702 switch (params_channels(params)) {
703 case 4:
704 val = ACDCDIG_I2S_TXCR1_TCSR_4CH;
705 break;
706 case 2:
707 val = ACDCDIG_I2S_TXCR1_TCSR_2CH;
708 break;
709 default:
710 return -EINVAL;
711 }
712
713 regmap_update_bits(rcd->regmap, I2S_TXCR1,
714 ACDCDIG_I2S_TXCR1_TCSR_MASK, val);
715 }
716
717 if (rcd->sync)
718 return rk_codec_digital_enable_sync(rcd);
719
720 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
721 regmap_update_bits(rcd->regmap, I2S_XFER,
722 ACDCDIG_I2S_XFER_RXS_MASK,
723 ACDCDIG_I2S_XFER_RXS_START);
724 regmap_update_bits(rcd->regmap, DACDIGEN,
725 ACDCDIG_DACDIGEN_DAC_GLBEN_MASK |
726 ACDCDIG_DACDIGEN_DACEN_L0R1_MASK,
727 ACDCDIG_DACDIGEN_DAC_GLBEN_EN |
728 ACDCDIG_DACDIGEN_DACEN_L0R1_EN);
729 } else {
730 regmap_update_bits(rcd->regmap, I2S_XFER,
731 ACDCDIG_I2S_XFER_TXS_MASK,
732 ACDCDIG_I2S_XFER_TXS_START);
733 regmap_update_bits(rcd->regmap, ADCDIGEN,
734 ACDCDIG_ADCDIGEN_ADC_GLBEN_MASK |
735 ACDCDIG_ADCDIGEN_ADCEN_L2_MASK |
736 ACDCDIG_ADCDIGEN_ADCEN_L0R1_MASK,
737 ACDCDIG_ADCDIGEN_ADC_GLBEN_EN |
738 ACDCDIG_ADCDIGEN_ADCEN_L2_EN |
739 ACDCDIG_ADCDIGEN_ADCEN_L0R1_EN);
740 }
741
742 return 0;
743 }
744
rk_codec_digital_pcm_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)745 static int rk_codec_digital_pcm_startup(struct snd_pcm_substream *substream,
746 struct snd_soc_dai *dai)
747 {
748 struct rk_codec_digital_priv *rcd =
749 snd_soc_component_get_drvdata(dai->component);
750
751 if (rcd->pa_ctl) {
752 gpiod_set_value_cansleep(rcd->pa_ctl, 1);
753 if (rcd->pa_ctl_delay_ms)
754 msleep(rcd->pa_ctl_delay_ms);
755 }
756
757 return 0;
758 }
759
rk_codec_digital_pcm_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)760 static void rk_codec_digital_pcm_shutdown(struct snd_pcm_substream *substream,
761 struct snd_soc_dai *dai)
762 {
763 struct rk_codec_digital_priv *rcd =
764 snd_soc_component_get_drvdata(dai->component);
765
766 if (rcd->pa_ctl)
767 gpiod_set_value_cansleep(rcd->pa_ctl, 0);
768
769 if (rcd->sync) {
770 if (!snd_soc_component_active(dai->component)) {
771 rk_codec_digital_disable_sync(rcd);
772 rk_codec_digital_reset(rcd);
773 }
774
775 return;
776 }
777
778 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
779 if (rcd->pwmout)
780 regmap_update_bits(rcd->regmap, DACPWM_CTRL,
781 ACDCDIG_DACPWM_CTRL_PWM_MODE_CKE_MASK |
782 ACDCDIG_DACPWM_CTRL_PWM_EN_MASK,
783 ACDCDIG_DACPWM_CTRL_PWM_MODE_CKE_DIS |
784 ACDCDIG_DACPWM_CTRL_PWM_DIS);
785 regmap_update_bits(rcd->regmap, I2S_XFER,
786 ACDCDIG_I2S_XFER_RXS_MASK,
787 ACDCDIG_I2S_XFER_RXS_STOP);
788 regmap_update_bits(rcd->regmap, I2S_CLR,
789 ACDCDIG_I2S_CLR_RXC_MASK,
790 ACDCDIG_I2S_CLR_RXC_CLR);
791 regmap_update_bits(rcd->regmap, DACDIGEN,
792 ACDCDIG_DACDIGEN_DAC_GLBEN_MASK |
793 ACDCDIG_DACDIGEN_DACEN_L0R1_MASK,
794 ACDCDIG_DACDIGEN_DAC_GLBEN_DIS |
795 ACDCDIG_DACDIGEN_DACEN_L0R1_DIS);
796 } else {
797 regmap_update_bits(rcd->regmap, I2S_XFER,
798 ACDCDIG_I2S_XFER_TXS_MASK,
799 ACDCDIG_I2S_XFER_TXS_STOP);
800 regmap_update_bits(rcd->regmap, I2S_CLR,
801 ACDCDIG_I2S_CLR_TXC_MASK,
802 ACDCDIG_I2S_CLR_TXC_CLR);
803
804 regmap_update_bits(rcd->regmap, ADCDIGEN,
805 ACDCDIG_ADCDIGEN_ADC_GLBEN_MASK |
806 ACDCDIG_ADCDIGEN_ADCEN_L2_MASK |
807 ACDCDIG_ADCDIGEN_ADCEN_L0R1_MASK,
808 ACDCDIG_ADCDIGEN_ADC_GLBEN_DIS |
809 ACDCDIG_ADCDIGEN_ADCEN_L2_DIS |
810 ACDCDIG_ADCDIGEN_ADCEN_L0R1_DIS);
811 }
812 }
813
814 static const struct snd_soc_dai_ops rcd_dai_ops = {
815 .hw_params = rk_codec_digital_hw_params,
816 .set_fmt = rk_codec_digital_set_dai_fmt,
817 .startup = rk_codec_digital_pcm_startup,
818 .shutdown = rk_codec_digital_pcm_shutdown,
819 };
820
821 static struct snd_soc_dai_driver rcd_dai[] = {
822 {
823 .name = "rk_codec_digital",
824 .id = 0,
825 .playback = {
826 .stream_name = "Playback",
827 .channels_min = 2,
828 .channels_max = 2,
829 .rates = SNDRV_PCM_RATE_8000_192000,
830 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
831 SNDRV_PCM_FMTBIT_S24_LE |
832 SNDRV_PCM_FMTBIT_S32_LE),
833 },
834 .capture = {
835 .stream_name = "Capture",
836 .channels_min = 2,
837 .channels_max = 4,
838 .rates = SNDRV_PCM_RATE_8000_192000,
839 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
840 SNDRV_PCM_FMTBIT_S24_LE |
841 SNDRV_PCM_FMTBIT_S32_LE),
842 },
843 .ops = &rcd_dai_ops,
844 },
845 };
846
847 static const struct snd_soc_component_driver soc_codec_dev_rcd = {
848 .controls = rk_codec_digital_snd_controls,
849 .num_controls = ARRAY_SIZE(rk_codec_digital_snd_controls),
850 };
851
852 static const struct regmap_config rcd_regmap_config = {
853 .reg_bits = 32,
854 .reg_stride = 4,
855 .val_bits = 32,
856 .max_register = VERSION,
857 .cache_type = REGCACHE_FLAT,
858 };
859
rk3568_soc_init(struct device * dev)860 static int rk3568_soc_init(struct device *dev)
861 {
862 struct rk_codec_digital_priv *rcd = dev_get_drvdata(dev);
863
864 if (IS_ERR(rcd->grf))
865 return PTR_ERR(rcd->grf);
866
867 /* enable internal codec to i2s3 */
868 return regmap_write(rcd->grf, RK3568_GRF_SOC_CON2,
869 (BIT(13) << 16 | BIT(13)));
870 }
871
rk3568_soc_deinit(struct device * dev)872 static void rk3568_soc_deinit(struct device *dev)
873 {
874 struct rk_codec_digital_priv *rcd = dev_get_drvdata(dev);
875
876 if (IS_ERR(rcd->grf))
877 return;
878
879 regmap_write(rcd->grf, RK3568_GRF_SOC_CON2, (BIT(13) << 16));
880 }
881
882 static const struct rk_codec_digital_soc_data rk3568_data = {
883 .init = rk3568_soc_init,
884 .deinit = rk3568_soc_deinit,
885 };
886
rk3588_soc_init(struct device * dev)887 static int rk3588_soc_init(struct device *dev)
888 {
889 struct rk_codec_digital_priv *rcd = dev_get_drvdata(dev);
890
891 if (IS_ERR(rcd->grf))
892 return PTR_ERR(rcd->grf);
893
894 /* enable internal codec to i2s3 */
895 return regmap_write(rcd->grf, RK3588_GRF_SOC_CON6,
896 (BIT(11) << 16 | BIT(11)));
897 }
898
rk3588_soc_deinit(struct device * dev)899 static void rk3588_soc_deinit(struct device *dev)
900 {
901 struct rk_codec_digital_priv *rcd = dev_get_drvdata(dev);
902
903 if (IS_ERR(rcd->grf))
904 return;
905
906 regmap_write(rcd->grf, RK3588_GRF_SOC_CON6, (BIT(11) << 16));
907 }
908
909 static const struct rk_codec_digital_soc_data rk3588_data = {
910 .init = rk3588_soc_init,
911 .deinit = rk3588_soc_deinit,
912 };
913
rv1106_soc_init(struct device * dev)914 static int rv1106_soc_init(struct device *dev)
915 {
916 struct rk_codec_digital_priv *rcd = dev_get_drvdata(dev);
917
918 if (IS_ERR(rcd->grf))
919 return PTR_ERR(rcd->grf);
920
921 /* enable internal codec to i2s0 */
922 return regmap_write(rcd->grf, RV1106_GRF_SOC_CON1,
923 (BIT(8) << 16 | BIT(8)));
924 }
925
rv1106_soc_deinit(struct device * dev)926 static void rv1106_soc_deinit(struct device *dev)
927 {
928 struct rk_codec_digital_priv *rcd = dev_get_drvdata(dev);
929
930 if (IS_ERR(rcd->grf))
931 return;
932
933 regmap_write(rcd->grf, RV1106_GRF_SOC_CON1, (BIT(8) << 16));
934 }
935
936 static const struct rk_codec_digital_soc_data rv1106_data = {
937 .init = rv1106_soc_init,
938 .deinit = rv1106_soc_deinit,
939 };
940
rv1126_soc_init(struct device * dev)941 static int rv1126_soc_init(struct device *dev)
942 {
943 struct rk_codec_digital_priv *rcd = dev_get_drvdata(dev);
944
945 if (IS_ERR(rcd->grf))
946 return PTR_ERR(rcd->grf);
947
948 /* enable internal codec to i2s0 */
949 return regmap_write(rcd->grf, RV1126_GRF_SOC_CON2,
950 (BIT(13) << 16 | BIT(13)));
951 }
952
rv1126_soc_deinit(struct device * dev)953 static void rv1126_soc_deinit(struct device *dev)
954 {
955 struct rk_codec_digital_priv *rcd = dev_get_drvdata(dev);
956
957 if (IS_ERR(rcd->grf))
958 return;
959
960 regmap_write(rcd->grf, RV1126_GRF_SOC_CON2, (BIT(13) << 16));
961 }
962
963 static const struct rk_codec_digital_soc_data rv1126_data = {
964 .init = rv1126_soc_init,
965 .deinit = rv1126_soc_deinit,
966 };
967
968 #ifdef CONFIG_OF
969 static const struct of_device_id rcd_of_match[] = {
970 { .compatible = "rockchip,codec-digital-v1", },
971 #ifdef CONFIG_CPU_RK3568
972 { .compatible = "rockchip,rk3568-codec-digital", .data = &rk3568_data },
973 #endif
974 #ifdef CONFIG_CPU_RK3588
975 { .compatible = "rockchip,rk3588-codec-digital", .data = &rk3588_data },
976 #endif
977 #ifdef CONFIG_CPU_RV1106
978 { .compatible = "rockchip,rv1106-codec-digital", .data = &rv1106_data },
979 #endif
980 #ifdef CONFIG_CPU_RV1126
981 { .compatible = "rockchip,rv1126-codec-digital", .data = &rv1126_data },
982 #endif
983 {},
984 };
985 MODULE_DEVICE_TABLE(of, rcd_of_match);
986 #endif
987
988 #ifdef CONFIG_PM
rk_codec_digital_runtime_resume(struct device * dev)989 static int rk_codec_digital_runtime_resume(struct device *dev)
990 {
991 struct rk_codec_digital_priv *rcd = dev_get_drvdata(dev);
992 int ret = 0;
993
994 ret = clk_prepare_enable(rcd->pclk);
995 if (ret)
996 return ret;
997
998 regcache_cache_only(rcd->regmap, false);
999 regcache_mark_dirty(rcd->regmap);
1000
1001 ret = regcache_sync(rcd->regmap);
1002 if (ret)
1003 goto err;
1004
1005 ret = clk_prepare_enable(rcd->clk_adc);
1006 if (ret)
1007 goto err;
1008
1009 ret = clk_prepare_enable(rcd->clk_dac);
1010 if (ret)
1011 goto err_adc;
1012
1013 ret = clk_prepare_enable(rcd->clk_i2c);
1014 if (ret)
1015 goto err_dac;
1016
1017 return 0;
1018
1019 err_dac:
1020 clk_disable_unprepare(rcd->clk_dac);
1021 err_adc:
1022 clk_disable_unprepare(rcd->clk_adc);
1023 err:
1024 clk_disable_unprepare(rcd->pclk);
1025
1026 return ret;
1027 }
1028
rk_codec_digital_runtime_suspend(struct device * dev)1029 static int rk_codec_digital_runtime_suspend(struct device *dev)
1030 {
1031 struct rk_codec_digital_priv *rcd = dev_get_drvdata(dev);
1032
1033 regcache_cache_only(rcd->regmap, true);
1034 clk_disable_unprepare(rcd->clk_adc);
1035 clk_disable_unprepare(rcd->clk_dac);
1036 clk_disable_unprepare(rcd->clk_i2c);
1037 clk_disable_unprepare(rcd->pclk);
1038
1039 return 0;
1040 }
1041 #endif
1042
rk_codec_digital_platform_probe(struct platform_device * pdev)1043 static int rk_codec_digital_platform_probe(struct platform_device *pdev)
1044 {
1045 struct device_node *np = pdev->dev.of_node;
1046 struct rk_codec_digital_priv *rcd;
1047 struct resource *res;
1048 void __iomem *base;
1049 int ret = 0;
1050
1051 rcd = devm_kzalloc(&pdev->dev, sizeof(*rcd), GFP_KERNEL);
1052 if (!rcd)
1053 return -ENOMEM;
1054
1055 rcd->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1056 rcd->pwmout = of_property_read_bool(np, "rockchip,pwm-output-mode");
1057 rcd->sync = of_property_read_bool(np, "rockchip,clk-sync-mode");
1058 if (of_property_read_u32(np, "rockchip,pa-ctl-delay-ms",
1059 &rcd->pa_ctl_delay_ms))
1060 rcd->pa_ctl_delay_ms = 0;
1061
1062 rcd->rc = devm_reset_control_get(&pdev->dev, "reset");
1063
1064 /* optional on some platform */
1065 rcd->clk_adc = devm_clk_get_optional(&pdev->dev, "adc");
1066 if (IS_ERR(rcd->clk_adc))
1067 return PTR_ERR(rcd->clk_adc);
1068
1069 rcd->clk_dac = devm_clk_get(&pdev->dev, "dac");
1070 if (IS_ERR(rcd->clk_dac))
1071 return PTR_ERR(rcd->clk_dac);
1072
1073 /* optional on some platform */
1074 rcd->clk_i2c = devm_clk_get_optional(&pdev->dev, "i2c");
1075 if (IS_ERR(rcd->clk_i2c))
1076 return PTR_ERR(rcd->clk_i2c);
1077
1078 rcd->pclk = devm_clk_get(&pdev->dev, "pclk");
1079 if (IS_ERR(rcd->pclk))
1080 return PTR_ERR(rcd->pclk);
1081
1082 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1083 base = devm_ioremap_resource(&pdev->dev, res);
1084 if (IS_ERR(base))
1085 return PTR_ERR(base);
1086
1087 rcd->regmap =
1088 devm_regmap_init_mmio(&pdev->dev, base, &rcd_regmap_config);
1089 if (IS_ERR(rcd->regmap))
1090 return PTR_ERR(rcd->regmap);
1091
1092 platform_set_drvdata(pdev, rcd);
1093
1094 rcd->data = of_device_get_match_data(&pdev->dev);
1095 if (rcd->data && rcd->data->init) {
1096 ret = rcd->data->init(&pdev->dev);
1097 if (ret)
1098 return ret;
1099 }
1100
1101 pm_runtime_enable(&pdev->dev);
1102 if (!pm_runtime_enabled(&pdev->dev)) {
1103 ret = rk_codec_digital_runtime_resume(&pdev->dev);
1104 if (ret)
1105 goto err_pm_disable;
1106 }
1107
1108 if (rcd->pwmout)
1109 regmap_update_bits(rcd->regmap, DACPWM_CTRL,
1110 ACDCDIG_DACPWM_CTRL_PWM_MODE_MASK,
1111 ACDCDIG_DACPWM_CTRL_PWM_MODE_0);
1112
1113 rcd->pa_ctl = devm_gpiod_get_optional(&pdev->dev, "pa-ctl",
1114 GPIOD_OUT_LOW);
1115
1116 if (!rcd->pa_ctl) {
1117 dev_info(&pdev->dev, "no need pa-ctl gpio\n");
1118 } else if (IS_ERR(rcd->pa_ctl)) {
1119 ret = PTR_ERR(rcd->pa_ctl);
1120 dev_err(&pdev->dev, "fail to request gpio pa-ctl\n");
1121 goto err_suspend;
1122 }
1123
1124 ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_dev_rcd,
1125 rcd_dai, ARRAY_SIZE(rcd_dai));
1126
1127 if (ret)
1128 goto err_suspend;
1129
1130 return 0;
1131
1132 err_suspend:
1133 if (!pm_runtime_status_suspended(&pdev->dev))
1134 rk_codec_digital_runtime_suspend(&pdev->dev);
1135 err_pm_disable:
1136 pm_runtime_disable(&pdev->dev);
1137
1138 if (rcd->data && rcd->data->deinit)
1139 rcd->data->deinit(&pdev->dev);
1140
1141 return ret;
1142 }
1143
rk_codec_digital_platform_remove(struct platform_device * pdev)1144 static int rk_codec_digital_platform_remove(struct platform_device *pdev)
1145 {
1146 struct rk_codec_digital_priv *rcd = dev_get_drvdata(&pdev->dev);
1147
1148 pm_runtime_disable(&pdev->dev);
1149 if (!pm_runtime_status_suspended(&pdev->dev))
1150 rk_codec_digital_runtime_suspend(&pdev->dev);
1151
1152 if (rcd->data && rcd->data->deinit)
1153 rcd->data->deinit(&pdev->dev);
1154
1155 return 0;
1156 }
1157
1158 static const struct dev_pm_ops rcd_pm = {
1159 SET_RUNTIME_PM_OPS(rk_codec_digital_runtime_suspend,
1160 rk_codec_digital_runtime_resume, NULL)
1161 };
1162
1163 static struct platform_driver rk_codec_digital_driver = {
1164 .driver = {
1165 .name = "rk_codec_digital",
1166 .of_match_table = of_match_ptr(rcd_of_match),
1167 .pm = &rcd_pm,
1168 },
1169 .probe = rk_codec_digital_platform_probe,
1170 .remove = rk_codec_digital_platform_remove,
1171 };
1172 module_platform_driver(rk_codec_digital_driver);
1173
1174 MODULE_AUTHOR("Sugar Zhang <sugar.zhang@rock-chips.com>");
1175 MODULE_DESCRIPTION("ASoC Rockchip codec digital driver");
1176 MODULE_LICENSE("GPL v2");
1177