1 /*
2 * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #include <linux/clk.h>
16 #include <linux/device.h>
17 #include <linux/delay.h>
18 #include <linux/mfd/rk808.h>
19 #include <linux/module.h>
20 #include <linux/of.h>
21 #include <linux/of_gpio.h>
22 #include <linux/platform_device.h>
23 #include <linux/regmap.h>
24 #include <sound/core.h>
25 #include <sound/pcm_params.h>
26 #include <sound/soc.h>
27 #include "rk817_codec.h"
28
29 #ifdef CONFIG_SND_DEBUG
30 #define DBG(args...) pr_info(args)
31 #else
32 #define DBG(args...)
33 #endif
34
35 /* For route */
36 #define RK817_CODEC_PLAYBACK 1
37 #define RK817_CODEC_CAPTURE 2
38 #define RK817_CODEC_INCALL 4
39 #define RK817_CODEC_ALL (RK817_CODEC_PLAYBACK |\
40 RK817_CODEC_CAPTURE | RK817_CODEC_INCALL)
41
42 /*
43 * DDAC L/R volume setting
44 * 0db~-95db,0.375db/step,for example:
45 * 0: 0dB
46 * 0x0a: -3.75dB
47 * 0x7d: -46dB
48 * 0xff: -95dB
49 */
50 #define OUT_VOLUME (0x03)
51
52 /*
53 * DADC L/R volume setting
54 * 0db~-95db,0.375db/step,for example:
55 * 0: 0dB
56 * 0x0a: -3.75dB
57 * 0x7d: -46dB
58 * 0xff: -95dB
59 */
60 #define CAPTURE_VOLUME (0x0)
61
62 #define CODEC_SET_SPK 1
63 #define CODEC_SET_HP 2
64
65 struct rk817_codec_priv {
66 struct snd_soc_component *component;
67 struct regmap *regmap;
68 struct rk808 *rk817;
69 struct clk *mclk;
70 struct mutex clk_lock;
71
72 unsigned int clk_capture;
73 unsigned int clk_playback;
74 unsigned int stereo_sysclk;
75 unsigned int rate;
76
77 unsigned int spk_volume;
78 unsigned int hp_volume;
79 unsigned int capture_volume;
80
81 bool mic_in_differential;
82 bool pdmdata_out_enable;
83 bool use_ext_amplifier;
84 bool adc_for_loopback;
85 bool resume_path;
86
87 bool out_l2spk_r2hp;
88 long int playback_path;
89 long int capture_path;
90
91 struct gpio_desc *spk_ctl_gpio;
92 struct gpio_desc *hp_ctl_gpio;
93 int spk_mute_delay;
94 int hp_mute_delay;
95 int chip_ver;
96 };
97
98 static const struct reg_default rk817_reg_defaults[] = {
99 { RK817_CODEC_DTOP_VUCTL, 0x003 },
100 { RK817_CODEC_DTOP_VUCTIME, 0x00 },
101 { RK817_CODEC_DTOP_LPT_SRST, 0x00 },
102 { RK817_CODEC_DTOP_DIGEN_CLKE, 0x00 },
103 { RK817_CODEC_AREF_RTCFG0, 0x00 },
104 { RK817_CODEC_AREF_RTCFG1, 0x06 },
105 { RK817_CODEC_AADC_CFG0, 0xc8 },
106 { RK817_CODEC_AADC_CFG1, 0x00 },
107 { RK817_CODEC_DADC_VOLL, 0x00 },
108 { RK817_CODEC_DADC_VOLR, 0x00 },
109 { RK817_CODEC_DADC_SR_ACL0, 0x00 },
110 { RK817_CODEC_DADC_ALC1, 0x00 },
111 { RK817_CODEC_DADC_ALC2, 0x00 },
112 { RK817_CODEC_DADC_NG, 0x00 },
113 { RK817_CODEC_DADC_HPF, 0x00 },
114 { RK817_CODEC_DADC_RVOLL, 0xff },
115 { RK817_CODEC_DADC_RVOLR, 0xff },
116 { RK817_CODEC_AMIC_CFG0, 0x70 },
117 { RK817_CODEC_AMIC_CFG1, 0x00 },
118 { RK817_CODEC_DMIC_PGA_GAIN, 0x66 },
119 { RK817_CODEC_DMIC_LMT1, 0x00 },
120 { RK817_CODEC_DMIC_LMT2, 0x00 },
121 { RK817_CODEC_DMIC_NG1, 0x00 },
122 { RK817_CODEC_DMIC_NG2, 0x00 },
123 { RK817_CODEC_ADAC_CFG0, 0x00 },
124 { RK817_CODEC_ADAC_CFG1, 0x07 },
125 { RK817_CODEC_DDAC_POPD_DACST, 0x82 },
126 { RK817_CODEC_DDAC_VOLL, 0x00 },
127 { RK817_CODEC_DDAC_VOLR, 0x00 },
128 { RK817_CODEC_DDAC_SR_LMT0, 0x00 },
129 { RK817_CODEC_DDAC_LMT1, 0x00 },
130 { RK817_CODEC_DDAC_LMT2, 0x00 },
131 { RK817_CODEC_DDAC_MUTE_MIXCTL, 0xa0 },
132 { RK817_CODEC_DDAC_RVOLL, 0xff },
133 { RK817_CODEC_DDAC_RVOLR, 0xff },
134 { RK817_CODEC_AHP_ANTI0, 0x00 },
135 { RK817_CODEC_AHP_ANTI1, 0x00 },
136 { RK817_CODEC_AHP_CFG0, 0xe0 },
137 { RK817_CODEC_AHP_CFG1, 0x1f },
138 { RK817_CODEC_AHP_CP, 0x09 },
139 { RK817_CODEC_ACLASSD_CFG1, 0x69 },
140 { RK817_CODEC_ACLASSD_CFG2, 0x44 },
141 { RK817_CODEC_APLL_CFG0, 0x04 },
142 { RK817_CODEC_APLL_CFG1, 0x00 },
143 { RK817_CODEC_APLL_CFG2, 0x30 },
144 { RK817_CODEC_APLL_CFG3, 0x19 },
145 { RK817_CODEC_APLL_CFG4, 0x65 },
146 { RK817_CODEC_APLL_CFG5, 0x01 },
147 { RK817_CODEC_DI2S_CKM, 0x01 },
148 { RK817_CODEC_DI2S_RSD, 0x00 },
149 { RK817_CODEC_DI2S_RXCR1, 0x00 },
150 { RK817_CODEC_DI2S_RXCR2, 0x17 },
151 { RK817_CODEC_DI2S_RXCMD_TSD, 0x00 },
152 { RK817_CODEC_DI2S_TXCR1, 0x00 },
153 { RK817_CODEC_DI2S_TXCR2, 0x17 },
154 { RK817_CODEC_DI2S_TXCR3_TXCMD, 0x00 },
155 };
156
rk817_volatile_register(struct device * dev,unsigned int reg)157 static bool rk817_volatile_register(struct device *dev, unsigned int reg)
158 {
159 switch (reg) {
160 case RK817_CODEC_DTOP_LPT_SRST:
161 case RK817_PMIC_CHIP_NAME:
162 case RK817_PMIC_CHIP_VER:
163 return true;
164 default:
165 return false;
166 }
167 }
168
rk817_codec_register(struct device * dev,unsigned int reg)169 static bool rk817_codec_register(struct device *dev, unsigned int reg)
170 {
171 switch (reg) {
172 case RK817_CODEC_DTOP_VUCTL:
173 case RK817_CODEC_DTOP_VUCTIME:
174 case RK817_CODEC_DTOP_LPT_SRST:
175 case RK817_CODEC_DTOP_DIGEN_CLKE:
176 case RK817_CODEC_AREF_RTCFG0:
177 case RK817_CODEC_AREF_RTCFG1:
178 case RK817_CODEC_AADC_CFG0:
179 case RK817_CODEC_AADC_CFG1:
180 case RK817_CODEC_DADC_VOLL:
181 case RK817_CODEC_DADC_VOLR:
182 case RK817_CODEC_DADC_SR_ACL0:
183 case RK817_CODEC_DADC_ALC1:
184 case RK817_CODEC_DADC_ALC2:
185 case RK817_CODEC_DADC_NG:
186 case RK817_CODEC_DADC_HPF:
187 case RK817_CODEC_DADC_RVOLL:
188 case RK817_CODEC_DADC_RVOLR:
189 case RK817_CODEC_AMIC_CFG0:
190 case RK817_CODEC_AMIC_CFG1:
191 case RK817_CODEC_DMIC_PGA_GAIN:
192 case RK817_CODEC_DMIC_LMT1:
193 case RK817_CODEC_DMIC_LMT2:
194 case RK817_CODEC_DMIC_NG1:
195 case RK817_CODEC_DMIC_NG2:
196 case RK817_CODEC_ADAC_CFG0:
197 case RK817_CODEC_ADAC_CFG1:
198 case RK817_CODEC_DDAC_POPD_DACST:
199 case RK817_CODEC_DDAC_VOLL:
200 case RK817_CODEC_DDAC_VOLR:
201 case RK817_CODEC_DDAC_SR_LMT0:
202 case RK817_CODEC_DDAC_LMT1:
203 case RK817_CODEC_DDAC_LMT2:
204 case RK817_CODEC_DDAC_MUTE_MIXCTL:
205 case RK817_CODEC_DDAC_RVOLL:
206 case RK817_CODEC_DDAC_RVOLR:
207 case RK817_CODEC_AHP_ANTI0:
208 case RK817_CODEC_AHP_ANTI1:
209 case RK817_CODEC_AHP_CFG0:
210 case RK817_CODEC_AHP_CFG1:
211 case RK817_CODEC_AHP_CP:
212 case RK817_CODEC_ACLASSD_CFG1:
213 case RK817_CODEC_ACLASSD_CFG2:
214 case RK817_CODEC_APLL_CFG0:
215 case RK817_CODEC_APLL_CFG1:
216 case RK817_CODEC_APLL_CFG2:
217 case RK817_CODEC_APLL_CFG3:
218 case RK817_CODEC_APLL_CFG4:
219 case RK817_CODEC_APLL_CFG5:
220 case RK817_CODEC_DI2S_CKM:
221 case RK817_CODEC_DI2S_RSD:
222 case RK817_CODEC_DI2S_RXCR1:
223 case RK817_CODEC_DI2S_RXCR2:
224 case RK817_CODEC_DI2S_RXCMD_TSD:
225 case RK817_CODEC_DI2S_TXCR1:
226 case RK817_CODEC_DI2S_TXCR2:
227 case RK817_CODEC_DI2S_TXCR3_TXCMD:
228 case RK817_PMIC_CHIP_NAME:
229 case RK817_PMIC_CHIP_VER:
230 return true;
231 default:
232 return false;
233 }
234 }
235
rk817_codec_ctl_gpio(struct rk817_codec_priv * rk817,int gpio,int level)236 static int rk817_codec_ctl_gpio(struct rk817_codec_priv *rk817,
237 int gpio, int level)
238 {
239 if ((gpio & CODEC_SET_SPK) &&
240 rk817->spk_ctl_gpio) {
241 gpiod_set_value(rk817->spk_ctl_gpio, level);
242 DBG("%s set spk clt %d\n", __func__, level);
243 msleep(rk817->spk_mute_delay);
244 }
245
246 if ((gpio & CODEC_SET_HP) &&
247 rk817->hp_ctl_gpio) {
248 gpiod_set_value(rk817->hp_ctl_gpio, level);
249 DBG("%s set hp clt %d\n", __func__, level);
250 msleep(rk817->hp_mute_delay);
251 }
252
253 return 0;
254 }
255
rk817_reset(struct snd_soc_component * component)256 static int rk817_reset(struct snd_soc_component *component)
257 {
258 struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component);
259
260 snd_soc_component_write(component, RK817_CODEC_DTOP_LPT_SRST, 0x40);
261 snd_soc_component_write(component, RK817_CODEC_DDAC_POPD_DACST, 0x02);
262 snd_soc_component_write(component, RK817_CODEC_DI2S_CKM, 0x00);
263 snd_soc_component_write(component, RK817_CODEC_DTOP_DIGEN_CLKE, 0xff);
264 snd_soc_component_write(component, RK817_CODEC_APLL_CFG1, 0x58);
265 snd_soc_component_write(component, RK817_CODEC_APLL_CFG2, 0x2d);
266 snd_soc_component_write(component, RK817_CODEC_APLL_CFG3, 0x0c);
267 snd_soc_component_write(component, RK817_CODEC_APLL_CFG5, 0x00);
268 snd_soc_component_write(component, RK817_CODEC_DTOP_DIGEN_CLKE, 0x00);
269 if (rk817->chip_ver <= 0x4) {
270 DBG("%s (%d): SMIC TudorAG and previous versions\n",
271 __func__, __LINE__);
272 snd_soc_component_write(component, RK817_CODEC_APLL_CFG0, 0x0c);
273 snd_soc_component_write(component, RK817_CODEC_APLL_CFG4, 0x95);
274 } else {
275 DBG("%s (%d): SMIC TudorAG version later\n",
276 __func__, __LINE__);
277 snd_soc_component_write(component, RK817_CODEC_APLL_CFG0, 0x04);
278 snd_soc_component_write(component, RK817_CODEC_APLL_CFG4, 0xa5);
279 }
280 snd_soc_component_write(component, RK817_CODEC_DTOP_DIGEN_CLKE, 0x00);
281
282 return 0;
283 }
284
285 static struct rk817_reg_val_typ playback_power_up_list[] = {
286 {RK817_CODEC_AREF_RTCFG1, 0x40},
287 {RK817_CODEC_DDAC_POPD_DACST, 0x02},
288 /* APLL */
289 /* {RK817_CODEC_APLL_CFG0, 0x04}, */
290 {RK817_CODEC_APLL_CFG1, 0x58},
291 {RK817_CODEC_APLL_CFG2, 0x2d},
292 /* {RK817_CODEC_APLL_CFG4, 0xa5}, */
293 {RK817_CODEC_APLL_CFG5, 0x00},
294
295 {RK817_CODEC_DI2S_RXCMD_TSD, 0x00},
296 {RK817_CODEC_DI2S_RSD, 0x00},
297 /* {RK817_CODEC_DI2S_CKM, 0x00}, */
298 {RK817_CODEC_DI2S_RXCR1, 0x00},
299 {RK817_CODEC_DI2S_RXCMD_TSD, 0x20},
300 {RK817_CODEC_DTOP_VUCTIME, 0xf4},
301 {RK817_CODEC_DDAC_MUTE_MIXCTL, 0x00},
302
303 {RK817_CODEC_DDAC_VOLL, 0x0a},
304 {RK817_CODEC_DDAC_VOLR, 0x0a},
305 };
306
307 #define RK817_CODEC_PLAYBACK_POWER_UP_LIST_LEN \
308 ARRAY_SIZE(playback_power_up_list)
309
310 static struct rk817_reg_val_typ playback_power_down_list[] = {
311 {RK817_CODEC_DDAC_MUTE_MIXCTL, 0x01},
312 {RK817_CODEC_ADAC_CFG1, 0x0f},
313 /* HP */
314 {RK817_CODEC_AHP_CFG0, 0xe0},
315 {RK817_CODEC_AHP_CP, 0x09},
316 /* SPK */
317 {RK817_CODEC_ACLASSD_CFG1, 0x69},
318 };
319
320 #define RK817_CODEC_PLAYBACK_POWER_DOWN_LIST_LEN \
321 ARRAY_SIZE(playback_power_down_list)
322
323 static struct rk817_reg_val_typ capture_power_up_list[] = {
324 {RK817_CODEC_AREF_RTCFG1, 0x40},
325 {RK817_CODEC_DADC_SR_ACL0, 0x02},
326 /* {RK817_CODEC_DTOP_DIGEN_CLKE, 0xff}, */
327 /* {RK817_CODEC_APLL_CFG0, 0x04}, */
328 {RK817_CODEC_APLL_CFG1, 0x58},
329 {RK817_CODEC_APLL_CFG2, 0x2d},
330 /* {RK817_CODEC_APLL_CFG4, 0xa5}, */
331 {RK817_CODEC_APLL_CFG5, 0x00},
332
333 /*{RK817_CODEC_DI2S_RXCMD_TSD, 0x00},*/
334 {RK817_CODEC_DI2S_RSD, 0x00},
335 /* {RK817_CODEC_DI2S_CKM, 0x00}, */
336 {RK817_CODEC_DI2S_RXCR1, 0x00},
337 {RK817_CODEC_DI2S_RXCMD_TSD, 0x20},
338 {RK817_CODEC_DTOP_VUCTIME, 0xf4},
339
340 {RK817_CODEC_DDAC_MUTE_MIXCTL, 0x00},
341 {RK817_CODEC_AADC_CFG0, 0x00},
342 {RK817_CODEC_AMIC_CFG0, 0x0a},
343 {RK817_CODEC_AMIC_CFG1, 0x30},
344 {RK817_CODEC_DI2S_TXCR3_TXCMD, 0x88},
345 {RK817_CODEC_DDAC_POPD_DACST, 0x02},
346 /* 0x29: -18db to 27db */
347 {RK817_CODEC_DMIC_PGA_GAIN, 0xaa},
348 };
349
350 #define RK817_CODEC_CAPTURE_POWER_UP_LIST_LEN \
351 ARRAY_SIZE(capture_power_up_list)
352
353 static struct rk817_reg_val_typ capture_power_down_list[] = {
354 {RK817_CODEC_AADC_CFG0, 0xc8},
355 {RK817_CODEC_AMIC_CFG0, 0x70},
356 };
357
358 #define RK817_CODEC_CAPTURE_POWER_DOWN_LIST_LEN \
359 ARRAY_SIZE(capture_power_down_list)
360
rk817_codec_power_up(struct snd_soc_component * component,int type)361 static int rk817_codec_power_up(struct snd_soc_component *component, int type)
362 {
363 struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component);
364 int i;
365
366 DBG("%s : power up %s %s %s\n", __func__,
367 type & RK817_CODEC_PLAYBACK ? "playback" : "",
368 type & RK817_CODEC_CAPTURE ? "capture" : "",
369 type & RK817_CODEC_INCALL ? "incall" : "");
370
371 if (type & RK817_CODEC_PLAYBACK) {
372 snd_soc_component_update_bits(component,
373 RK817_CODEC_DTOP_DIGEN_CLKE,
374 DAC_DIG_CLK_MASK, DAC_DIG_CLK_EN);
375 for (i = 0; i < RK817_CODEC_PLAYBACK_POWER_UP_LIST_LEN; i++) {
376 snd_soc_component_write(component,
377 playback_power_up_list[i].reg,
378 playback_power_up_list[i].value);
379 }
380
381 /* configure APLL CFG0/4 */
382 if (rk817->chip_ver <= 0x4) {
383 DBG("%s (%d): SMIC TudorAG and previous versions\n",
384 __func__, __LINE__);
385 snd_soc_component_write(component, RK817_CODEC_APLL_CFG0, 0x0c);
386 snd_soc_component_write(component, RK817_CODEC_APLL_CFG4, 0x95);
387 } else {
388 DBG("%s: SMIC TudorAG version later\n", __func__);
389 snd_soc_component_write(component, RK817_CODEC_APLL_CFG0, 0x04);
390 snd_soc_component_write(component, RK817_CODEC_APLL_CFG4, 0xa5);
391 }
392
393 snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE,
394 DAC_DIG_CLK_MASK, DAC_DIG_CLK_DIS);
395 usleep_range(2000, 2500);
396 snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE,
397 DAC_DIG_CLK_MASK, DAC_DIG_CLK_EN);
398 DBG("%s: %d - Playback DIG CLK OPS\n", __func__, __LINE__);
399 }
400
401 if (type & RK817_CODEC_CAPTURE) {
402 snd_soc_component_update_bits(component,
403 RK817_CODEC_DTOP_DIGEN_CLKE,
404 ADC_DIG_CLK_MASK,
405 ADC_DIG_CLK_EN);
406 for (i = 0; i < RK817_CODEC_CAPTURE_POWER_UP_LIST_LEN; i++) {
407 snd_soc_component_write(component,
408 capture_power_up_list[i].reg,
409 capture_power_up_list[i].value);
410 }
411
412 /* configure APLL CFG0/4 */
413 if (rk817->chip_ver <= 0x4) {
414 DBG("%s (%d): SMIC TudorAG and previous versions\n",
415 __func__, __LINE__);
416 snd_soc_component_write(component, RK817_CODEC_APLL_CFG0, 0x0c);
417 snd_soc_component_write(component, RK817_CODEC_APLL_CFG4, 0x95);
418 } else {
419 DBG("%s: SMIC TudorAG version later\n", __func__);
420 snd_soc_component_write(component, RK817_CODEC_APLL_CFG0, 0x04);
421 snd_soc_component_write(component, RK817_CODEC_APLL_CFG4, 0xa5);
422 }
423
424 snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE,
425 ADC_DIG_CLK_MASK, DAC_DIG_CLK_DIS);
426 usleep_range(2000, 2500);
427 snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE,
428 ADC_DIG_CLK_MASK, ADC_DIG_CLK_EN);
429 DBG("%s: %d - Capture DIG CLK OPS\n", __func__, __LINE__);
430
431 if (rk817->mic_in_differential)
432 snd_soc_component_update_bits(component,
433 RK817_CODEC_AMIC_CFG0,
434 MIC_DIFF_MASK, MIC_DIFF_EN);
435 else
436 snd_soc_component_update_bits(component,
437 RK817_CODEC_AMIC_CFG0,
438 MIC_DIFF_MASK,
439 MIC_DIFF_DIS);
440
441 if (rk817->pdmdata_out_enable)
442 snd_soc_component_update_bits(component,
443 RK817_CODEC_DI2S_CKM,
444 PDM_EN_MASK,
445 PDM_EN_ENABLE);
446
447 snd_soc_component_write(component, RK817_CODEC_DADC_VOLL,
448 rk817->capture_volume);
449 snd_soc_component_write(component, RK817_CODEC_DADC_VOLR,
450 rk817->capture_volume);
451 }
452
453 return 0;
454 }
455
rk817_codec_power_down(struct snd_soc_component * component,int type)456 static int rk817_codec_power_down(struct snd_soc_component *component, int type)
457 {
458 int i;
459
460 DBG("%s : power down %s %s %s\n", __func__,
461 type & RK817_CODEC_PLAYBACK ? "playback" : "",
462 type & RK817_CODEC_CAPTURE ? "capture" : "",
463 type & RK817_CODEC_INCALL ? "incall" : "");
464
465 /* mute output for pop noise */
466 if ((type & RK817_CODEC_PLAYBACK) ||
467 (type & RK817_CODEC_INCALL)) {
468 snd_soc_component_update_bits(component,
469 RK817_CODEC_DDAC_MUTE_MIXCTL,
470 DACMT_ENABLE, DACMT_ENABLE);
471 }
472
473 if (type & RK817_CODEC_CAPTURE) {
474 for (i = 0; i < RK817_CODEC_CAPTURE_POWER_DOWN_LIST_LEN; i++) {
475 snd_soc_component_write(component,
476 capture_power_down_list[i].reg,
477 capture_power_down_list[i].value);
478 }
479 snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE,
480 ADC_DIG_CLK_MASK, ADC_DIG_CLK_DIS);
481 }
482
483 if (type & RK817_CODEC_PLAYBACK) {
484 for (i = 0; i < RK817_CODEC_PLAYBACK_POWER_DOWN_LIST_LEN; i++) {
485 snd_soc_component_write(component,
486 playback_power_down_list[i].reg,
487 playback_power_down_list[i].value);
488 }
489 snd_soc_component_update_bits(component,
490 RK817_CODEC_DTOP_DIGEN_CLKE,
491 DAC_DIG_CLK_MASK, DAC_DIG_CLK_DIS);
492 }
493
494 if (type == RK817_CODEC_ALL) {
495 for (i = 0; i < RK817_CODEC_PLAYBACK_POWER_DOWN_LIST_LEN; i++) {
496 snd_soc_component_write(component,
497 playback_power_down_list[i].reg,
498 playback_power_down_list[i].value);
499 }
500 for (i = 0; i < RK817_CODEC_CAPTURE_POWER_DOWN_LIST_LEN; i++) {
501 snd_soc_component_write(component,
502 capture_power_down_list[i].reg,
503 capture_power_down_list[i].value);
504 }
505 snd_soc_component_write(component, RK817_CODEC_DTOP_DIGEN_CLKE, 0x00);
506 snd_soc_component_write(component, RK817_CODEC_APLL_CFG5, 0x01);
507 snd_soc_component_write(component, RK817_CODEC_AREF_RTCFG1, 0x06);
508 }
509
510 return 0;
511 }
512
513 /* For tiny alsa playback/capture/voice call path */
514 static const char * const rk817_playback_path_mode[] = {
515 "OFF", "RCV", "SPK", "HP", "HP_NO_MIC", "BT", "SPK_HP", /* 0-6 */
516 "RING_SPK", "RING_HP", "RING_HP_NO_MIC", "RING_SPK_HP"}; /* 7-10 */
517
518 static const char * const rk817_capture_path_mode[] = {
519 "MIC OFF", "Main Mic", "Hands Free Mic", "BT Sco Mic"};
520
521 static const char * const rk817_binary_mode[] = {"OFF", "ON"};
522
523 static SOC_ENUM_SINGLE_DECL(rk817_playback_path_type,
524 0, 0, rk817_playback_path_mode);
525
526 static SOC_ENUM_SINGLE_DECL(rk817_capture_path_type,
527 0, 0, rk817_capture_path_mode);
528
529 static SOC_ENUM_SINGLE_DECL(rk817_resume_path_type,
530 0, 0, rk817_binary_mode);
531
rk817_playback_path_config(struct snd_soc_component * component,long pre_path,long target_path)532 static int rk817_playback_path_config(struct snd_soc_component *component,
533 long pre_path, long target_path)
534 {
535 struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component);
536
537 rk817->playback_path = target_path;
538
539 DBG("%s : set playback_path %ld, pre_path %ld\n",
540 __func__, rk817->playback_path, pre_path);
541
542 mutex_lock(&rk817->clk_lock);
543 if (rk817->playback_path != OFF) {
544 if (rk817->clk_playback == 0) {
545 clk_prepare_enable(rk817->mclk);
546 rk817->clk_playback++;
547 }
548 } else {
549 if (rk817->clk_playback > 0) {
550 clk_disable_unprepare(rk817->mclk);
551 rk817->clk_playback--;
552 }
553 }
554 mutex_unlock(&rk817->clk_lock);
555
556 switch (rk817->playback_path) {
557 case OFF:
558 if (pre_path != OFF && (pre_path != HP_PATH &&
559 pre_path != HP_NO_MIC && pre_path != RING_HP &&
560 pre_path != RING_HP_NO_MIC)) {
561 rk817_codec_power_down(component, RK817_CODEC_PLAYBACK);
562 if (rk817->capture_path == 0)
563 rk817_codec_power_down(component, RK817_CODEC_ALL);
564 }
565 break;
566 case RCV:
567 case SPK_PATH:
568 case RING_SPK:
569 if (pre_path == OFF)
570 rk817_codec_power_up(component, RK817_CODEC_PLAYBACK);
571 if (rk817->out_l2spk_r2hp) {
572 /* for costdown: ldac -> ClassD rdac -> Hp */
573 /* HP_CP_EN , CP 2.3V */
574 snd_soc_component_write(component, RK817_CODEC_AHP_CP,
575 0x11);
576 /* power on HP two stage opamp ,HP amplitude 0db */
577 snd_soc_component_write(component, RK817_CODEC_AHP_CFG0,
578 0x80);
579 /* power on dac ibias/l/r */
580 snd_soc_component_write(component, RK817_CODEC_ADAC_CFG1,
581 PWD_DACBIAS_ON | PWD_DACD_ON |
582 PWD_DACL_ON | PWD_DACR_ON);
583 /* CLASS D mode */
584 snd_soc_component_write(component,
585 RK817_CODEC_DDAC_MUTE_MIXCTL,
586 0x18);
587 /* CLASS D enable */
588 snd_soc_component_write(component,
589 RK817_CODEC_ACLASSD_CFG1,
590 0xa5);
591 /* restart CLASS D, OCPP/N */
592 snd_soc_component_write(component,
593 RK817_CODEC_ACLASSD_CFG2,
594 0xf7);
595 } else if (!rk817->use_ext_amplifier) {
596 /* power on dac ibias/l/r */
597 snd_soc_component_write(component, RK817_CODEC_ADAC_CFG1,
598 PWD_DACBIAS_ON | PWD_DACD_ON |
599 PWD_DACL_DOWN | PWD_DACR_DOWN);
600 /* CLASS D mode */
601 snd_soc_component_write(component,
602 RK817_CODEC_DDAC_MUTE_MIXCTL,
603 0x10);
604 /* CLASS D enable */
605 snd_soc_component_write(component,
606 RK817_CODEC_ACLASSD_CFG1,
607 0xa5);
608 /* restart CLASS D, OCPP/N */
609 snd_soc_component_write(component,
610 RK817_CODEC_ACLASSD_CFG2,
611 0xf7);
612 } else {
613 /* HP_CP_EN , CP 2.3V */
614 snd_soc_component_write(component, RK817_CODEC_AHP_CP,
615 0x11);
616 /* power on HP two stage opamp ,HP amplitude 0db */
617 snd_soc_component_write(component, RK817_CODEC_AHP_CFG0,
618 0x80);
619 /* power on dac ibias/l/r */
620 snd_soc_component_write(component, RK817_CODEC_ADAC_CFG1,
621 PWD_DACBIAS_ON | PWD_DACD_DOWN |
622 PWD_DACL_ON | PWD_DACR_ON);
623 snd_soc_component_update_bits(component,
624 RK817_CODEC_DDAC_MUTE_MIXCTL,
625 DACMT_ENABLE, DACMT_DISABLE);
626 }
627 snd_soc_component_write(component, RK817_CODEC_DDAC_VOLL,
628 rk817->spk_volume);
629 snd_soc_component_write(component, RK817_CODEC_DDAC_VOLR,
630 rk817->spk_volume);
631 break;
632 case HP_PATH:
633 case HP_NO_MIC:
634 case RING_HP:
635 case RING_HP_NO_MIC:
636 if (pre_path == OFF)
637 rk817_codec_power_up(component, RK817_CODEC_PLAYBACK);
638 /* HP_CP_EN , CP 2.3V */
639 snd_soc_component_write(component, RK817_CODEC_AHP_CP, 0x11);
640 /* power on HP two stage opamp ,HP amplitude 0db */
641 snd_soc_component_write(component, RK817_CODEC_AHP_CFG0, 0x80);
642 /* power on dac ibias/l/r */
643 snd_soc_component_write(component, RK817_CODEC_ADAC_CFG1,
644 PWD_DACBIAS_ON | PWD_DACD_DOWN |
645 PWD_DACL_ON | PWD_DACR_ON);
646 snd_soc_component_update_bits(component,
647 RK817_CODEC_DDAC_MUTE_MIXCTL,
648 DACMT_ENABLE, DACMT_DISABLE);
649
650 snd_soc_component_write(component, RK817_CODEC_DDAC_VOLL,
651 rk817->hp_volume);
652 snd_soc_component_write(component, RK817_CODEC_DDAC_VOLR,
653 rk817->hp_volume);
654 break;
655 case BT:
656 break;
657 case SPK_HP:
658 case RING_SPK_HP:
659 if (pre_path == OFF)
660 rk817_codec_power_up(component, RK817_CODEC_PLAYBACK);
661
662 /* HP_CP_EN , CP 2.3V */
663 snd_soc_component_write(component, RK817_CODEC_AHP_CP, 0x11);
664 /* power on HP two stage opamp ,HP amplitude 0db */
665 snd_soc_component_write(component, RK817_CODEC_AHP_CFG0, 0x80);
666
667 /* power on dac ibias/l/r */
668 snd_soc_component_write(component, RK817_CODEC_ADAC_CFG1,
669 PWD_DACBIAS_ON | PWD_DACD_ON |
670 PWD_DACL_ON | PWD_DACR_ON);
671
672 if (!rk817->use_ext_amplifier) {
673 /* CLASS D mode */
674 snd_soc_component_write(component,
675 RK817_CODEC_DDAC_MUTE_MIXCTL,
676 0x10);
677 /* CLASS D enable */
678 snd_soc_component_write(component,
679 RK817_CODEC_ACLASSD_CFG1,
680 0xa5);
681 /* restart CLASS D, OCPP/N */
682 snd_soc_component_write(component,
683 RK817_CODEC_ACLASSD_CFG2,
684 0xf7);
685 }
686
687 snd_soc_component_write(component, RK817_CODEC_DDAC_VOLL,
688 rk817->hp_volume);
689 snd_soc_component_write(component, RK817_CODEC_DDAC_VOLR,
690 rk817->hp_volume);
691 break;
692 default:
693 return -EINVAL;
694 }
695
696 return 0;
697 }
698
rk817_playback_path_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)699 static int rk817_playback_path_get(struct snd_kcontrol *kcontrol,
700 struct snd_ctl_elem_value *ucontrol)
701 {
702 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
703 struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component);
704
705 DBG("%s : playback_path %ld\n", __func__, rk817->playback_path);
706
707 ucontrol->value.integer.value[0] = rk817->playback_path;
708
709 return 0;
710 }
711
rk817_playback_path_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)712 static int rk817_playback_path_put(struct snd_kcontrol *kcontrol,
713 struct snd_ctl_elem_value *ucontrol)
714 {
715 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
716 struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component);
717
718 if (rk817->playback_path == ucontrol->value.integer.value[0]) {
719 DBG("%s : playback_path is not changed!\n",
720 __func__);
721 return 0;
722 }
723
724 return rk817_playback_path_config(component, rk817->playback_path,
725 ucontrol->value.integer.value[0]);
726 }
727
rk817_capture_path_config(struct snd_soc_component * component,long pre_path,long target_path)728 static int rk817_capture_path_config(struct snd_soc_component *component,
729 long pre_path, long target_path)
730 {
731 struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component);
732
733 rk817->capture_path = target_path;
734
735 DBG("%s : set capture_path %ld, pre_path %ld\n", __func__,
736 rk817->capture_path, pre_path);
737
738 mutex_lock(&rk817->clk_lock);
739 if (rk817->capture_path != MIC_OFF) {
740 if (rk817->clk_capture == 0) {
741 clk_prepare_enable(rk817->mclk);
742 rk817->clk_capture++;
743 }
744 } else {
745 if (rk817->clk_capture > 0) {
746 clk_disable_unprepare(rk817->mclk);
747 rk817->clk_capture--;
748 }
749 }
750 mutex_unlock(&rk817->clk_lock);
751
752 switch (rk817->capture_path) {
753 case MIC_OFF:
754 if (pre_path != MIC_OFF) {
755 rk817_codec_power_down(component, RK817_CODEC_CAPTURE);
756 if (rk817->playback_path == OFF)
757 rk817_codec_power_down(component, RK817_CODEC_ALL);
758 }
759 break;
760 case MAIN_MIC:
761 if (pre_path == MIC_OFF)
762 rk817_codec_power_up(component, RK817_CODEC_CAPTURE);
763
764 if (rk817->adc_for_loopback) {
765 /* don't need to gain when adc use for loopback */
766 snd_soc_component_update_bits(component,
767 RK817_CODEC_AMIC_CFG0,
768 0xf,
769 0x0);
770 snd_soc_component_write(component,
771 RK817_CODEC_DMIC_PGA_GAIN,
772 0x66);
773 snd_soc_component_write(component,
774 RK817_CODEC_DADC_VOLL,
775 0x00);
776 snd_soc_component_write(component,
777 RK817_CODEC_DADC_VOLR,
778 0x00);
779 break;
780 }
781 if (!rk817->mic_in_differential) {
782 snd_soc_component_write(component,
783 RK817_CODEC_DADC_VOLR,
784 0xff);
785 snd_soc_component_update_bits(component,
786 RK817_CODEC_AADC_CFG0,
787 ADC_R_PWD_MASK,
788 ADC_R_PWD_EN);
789 snd_soc_component_update_bits(component,
790 RK817_CODEC_AMIC_CFG0,
791 PWD_PGA_R_MASK,
792 PWD_PGA_R_EN);
793 }
794 break;
795 case HANDS_FREE_MIC:
796 if (pre_path == MIC_OFF)
797 rk817_codec_power_up(component, RK817_CODEC_CAPTURE);
798
799 if (rk817->adc_for_loopback) {
800 /* don't need to gain when adc use for loopback */
801 snd_soc_component_update_bits(component,
802 RK817_CODEC_AMIC_CFG0,
803 0xf,
804 0x0);
805 snd_soc_component_write(component,
806 RK817_CODEC_DMIC_PGA_GAIN,
807 0x66);
808 snd_soc_component_write(component,
809 RK817_CODEC_DADC_VOLL,
810 0x00);
811 snd_soc_component_write(component,
812 RK817_CODEC_DADC_VOLR,
813 0x00);
814 break;
815 }
816 if (!rk817->mic_in_differential) {
817 snd_soc_component_write(component,
818 RK817_CODEC_DADC_VOLL,
819 0xff);
820 snd_soc_component_update_bits(component,
821 RK817_CODEC_AADC_CFG0,
822 ADC_L_PWD_MASK,
823 ADC_L_PWD_EN);
824 snd_soc_component_update_bits(component,
825 RK817_CODEC_AMIC_CFG0,
826 PWD_PGA_L_MASK,
827 PWD_PGA_L_EN);
828 }
829 break;
830 case BT_SCO_MIC:
831 break;
832 default:
833 return -EINVAL;
834 }
835
836 return 0;
837 }
838
rk817_capture_path_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)839 static int rk817_capture_path_get(struct snd_kcontrol *kcontrol,
840 struct snd_ctl_elem_value *ucontrol)
841 {
842 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
843 struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component);
844
845 DBG("%s : capture_path %ld\n", __func__,
846 rk817->capture_path);
847
848 ucontrol->value.integer.value[0] = rk817->capture_path;
849
850 return 0;
851 }
852
rk817_capture_path_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)853 static int rk817_capture_path_put(struct snd_kcontrol *kcontrol,
854 struct snd_ctl_elem_value *ucontrol)
855 {
856 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
857 struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component);
858
859 if (rk817->capture_path == ucontrol->value.integer.value[0]) {
860 DBG("%s : capture_path is not changed!\n",
861 __func__);
862 return 0;
863 }
864
865 return rk817_capture_path_config(component, rk817->capture_path,
866 ucontrol->value.integer.value[0]);
867 }
868
rk817_resume_path_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)869 static int rk817_resume_path_get(struct snd_kcontrol *kcontrol,
870 struct snd_ctl_elem_value *ucontrol)
871 {
872 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
873 struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component);
874
875 DBG("%s : resume_path %ld\n", __func__, rk817->resume_path);
876
877 ucontrol->value.integer.value[0] = rk817->resume_path;
878
879 return 0;
880 }
881
rk817_resume_path_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)882 static int rk817_resume_path_put(struct snd_kcontrol *kcontrol,
883 struct snd_ctl_elem_value *ucontrol)
884 {
885 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
886 struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component);
887
888 rk817->resume_path = ucontrol->value.integer.value[0];
889
890 return 0;
891 }
892
893 static struct snd_kcontrol_new rk817_snd_path_controls[] = {
894 SOC_ENUM_EXT("Playback Path", rk817_playback_path_type,
895 rk817_playback_path_get, rk817_playback_path_put),
896
897 SOC_ENUM_EXT("Capture MIC Path", rk817_capture_path_type,
898 rk817_capture_path_get, rk817_capture_path_put),
899
900 SOC_ENUM_EXT("Resume Path", rk817_resume_path_type,
901 rk817_resume_path_get, rk817_resume_path_put),
902 };
903
rk817_set_dai_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)904 static int rk817_set_dai_sysclk(struct snd_soc_dai *codec_dai,
905 int clk_id, unsigned int freq, int dir)
906 {
907 struct snd_soc_component *component = codec_dai->component;
908 struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component);
909
910 rk817->stereo_sysclk = freq;
911
912 DBG("%s : MCLK = %dHz\n", __func__, rk817->stereo_sysclk);
913
914 return 0;
915 }
916
rk817_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)917 static int rk817_set_dai_fmt(struct snd_soc_dai *codec_dai,
918 unsigned int fmt)
919 {
920 struct snd_soc_component *component = codec_dai->component;
921 unsigned int i2s_mst = 0;
922
923 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
924 case SND_SOC_DAIFMT_CBS_CFS:
925 i2s_mst |= RK817_I2S_MODE_SLV;
926 break;
927 case SND_SOC_DAIFMT_CBM_CFM:
928 i2s_mst |= RK817_I2S_MODE_MST;
929 break;
930 default:
931 dev_err(component->dev, "%s : set master mask failed!\n", __func__);
932 return -EINVAL;
933 }
934 DBG("%s : i2s %s mode\n", __func__, i2s_mst ? "master" : "slave");
935
936 snd_soc_component_update_bits(component, RK817_CODEC_DI2S_CKM,
937 RK817_I2S_MODE_MASK, i2s_mst);
938
939 return 0;
940 }
941
rk817_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)942 static int rk817_hw_params(struct snd_pcm_substream *substream,
943 struct snd_pcm_hw_params *params,
944 struct snd_soc_dai *dai)
945 {
946 struct snd_soc_component *component = dai->component;
947 struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component);
948 unsigned int rate = params_rate(params);
949 unsigned char apll_cfg3_val;
950 unsigned char dtop_digen_sr_lmt0;
951 unsigned char dtop_digen_clke;
952
953 DBG("%s : sample rate = %dHz\n", __func__, rate);
954
955 if (rk817->chip_ver <= 0x4) {
956 DBG("%s: SMIC TudorAG and previous versions\n", __func__);
957 snd_soc_component_write(component, RK817_CODEC_APLL_CFG0, 0x0c);
958 snd_soc_component_write(component, RK817_CODEC_APLL_CFG4, 0x95);
959 } else {
960 DBG("%s: SMIC TudorAG version later\n", __func__);
961 snd_soc_component_write(component, RK817_CODEC_APLL_CFG0, 0x04);
962 snd_soc_component_write(component, RK817_CODEC_APLL_CFG4, 0xa5);
963 }
964
965 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
966 dtop_digen_clke = DAC_DIG_CLK_EN;
967 else
968 dtop_digen_clke = ADC_DIG_CLK_EN;
969
970 switch (rate) {
971 case 8000:
972 apll_cfg3_val = 0x03;
973 dtop_digen_sr_lmt0 = 0x00;
974 break;
975 case 16000:
976 apll_cfg3_val = 0x06;
977 dtop_digen_sr_lmt0 = 0x01;
978 break;
979 case 96000:
980 apll_cfg3_val = 0x18;
981 dtop_digen_sr_lmt0 = 0x03;
982 break;
983 case 32000:
984 case 44100:
985 case 48000:
986 apll_cfg3_val = 0x0c;
987 dtop_digen_sr_lmt0 = 0x02;
988 break;
989 default:
990 pr_err("Unsupported rate: %d\n", rate);
991 return -EINVAL;
992 }
993
994 /**
995 * Note that: If you use the ALSA hooks plugin, entering hw_params()
996 * is before playback/capture_path_put, therefore, we need to configure
997 * APLL_CFG3/DTOP_DIGEN_CLKE/DDAC_SR_LMT0 for different sample rates.
998 */
999 if (!((substream->stream == SNDRV_PCM_STREAM_CAPTURE) && rk817->pdmdata_out_enable)) {
1000 snd_soc_component_write(component, RK817_CODEC_APLL_CFG3, apll_cfg3_val);
1001 /* The 0x00 contains ADC_DIG_CLK_DIS and DAC_DIG_CLK_DIS */
1002 snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE,
1003 dtop_digen_clke, 0x00);
1004 snd_soc_component_update_bits(component, RK817_CODEC_DDAC_SR_LMT0,
1005 DACSRT_MASK, dtop_digen_sr_lmt0);
1006 snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE,
1007 dtop_digen_clke, dtop_digen_clke);
1008 snd_soc_component_update_bits(component, RK817_CODEC_APLL_CFG5,
1009 PLL_PW_DOWN, PLL_PW_DOWN);
1010 usleep_range(50, 60);
1011 snd_soc_component_update_bits(component, RK817_CODEC_APLL_CFG5,
1012 PLL_PW_DOWN, PLL_PW_UP);
1013 usleep_range(500, 600);
1014 }
1015
1016 switch (params_format(params)) {
1017 case SNDRV_PCM_FORMAT_S16_LE:
1018 snd_soc_component_write(component, RK817_CODEC_DI2S_RXCR2,
1019 VDW_RX_16BITS);
1020 snd_soc_component_write(component, RK817_CODEC_DI2S_TXCR2,
1021 VDW_TX_16BITS);
1022 break;
1023 case SNDRV_PCM_FORMAT_S24_LE:
1024 case SNDRV_PCM_FORMAT_S32_LE:
1025 snd_soc_component_write(component, RK817_CODEC_DI2S_RXCR2,
1026 VDW_RX_24BITS);
1027 snd_soc_component_write(component, RK817_CODEC_DI2S_TXCR2,
1028 VDW_TX_24BITS);
1029 break;
1030 default:
1031 return -EINVAL;
1032 }
1033
1034 return 0;
1035 }
1036
rk817_digital_mute(struct snd_soc_dai * dai,int mute,int stream)1037 static int rk817_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
1038 {
1039 struct snd_soc_component *component = dai->component;
1040 struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component);
1041
1042 DBG("%s %d\n", __func__, mute);
1043
1044 if (mute) {
1045 rk817_codec_ctl_gpio(rk817, CODEC_SET_SPK, 0);
1046 rk817_codec_ctl_gpio(rk817, CODEC_SET_HP, 0);
1047
1048 snd_soc_component_update_bits(component,
1049 RK817_CODEC_DDAC_MUTE_MIXCTL,
1050 DACMT_ENABLE, DACMT_ENABLE);
1051 snd_soc_component_write(component, RK817_CODEC_ADAC_CFG1,
1052 PWD_DACBIAS_DOWN | PWD_DACD_DOWN |
1053 PWD_DACL_DOWN | PWD_DACR_DOWN);
1054 /* Reset DAC DTOP_DIGEN_CLKE for playback stopped */
1055 snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE,
1056 DAC_DIG_CLK_EN, DAC_DIG_CLK_DIS);
1057 snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE,
1058 DAC_DIG_CLK_EN, DAC_DIG_CLK_EN);
1059 } else {
1060 snd_soc_component_update_bits(component,
1061 RK817_CODEC_DDAC_MUTE_MIXCTL,
1062 DACMT_ENABLE, DACMT_DISABLE);
1063
1064 switch (rk817->playback_path) {
1065 case SPK_PATH:
1066 case RING_SPK:
1067 if (rk817->out_l2spk_r2hp) {
1068 snd_soc_component_write(component, RK817_CODEC_ADAC_CFG1,
1069 PWD_DACBIAS_ON | PWD_DACD_ON |
1070 PWD_DACL_ON | PWD_DACR_ON);
1071 } else if (!rk817->use_ext_amplifier) {
1072 snd_soc_component_write(component, RK817_CODEC_ADAC_CFG1,
1073 PWD_DACBIAS_ON | PWD_DACD_ON |
1074 PWD_DACL_DOWN | PWD_DACR_DOWN);
1075 } else {
1076 snd_soc_component_write(component, RK817_CODEC_ADAC_CFG1,
1077 PWD_DACBIAS_ON | PWD_DACD_DOWN |
1078 PWD_DACL_ON | PWD_DACR_ON);
1079 }
1080 rk817_codec_ctl_gpio(rk817, CODEC_SET_SPK, 1);
1081 rk817_codec_ctl_gpio(rk817, CODEC_SET_HP, 0);
1082 break;
1083 case HP_PATH:
1084 case HP_NO_MIC:
1085 case RING_HP:
1086 case RING_HP_NO_MIC:
1087 snd_soc_component_write(component, RK817_CODEC_ADAC_CFG1,
1088 PWD_DACBIAS_ON | PWD_DACD_DOWN |
1089 PWD_DACL_ON | PWD_DACR_ON);
1090 rk817_codec_ctl_gpio(rk817, CODEC_SET_SPK, 0);
1091 rk817_codec_ctl_gpio(rk817, CODEC_SET_HP, 1);
1092 break;
1093 case SPK_HP:
1094 case RING_SPK_HP:
1095 snd_soc_component_write(component, RK817_CODEC_ADAC_CFG1,
1096 PWD_DACBIAS_ON | PWD_DACD_ON |
1097 PWD_DACL_ON | PWD_DACR_ON);
1098 rk817_codec_ctl_gpio(rk817, CODEC_SET_SPK, 1);
1099 rk817_codec_ctl_gpio(rk817, CODEC_SET_HP, 1);
1100 break;
1101 default:
1102 break;
1103 }
1104 }
1105
1106 return 0;
1107 }
1108
1109 #define RK817_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1110 SNDRV_PCM_RATE_16000 | \
1111 SNDRV_PCM_RATE_32000 | \
1112 SNDRV_PCM_RATE_44100 | \
1113 SNDRV_PCM_RATE_48000 | \
1114 SNDRV_PCM_RATE_96000)
1115
1116 #define RK817_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1117 SNDRV_PCM_RATE_16000 | \
1118 SNDRV_PCM_RATE_32000 | \
1119 SNDRV_PCM_RATE_44100 | \
1120 SNDRV_PCM_RATE_48000 | \
1121 SNDRV_PCM_RATE_96000)
1122
1123 #define RK817_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1124 SNDRV_PCM_FMTBIT_S20_3LE |\
1125 SNDRV_PCM_FMTBIT_S24_LE |\
1126 SNDRV_PCM_FMTBIT_S32_LE)
1127
rk817_codec_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1128 static void rk817_codec_shutdown(struct snd_pcm_substream *substream,
1129 struct snd_soc_dai *dai)
1130 {
1131 struct snd_soc_component *component = dai->component;
1132
1133 /**
1134 * Note: The following configurations will take effect when i2s bclk
1135 * is working, and we just need to handle the part of ADC that is
1136 * output to SoC.
1137 */
1138 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
1139 snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE,
1140 I2STX_CKE_EN, I2STX_CKE_EN);
1141 usleep_range(1000, 1100);
1142 snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE,
1143 I2STX_CKE_EN, I2STX_CKE_DIS);
1144 }
1145 }
1146
1147 static struct snd_soc_dai_ops rk817_dai_ops = {
1148 .hw_params = rk817_hw_params,
1149 .set_fmt = rk817_set_dai_fmt,
1150 .set_sysclk = rk817_set_dai_sysclk,
1151 .mute_stream = rk817_digital_mute,
1152 .shutdown = rk817_codec_shutdown,
1153 .no_capture_mute = 1,
1154 };
1155
1156 static struct snd_soc_dai_driver rk817_dai[] = {
1157 {
1158 .name = "rk817-hifi",
1159 .id = RK817_HIFI,
1160 .playback = {
1161 .stream_name = "HiFi Playback",
1162 .channels_min = 2,
1163 .channels_max = 8,
1164 .rates = RK817_PLAYBACK_RATES,
1165 .formats = RK817_FORMATS,
1166 },
1167 .capture = {
1168 .stream_name = "HiFi Capture",
1169 .channels_min = 2,
1170 .channels_max = 8,
1171 .rates = RK817_CAPTURE_RATES,
1172 .formats = RK817_FORMATS,
1173 },
1174 .ops = &rk817_dai_ops,
1175 },
1176 {
1177 .name = "rk817-voice",
1178 .id = RK817_VOICE,
1179 .playback = {
1180 .stream_name = "Voice Playback",
1181 .channels_min = 1,
1182 .channels_max = 2,
1183 .rates = RK817_PLAYBACK_RATES,
1184 .formats = RK817_FORMATS,
1185 },
1186 .capture = {
1187 .stream_name = "Voice Capture",
1188 .channels_min = 2,
1189 .channels_max = 8,
1190 .rates = RK817_CAPTURE_RATES,
1191 .formats = RK817_FORMATS,
1192 },
1193 .ops = &rk817_dai_ops,
1194 },
1195
1196 };
1197
rk817_suspend(struct snd_soc_component * component)1198 static int rk817_suspend(struct snd_soc_component *component)
1199 {
1200 rk817_codec_power_down(component, RK817_CODEC_ALL);
1201 return 0;
1202 }
1203
rk817_resume(struct snd_soc_component * component)1204 static int rk817_resume(struct snd_soc_component *component)
1205 {
1206 struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component);
1207
1208 if (rk817->resume_path) {
1209 if (rk817->capture_path != MIC_OFF)
1210 rk817_capture_path_config(component, OFF, rk817->capture_path);
1211 if (rk817->playback_path != OFF)
1212 rk817_playback_path_config(component, OFF, rk817->playback_path);
1213 }
1214
1215 return 0;
1216 }
1217
rk817_probe(struct snd_soc_component * component)1218 static int rk817_probe(struct snd_soc_component *component)
1219 {
1220 struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component);
1221 int chip_name = 0;
1222 int chip_ver = 0;
1223
1224 DBG("%s\n", __func__);
1225
1226 if (!rk817) {
1227 dev_err(component->dev, "%s : rk817 priv is NULL!\n",
1228 __func__);
1229 return -EINVAL;
1230 }
1231 snd_soc_component_init_regmap(component, rk817->regmap);
1232 rk817->component = component;
1233 rk817->playback_path = OFF;
1234 rk817->capture_path = MIC_OFF;
1235
1236 chip_name = snd_soc_component_read(component, RK817_PMIC_CHIP_NAME);
1237 chip_ver = snd_soc_component_read(component, RK817_PMIC_CHIP_VER);
1238 rk817->chip_ver = (chip_ver & 0x0f);
1239 dev_info(component->dev, "%s: chip_name:0x%x, chip_ver:0x%x\n", __func__, chip_name, chip_ver);
1240
1241 clk_prepare_enable(rk817->mclk);
1242 rk817_reset(component);
1243 clk_disable_unprepare(rk817->mclk);
1244 mutex_init(&rk817->clk_lock);
1245 rk817->clk_capture = 0;
1246 rk817->clk_playback = 0;
1247
1248 snd_soc_add_component_controls(component, rk817_snd_path_controls,
1249 ARRAY_SIZE(rk817_snd_path_controls));
1250 return 0;
1251 }
1252
1253 /* power down chip */
rk817_remove(struct snd_soc_component * component)1254 static void rk817_remove(struct snd_soc_component *component)
1255 {
1256 struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component);
1257
1258 DBG("%s\n", __func__);
1259
1260 if (!rk817) {
1261 dev_err(component->dev, "%s : rk817 is NULL\n", __func__);
1262 return;
1263 }
1264
1265 rk817_codec_power_down(component, RK817_CODEC_ALL);
1266 snd_soc_component_exit_regmap(component);
1267 mutex_destroy(&rk817->clk_lock);
1268 mdelay(10);
1269
1270 }
1271
1272 static const struct snd_soc_component_driver soc_codec_dev_rk817 = {
1273 .probe = rk817_probe,
1274 .remove = rk817_remove,
1275 .suspend = rk817_suspend,
1276 .resume = rk817_resume,
1277 .idle_bias_on = 1,
1278 .use_pmdown_time = 1,
1279 .endianness = 1,
1280 .non_legacy_dai_naming = 1
1281 };
1282
rk817_codec_parse_dt_property(struct device * dev,struct rk817_codec_priv * rk817)1283 static int rk817_codec_parse_dt_property(struct device *dev,
1284 struct rk817_codec_priv *rk817)
1285 {
1286 struct device_node *node = dev->parent->of_node;
1287 int ret;
1288
1289 DBG("%s()\n", __func__);
1290
1291 if (!node) {
1292 dev_err(dev, "%s() dev->parent->of_node is NULL\n",
1293 __func__);
1294 return -ENODEV;
1295 }
1296
1297 node = of_get_child_by_name(dev->parent->of_node, "codec");
1298 if (!node) {
1299 dev_err(dev, "%s() Can not get child: codec\n",
1300 __func__);
1301 return -ENODEV;
1302 }
1303
1304 rk817->hp_ctl_gpio = devm_gpiod_get_optional(dev, "hp-ctl",
1305 GPIOD_OUT_LOW);
1306 if (!IS_ERR_OR_NULL(rk817->hp_ctl_gpio)) {
1307 DBG("%s : hp-ctl-gpio %d\n", __func__,
1308 desc_to_gpio(rk817->hp_ctl_gpio));
1309 }
1310
1311 rk817->spk_ctl_gpio = devm_gpiod_get_optional(dev, "spk-ctl",
1312 GPIOD_OUT_LOW);
1313 if (!IS_ERR_OR_NULL(rk817->spk_ctl_gpio)) {
1314 DBG("%s : spk-ctl-gpio %d\n", __func__,
1315 desc_to_gpio(rk817->spk_ctl_gpio));
1316 }
1317
1318 ret = of_property_read_u32(node, "spk-mute-delay-ms",
1319 &rk817->spk_mute_delay);
1320 if (ret < 0) {
1321 DBG("%s() Can not read property spk-mute-delay-ms\n",
1322 __func__);
1323 rk817->spk_mute_delay = 0;
1324 }
1325
1326 ret = of_property_read_u32(node, "hp-mute-delay-ms",
1327 &rk817->hp_mute_delay);
1328 if (ret < 0) {
1329 DBG("%s() Can not read property hp-mute-delay-ms\n",
1330 __func__);
1331 rk817->hp_mute_delay = 0;
1332 }
1333 DBG("spk mute delay %dms --- hp mute delay %dms\n",
1334 rk817->spk_mute_delay, rk817->hp_mute_delay);
1335
1336 ret = of_property_read_u32(node, "spk-volume", &rk817->spk_volume);
1337 if (ret < 0) {
1338 DBG("%s() Can not read property spk-volume\n", __func__);
1339 rk817->spk_volume = OUT_VOLUME;
1340 }
1341 if (rk817->spk_volume < 3)
1342 rk817->spk_volume = 3;
1343
1344 ret = of_property_read_u32(node, "hp-volume",
1345 &rk817->hp_volume);
1346 if (ret < 0) {
1347 DBG("%s() Can not read property hp-volume\n",
1348 __func__);
1349 rk817->hp_volume = OUT_VOLUME;
1350 }
1351 if (rk817->hp_volume < 3)
1352 rk817->hp_volume = 3;
1353
1354 ret = of_property_read_u32(node, "capture-volume",
1355 &rk817->capture_volume);
1356 if (ret < 0) {
1357 DBG("%s() Can not read property capture-volume\n",
1358 __func__);
1359 rk817->capture_volume = CAPTURE_VOLUME;
1360 }
1361
1362 rk817->mic_in_differential =
1363 of_property_read_bool(node, "mic-in-differential");
1364
1365 rk817->pdmdata_out_enable =
1366 of_property_read_bool(node, "pdmdata-out-enable");
1367
1368 rk817->use_ext_amplifier =
1369 of_property_read_bool(node, "use-ext-amplifier");
1370
1371 rk817->out_l2spk_r2hp = of_property_read_bool(node, "out-l2spk-r2hp");
1372
1373 rk817->adc_for_loopback =
1374 of_property_read_bool(node, "adc-for-loopback");
1375
1376 return 0;
1377 }
1378
1379 static const struct regmap_config rk817_codec_regmap_config = {
1380 .name = "rk817-codec",
1381 .reg_bits = 8,
1382 .val_bits = 8,
1383 .reg_stride = 1,
1384 .max_register = 0xfe,
1385 .cache_type = REGCACHE_FLAT,
1386 .volatile_reg = rk817_volatile_register,
1387 .writeable_reg = rk817_codec_register,
1388 .readable_reg = rk817_codec_register,
1389 .reg_defaults = rk817_reg_defaults,
1390 .num_reg_defaults = ARRAY_SIZE(rk817_reg_defaults),
1391 };
1392
rk817_platform_probe(struct platform_device * pdev)1393 static int rk817_platform_probe(struct platform_device *pdev)
1394 {
1395 struct rk808 *rk817 = dev_get_drvdata(pdev->dev.parent);
1396 struct rk817_codec_priv *rk817_codec_data;
1397 int ret;
1398
1399 DBG("%s\n", __func__);
1400
1401 if (!rk817) {
1402 dev_err(&pdev->dev, "%s : rk817 is NULL\n", __func__);
1403 return -EINVAL;
1404 }
1405
1406 rk817_codec_data = devm_kzalloc(&pdev->dev,
1407 sizeof(struct rk817_codec_priv),
1408 GFP_KERNEL);
1409 if (!rk817_codec_data)
1410 return -ENOMEM;
1411
1412 platform_set_drvdata(pdev, rk817_codec_data);
1413
1414 ret = rk817_codec_parse_dt_property(&pdev->dev, rk817_codec_data);
1415 if (ret < 0) {
1416 dev_err(&pdev->dev, "%s() parse device tree property error %d\n",
1417 __func__, ret);
1418 goto err_;
1419 }
1420
1421 rk817_codec_data->regmap = devm_regmap_init_i2c(rk817->i2c,
1422 &rk817_codec_regmap_config);
1423 if (IS_ERR(rk817_codec_data->regmap)) {
1424 ret = PTR_ERR(rk817_codec_data->regmap);
1425 dev_err(&pdev->dev, "failed to allocate register map: %d\n",
1426 ret);
1427 goto err_;
1428 }
1429
1430 rk817_codec_data->mclk = devm_clk_get(&pdev->dev, "mclk");
1431 if (IS_ERR(rk817_codec_data->mclk)) {
1432 dev_err(&pdev->dev, "Unable to get mclk\n");
1433 ret = -ENXIO;
1434 goto err_;
1435 }
1436
1437 ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_dev_rk817,
1438 rk817_dai, ARRAY_SIZE(rk817_dai));
1439 if (ret < 0) {
1440 dev_err(&pdev->dev, "%s() register codec error %d\n",
1441 __func__, ret);
1442 goto err_;
1443 }
1444
1445 return 0;
1446 err_:
1447
1448 return ret;
1449 }
1450
rk817_platform_remove(struct platform_device * pdev)1451 static int rk817_platform_remove(struct platform_device *pdev)
1452 {
1453 snd_soc_unregister_component(&pdev->dev);
1454
1455 return 0;
1456 }
1457
rk817_platform_shutdown(struct platform_device * pdev)1458 static void rk817_platform_shutdown(struct platform_device *pdev)
1459 {
1460 struct rk817_codec_priv *rk817 = dev_get_drvdata(&pdev->dev);
1461
1462 DBG("%s\n", __func__);
1463
1464 if (rk817 && rk817->component)
1465 rk817_codec_power_down(rk817->component, RK817_CODEC_ALL);
1466 }
1467
1468 static const struct of_device_id rk817_codec_dt_ids[] = {
1469 { .compatible = "rockchip,rk817-codec" },
1470 {},
1471 };
1472 MODULE_DEVICE_TABLE(of, rk817_codec_dt_ids);
1473
1474 static struct platform_driver rk817_codec_driver = {
1475 .driver = {
1476 .name = "rk817-codec",
1477 .of_match_table = rk817_codec_dt_ids,
1478 },
1479 .probe = rk817_platform_probe,
1480 .remove = rk817_platform_remove,
1481 .shutdown = rk817_platform_shutdown,
1482 };
1483
1484 module_platform_driver(rk817_codec_driver);
1485
1486 MODULE_DESCRIPTION("ASoC RK817 codec driver");
1487 MODULE_AUTHOR("binyuan <kevan.lan@rock-chips.com>");
1488 MODULE_LICENSE("GPL v2");
1489