1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * rk730.h -- RK730 ALSA SoC Audio driver 4 * 5 * Copyright (C) 2022 Rockchip Electronics Co.,Ltd 6 */ 7 8 #ifndef _RK730_H 9 #define _RK730_H 10 11 /* RK730 Analog Registers Definition */ 12 #define RK730_HK_TOP_0 0x00 13 #define RK730_HK_TOP_1 0x01 14 #define RK730_HK_TOP_2 0x02 15 #define RK730_HK_TRIM_0 0x03 16 #define RK730_HK_TRIM_1 0x04 17 #define RK730_ADC_0 0x05 18 #define RK730_ADC_1 0x06 19 #define RK730_ADC_2 0x07 20 #define RK730_DAC_0 0x08 21 #define RK730_DAC_1 0x09 22 #define RK730_DAC_2 0x0a 23 #define RK730_MIC_BOOST_0 0x0b 24 #define RK730_MIC_BOOST_1 0x0c 25 #define RK730_MIC_BOOST_2 0x0d 26 #define RK730_MIC_BOOST_3 0x0e 27 #define RK730_ADC_PGA_BLOCK_0 0x0f 28 #define RK730_ADC_PGA_BLOCK_1 0x10 29 #define RK730_SYSPLL_0 0x11 30 #define RK730_SYSPLL_1 0x12 31 #define RK730_SYSPLL_2 0x13 32 #define RK730_SYSPLL_3 0x14 33 #define RK730_SYSPLL_LOOP_0 0x15 34 #define RK730_SYSPLL_LOOP_1 0x16 35 #define RK730_SYSPLL_LOOP_2 0x17 36 #define RK730_SYSPLL_LOOP_3 0x18 37 #define RK730_SYSPLL_RVCO_0 0x19 38 #define RK730_SYSPLL_RVCO_1 0x1a 39 #define RK730_SYSPLL_RVCO_2 0x1b 40 #define RK730_SYSPLL_RVCO_3 0x1c 41 #define RK730_SYSPLL_FRACT_0 0x1d 42 #define RK730_SYSPLL_FRACT_1 0x1e 43 #define RK730_SYSPLL_FRACT_2 0x1f 44 #define RK730_LDO 0x20 45 #define RK730_MIC_BIAS 0x21 46 #define RK730_MUXER_0 0x22 47 #define RK730_MUXER_1 0x23 48 #define RK730_MIXER_0 0x24 49 #define RK730_MIXER_1 0x25 50 #define RK730_MIXER_2 0x26 51 #define RK730_CHARGE_PUMP 0x27 52 #define RK730_HP_0 0x28 53 #define RK730_HP_1 0x29 54 #define RK730_LINEOUT_0 0x2a 55 #define RK730_LINEOUT_1 0x2b 56 57 /* RK730 Digital Registers Definition */ 58 #define RK730_DTOP_VUCTL 0x40 59 #define RK730_DTOP_VUCTIME 0x41 60 #define RK730_DTOP_LPT_SRST 0x42 61 #define RK730_DTOP_DIGEN_CLKE 0x43 62 #define RK730_DADC_VOLL 0x44 63 #define RK730_DADC_VOLR 0x45 64 #define RK730_DADC_SR_ACL 0x46 65 #define RK730_DADC_PR_0 0x47 66 #define RK730_DADC_PR_1 0x48 67 #define RK730_DADC_PR_2 0x49 68 #define RK730_DADC_PR_3 0x4a 69 #define RK730_DADC_NG_0 0x4b 70 #define RK730_DADC_NG_1 0x4c 71 #define RK730_DADC_NG_2 0x4d 72 #define RK730_DADC_NG_3 0x4e 73 #define RK730_DADC_CICCOMP 0x4f 74 #define RK730_DADC_HPF 0x50 75 #define RK730_DADC_RVOLL 0x51 76 #define RK730_DADC_RVOLR 0x52 77 #define RK730_DMIC_LMT_1 0x53 78 #define RK730_DMIC_LMT_2 0x54 79 #define RK730_DMIC_NG_1 0x55 80 #define RK730_DMIC_NG_2 0x56 81 #define RK730_DDAC_POPD_DACST 0x57 82 #define RK730_DDAC_VOLL 0x58 83 #define RK730_DDAC_VOLR 0x59 84 #define RK730_DDAC_SR_LMT 0x5a 85 #define RK730_DDAC_PR_0 0x5b 86 #define RK730_DDAC_PR_1 0x5c 87 #define RK730_DDAC_PR_2 0x5d 88 #define RK730_DDAC_PR_3 0x5e 89 #define RK730_DDAC_NG_0 0x5f 90 #define RK730_DDAC_NG_1 0x60 91 #define RK730_DDAC_NG_2 0x61 92 #define RK730_DDAC_NG_3 0x62 93 #define RK730_DDAC_MUTE_MIXCTL 0x63 94 #define RK730_DDAC_RVOLL 0x64 95 #define RK730_DDAC_RVOLR 0x65 96 #define RK730_DI2S_CKM 0x66 97 #define RK730_DI2S_RSD 0x67 98 #define RK730_DI2S_RXCR_1 0x68 99 #define RK730_DI2S_RXCR_2 0x69 100 #define RK730_DI2S_RXCMD_TSD 0x6a 101 #define RK730_DI2S_TXCR_1 0x6b 102 #define RK730_DI2S_TXCR_2 0x6c 103 #define RK730_DI2S_TXCR_3_TXCMD 0x6d 104 #define RK730_DAC_ATTN 0x6e 105 106 /* RK730_HK_TOP_1 */ 107 #define RK730_HK_TOP_1_DAC_REF_BUF_CHOP_MASK GENMASK(7, 6) 108 #define RK730_HK_TOP_1_DAC_REF_BUF_CHOP(x) ((x) << 6) 109 #define RK730_HK_TOP_1_IBIAS_STD_SEL_MASK GENMASK(5, 4) 110 #define RK730_HK_TOP_1_IBIAS_STD_SEL_27_5UA (3 << 4) 111 #define RK730_HK_TOP_1_IBIAS_STD_SEL_23_5UA (2 << 4) 112 #define RK730_HK_TOP_1_IBIAS_STD_SEL_20UA (1 << 4) 113 #define RK730_HK_TOP_1_IBIAS_STD_SEL_16_5UA (0 << 4) 114 #define RK730_HK_TOP_1_IBIAS_GAIN_SEL_MASK GENMASK(3, 0) 115 #define RK730_HK_TOP_1_IBIAS_GAIN_SEL_200 8 116 #define RK730_HK_TOP_1_IBIAS_GAIN_SEL_143 9 117 #define RK730_HK_TOP_1_IBIAS_GAIN_SEL_120 10 118 #define RK730_HK_TOP_1_IBIAS_GAIN_SEL_100 0 119 #define RK730_HK_TOP_1_IBIAS_GAIN_SEL_71_5 1 120 #define RK730_HK_TOP_1_IBIAS_GAIN_SEL_62_5 2 121 #define RK730_HK_TOP_1_IBIAS_GAIN_SEL_50 3 122 #define RK730_HK_TOP_1_IBIAS_GAIN_SEL_38_2 6 123 #define RK730_HK_TOP_1_IBIAS_GAIN_SEL_32 7 124 125 /* RK730_ADC_0 */ 126 #define RK730_ADC_0_DEM_EN_MASK BIT(3) 127 #define RK730_ADC_0_DEM_EN BIT(3) 128 #define RK730_ADC_0_DEM_DIS 0 129 130 /* RK730_MIC_BOOST_3 */ 131 #define RK730_MIC_BOOST_3_MIC_CHOP_MASK GENMASK(7, 6) 132 #define RK730_MIC_BOOST_3_MIC_CHOP(x) ((x) << 6) 133 134 /* RK730_ADC_PGA_BLOCK_1 */ 135 #define RK730_ADC_PGA_BLOCK_1_PGA_CHOP_MASK GENMASK(7, 6) 136 #define RK730_ADC_PGA_BLOCK_1_PGA_CHOP(x) ((x) << 6) 137 138 /* RK730_MIC_BIAS */ 139 #define RK730_MIC_BIAS_VOLT_MASK GENMASK(3, 2) 140 #define RK730_MIC_BIAS_VOLT_2_8V (3 << 2) 141 #define RK730_MIC_BIAS_VOLT_2_5V (2 << 2) 142 #define RK730_MIC_BIAS_VOLT_2_2V (1 << 2) 143 #define RK730_MIC_BIAS_VOLT_2_0V (0 << 2) 144 145 /* RK730_MUXER_1 */ 146 #define RK730_MUXER_1_MUX_OUT_CHOP_MASK GENMASK(1, 0) 147 #define RK730_MUXER_1_MUX_OUT_CHOP(x) ((x) << 0) 148 149 /* RK730_MIXER_2 */ 150 #define RK730_MIXER_2_MIX_CHOP_MASK GENMASK(7, 6) 151 #define RK730_MIXER_2_MIX_CHOP(x) ((x) << 6) 152 #define RK730_MIXER_2_MIX_R_MODE_MASK GENMASK(5, 4) 153 #define RK730_MIXER_2_MIX_R_MODE(x) ((x) << 4) 154 #define RK730_MIXER_2_MIX_L_MODE_MASK GENMASK(2, 1) 155 #define RK730_MIXER_2_MIX_L_MODE(x) ((x) << 1) 156 157 /* RK730_HP_1 */ 158 #define RK730_HP_1_HP_LO_CHOP_MASK GENMASK(6, 5) 159 #define RK730_HP_1_HP_LO_CHOP(x) ((x) << 5) 160 161 /* RK730_DTOP_DIGEN_CLKE */ 162 #define RK730_DTOP_DIGEN_CLKE_ADC_CKE_MASK BIT(7) 163 #define RK730_DTOP_DIGEN_CLKE_ADC_CKE_EN BIT(7) 164 #define RK730_DTOP_DIGEN_CLKE_ADC_CKE_DIS 0 165 #define RK730_DTOP_DIGEN_CLKE_I2STX_CKE_MASK BIT(6) 166 #define RK730_DTOP_DIGEN_CLKE_I2STX_CKE_EN BIT(6) 167 #define RK730_DTOP_DIGEN_CLKE_I2STX_CKE_DIS 0 168 #define RK730_DTOP_DIGEN_CLKE_ADC_EN_MASK BIT(5) 169 #define RK730_DTOP_DIGEN_CLKE_ADC_EN BIT(5) 170 #define RK730_DTOP_DIGEN_CLKE_ADC_DIS 0 171 #define RK730_DTOP_DIGEN_CLKE_I2STX_EN_MASK BIT(4) 172 #define RK730_DTOP_DIGEN_CLKE_I2STX_EN BIT(4) 173 #define RK730_DTOP_DIGEN_CLKE_I2STX_DIS 0 174 #define RK730_DTOP_DIGEN_CLKE_DAC_CKE_MASK BIT(3) 175 #define RK730_DTOP_DIGEN_CLKE_DAC_CKE_EN BIT(3) 176 #define RK730_DTOP_DIGEN_CLKE_DAC_CKE_DIS 0 177 #define RK730_DTOP_DIGEN_CLKE_I2SRX_CKE_MASK BIT(2) 178 #define RK730_DTOP_DIGEN_CLKE_I2SRX_CKE_EN BIT(2) 179 #define RK730_DTOP_DIGEN_CLKE_I2SRX_CKE_DIS 0 180 #define RK730_DTOP_DIGEN_CLKE_DAC_EN_MASK BIT(1) 181 #define RK730_DTOP_DIGEN_CLKE_DAC_EN BIT(1) 182 #define RK730_DTOP_DIGEN_CLKE_DAC_DIS 0 183 #define RK730_DTOP_DIGEN_CLKE_I2SRX_EN_MASK BIT(0) 184 #define RK730_DTOP_DIGEN_CLKE_I2SRX_EN BIT(0) 185 #define RK730_DTOP_DIGEN_CLKE_I2SRX_DIS 0 186 187 /* RK730_DADC_SR_ACL */ 188 #define RK730_DADC_SR_ACL_VOLL_POL_MASK BIT(5) 189 #define RK730_DADC_SR_ACL_VOLL_POS BIT(5) 190 #define RK730_DADC_SR_ACL_VOLL_NEG 0 191 #define RK730_DADC_SR_ACL_VOLR_POL_MASK BIT(4) 192 #define RK730_DADC_SR_ACL_VOLR_POS BIT(4) 193 #define RK730_DADC_SR_ACL_VOLR_NEG 0 194 #define RK730_DADC_SR_ACL_SRT_MASK GENMASK(2, 0) 195 #define RK730_DADC_SR_ACL_SRT(x) (x) 196 197 /* RK730_DDAC_SR_LMT */ 198 #define RK730_DDAC_SR_LMT_VOLL_POL_MASK BIT(5) 199 #define RK730_DDAC_SR_LMT_VOLL_POS BIT(5) 200 #define RK730_DDAC_SR_LMT_VOLL_NEG 0 201 #define RK730_DDAC_SR_LMT_VOLR_POL_MASK BIT(4) 202 #define RK730_DDAC_SR_LMT_VOLR_POS BIT(4) 203 #define RK730_DDAC_SR_LMT_VOLR_NEG 0 204 #define RK730_DDAC_SR_LMT_SRT_MASK GENMASK(2, 0) 205 #define RK730_DDAC_SR_LMT_SRT(x) (x) 206 207 /* RK730_DDAC_MUTE_MIXCTL */ 208 #define RK730_DDAC_MUTE_MIXCTL_MUTE_MASK BIT(0) 209 #define RK730_DDAC_MUTE_MIXCTL_MUTE BIT(0) 210 #define RK730_DDAC_MUTE_MIXCTL_UNMUTE 0 211 212 /* RK730_DI2S_CKM */ 213 #define RK730_DI2S_CKM_SCLK_DIV_MASK GENMASK(7, 4) 214 #define RK730_DI2S_CKM_SCLK_DIV(x) ((x - 1) << 4) 215 #define RK730_DI2S_CKM_SCLK_EN_MASK BIT(2) 216 #define RK730_DI2S_CKM_SCLK_EN BIT(2) 217 #define RK730_DI2S_CKM_SCLK_DIS 0 218 #define RK730_DI2S_CKM_SCLK_POL_MASK BIT(1) 219 #define RK730_DI2S_CKM_SCLK_INVERTED BIT(1) 220 #define RK730_DI2S_CKM_SCLK_NORMAL 0 221 #define RK730_DI2S_CKM_MST_MASK BIT(0) 222 #define RK730_DI2S_CKM_MST_MASTER BIT(0) 223 #define RK730_DI2S_CKM_MST_SLAVE 0 224 225 /* RK730_DI2S_XCR2 */ 226 #define RK730_DI2S_XCR2_VDW_MASK GENMASK(4, 0) 227 #define RK730_DI2S_XCR2_VDW(x) (x - 1) 228 229 /* RK730_DI2S_RXCMD_TSD */ 230 #define RK730_DI2S_RXCMD_TSD_RXS_MASK BIT(5) 231 #define RK730_DI2S_RXCMD_TSD_RXS_EN BIT(5) 232 #define RK730_DI2S_RXCMD_TSD_RXS_DIS 0 233 234 /* RK730_DI2S_TXCR_3_TXCMD */ 235 #define RK730_DI2S_TXCR_3_TXCMD_TXS_MASK BIT(7) 236 #define RK730_DI2S_TXCR_3_TXCMD_TXS_EN BIT(7) 237 #define RK730_DI2S_TXCR_3_TXCMD_TXS_DIS 0 238 239 #endif 240