1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * rk3528_codec.c - Rockchip RK3528 SoC Codec Driver
4 *
5 * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
6 */
7
8 #include <linux/clk.h>
9 #include <linux/device.h>
10 #include <linux/delay.h>
11 #include <linux/module.h>
12 #include <linux/of_gpio.h>
13 #include <linux/of_platform.h>
14 #include <linux/platform_device.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/regmap.h>
17 #include <linux/reset.h>
18 #include <sound/pcm_params.h>
19 #include <sound/soc.h>
20 #include <sound/tlv.h>
21
22 #include "rk3528_codec.h"
23
24 #define CODEC_DRV_NAME "rk3528-acodec"
25
26 struct rk3528_codec_priv {
27 const struct device *plat_dev;
28 struct reset_control *reset;
29 struct regmap *regmap;
30 struct clk *pclk;
31 struct clk *mclk;
32 struct gpio_desc *pa_ctl_gpio;
33 struct snd_soc_component *component;
34 u32 pa_ctl_delay_ms;
35 };
36
rk3528_codec_pa_ctrl(struct rk3528_codec_priv * rk3528,bool on)37 static void rk3528_codec_pa_ctrl(struct rk3528_codec_priv *rk3528, bool on)
38 {
39 if (!rk3528->pa_ctl_gpio)
40 return;
41
42 if (on) {
43 gpiod_direction_output(rk3528->pa_ctl_gpio, on);
44 msleep(rk3528->pa_ctl_delay_ms);
45 } else {
46 gpiod_direction_output(rk3528->pa_ctl_gpio, on);
47 }
48 }
49
rk3528_codec_reset(struct snd_soc_component * component)50 static int rk3528_codec_reset(struct snd_soc_component *component)
51 {
52 struct rk3528_codec_priv *rk3528 = snd_soc_component_get_drvdata(component);
53
54 reset_control_assert(rk3528->reset);
55 usleep_range(10000, 11000); /* estimated value */
56 reset_control_deassert(rk3528->reset);
57
58 regmap_update_bits(rk3528->regmap, ACODEC_DIG00,
59 ACODEC_DAC_RST_MASK |
60 ACODEC_SYS_RST_MASK,
61 ACODEC_DAC_RST_N |
62 ACODEC_SYS_RST_N);
63 regmap_update_bits(rk3528->regmap, ACODEC_DIG02,
64 ACODEC_DAC_I2S_RST_MASK,
65 ACODEC_DAC_I2S_RST_N);
66 usleep_range(10000, 11000); /* estimated value */
67 regmap_update_bits(rk3528->regmap, ACODEC_DIG00,
68 ACODEC_DAC_RST_MASK |
69 ACODEC_SYS_RST_MASK,
70 ACODEC_DAC_RST_P |
71 ACODEC_SYS_RST_P);
72 regmap_update_bits(rk3528->regmap, ACODEC_DIG02,
73 ACODEC_DAC_I2S_RST_MASK,
74 ACODEC_DAC_I2S_RST_P);
75
76 return 0;
77 }
78
rk3528_codec_power_on(struct rk3528_codec_priv * rk3528)79 static int rk3528_codec_power_on(struct rk3528_codec_priv *rk3528)
80 {
81 /* vendor step 0, Supply the power of the digital part and reset the audio codec. */
82 /* vendor step 1 */
83 regmap_update_bits(rk3528->regmap, ACODEC_ANA08,
84 ACODEC_DAC_L_POP_CTRL_MASK,
85 ACODEC_DAC_L_POP_CTRL_ON);
86 regmap_update_bits(rk3528->regmap, ACODEC_ANA0C,
87 ACODEC_DAC_R_POP_CTRL_MASK,
88 ACODEC_DAC_R_POP_CTRL_ON);
89 /* vendor step 2 */
90 regmap_update_bits(rk3528->regmap, ACODEC_ANA01,
91 ACODEC_VREF_SEL_MASK, ACODEC_VREF_SEL(0xff));
92 /* vendor step 3, supply the power of the analog part */
93 /* vendor step 4 */
94 regmap_update_bits(rk3528->regmap, ACODEC_ANA00,
95 ACODEC_VREF_MASK, ACODEC_VREF_EN);
96
97 /* vendor step 5, Wait until the voltage of VCM keeps stable at the AVDD/2. */
98 usleep_range(20000, 22000);
99 /* vendor step 6 */
100 regmap_update_bits(rk3528->regmap, ACODEC_ANA01,
101 ACODEC_VREF_SEL_MASK, ACODEC_VREF_SEL(2));
102 return 0;
103 }
104
rk3528_codec_power_off(struct rk3528_codec_priv * rk3528)105 static int rk3528_codec_power_off(struct rk3528_codec_priv *rk3528)
106 {
107 /*
108 * vendor step 0. Keep the power on and disable the DAC and ADC path.
109 */
110 /* vendor step 1 */
111 regmap_update_bits(rk3528->regmap, ACODEC_ANA01,
112 ACODEC_VREF_SEL_MASK, ACODEC_VREF_SEL(0xff));
113 /* vendor step 2 */
114 /* vendor step 3 */
115 regmap_update_bits(rk3528->regmap, ACODEC_ANA00,
116 ACODEC_VREF_MASK, ACODEC_VREF_DIS);
117 /* vendor step 4. Wait until the voltage of VCM keep stable at AGND. */
118 usleep_range(20000, 22000);
119 /* vendor step 5, power off the analog power supply */
120 /* vendor step 6, power off the digital power supply */
121
122 return 0;
123 }
124
rk3528_codec_dac_enable(struct rk3528_codec_priv * rk3528)125 static int rk3528_codec_dac_enable(struct rk3528_codec_priv *rk3528)
126 {
127 /* vendor step 0, power up the codec and input the mute signal */
128 /* vendor step 1 */
129 regmap_update_bits(rk3528->regmap, ACODEC_ANA00,
130 ACODEC_IBIAS_DAC_MASK,
131 ACODEC_IBIAS_DAC_EN);
132 /* vendor step 2 */
133 regmap_update_bits(rk3528->regmap, ACODEC_ANA08,
134 ACODEC_DAC_L_BUF_MASK,
135 ACODEC_DAC_L_BUF_EN);
136 regmap_update_bits(rk3528->regmap, ACODEC_ANA0C,
137 ACODEC_DAC_R_BUF_MASK,
138 ACODEC_DAC_R_BUF_EN);
139 /* vendor step 3 */
140 regmap_update_bits(rk3528->regmap, ACODEC_ANA08,
141 ACODEC_DAC_L_POP_CTRL_MASK,
142 ACODEC_DAC_L_POP_CTRL_ON);
143 regmap_update_bits(rk3528->regmap, ACODEC_ANA0C,
144 ACODEC_DAC_R_POP_CTRL_MASK,
145 ACODEC_DAC_R_POP_CTRL_ON);
146 /* vendor step 4 */
147 regmap_update_bits(rk3528->regmap, ACODEC_ANA09,
148 ACODEC_LINEOUT_L_MASK,
149 ACODEC_LINEOUT_L_EN);
150 regmap_update_bits(rk3528->regmap, ACODEC_ANA0D,
151 ACODEC_LINEOUT_R_MASK,
152 ACODEC_LINEOUT_R_EN);
153 /* vendor step 5 */
154 regmap_update_bits(rk3528->regmap, ACODEC_ANA09,
155 ACODEC_LINEOUT_L_INIT_MASK,
156 ACODEC_LINEOUT_L_INIT_WORK);
157 regmap_update_bits(rk3528->regmap, ACODEC_ANA0D,
158 ACODEC_LINEOUT_R_INIT_MASK,
159 ACODEC_LINEOUT_R_INIT_WORK);
160 /* vendor step 6 */
161 regmap_update_bits(rk3528->regmap, ACODEC_ANA08,
162 ACODEC_DAC_L_VREF_MASK,
163 ACODEC_DAC_L_VREF_EN);
164 regmap_update_bits(rk3528->regmap, ACODEC_ANA0C,
165 ACODEC_DAC_R_VREF_MASK,
166 ACODEC_DAC_R_VREF_EN);
167 /* vendor step 7 */
168 regmap_update_bits(rk3528->regmap, ACODEC_ANA08,
169 ACODEC_DAC_L_CLK_MASK,
170 ACODEC_DAC_L_CLK_EN);
171 regmap_update_bits(rk3528->regmap, ACODEC_ANA0C,
172 ACODEC_DAC_R_CLK_MASK,
173 ACODEC_DAC_R_CLK_EN);
174 /* vendor step 8 */
175 regmap_update_bits(rk3528->regmap, ACODEC_ANA08,
176 ACODEC_DAC_L_MASK,
177 ACODEC_DAC_L_EN);
178 regmap_update_bits(rk3528->regmap, ACODEC_ANA0C,
179 ACODEC_DAC_R_MASK,
180 ACODEC_DAC_R_EN);
181 /* vendor step 9 */
182 regmap_update_bits(rk3528->regmap, ACODEC_ANA08,
183 ACODEC_DAC_L_INIT_MASK,
184 ACODEC_DAC_L_WORK);
185 regmap_update_bits(rk3528->regmap, ACODEC_ANA0C,
186 ACODEC_DAC_R_INIT_MASK,
187 ACODEC_DAC_R_WORK);
188 /* vendor step 10 */
189 regmap_update_bits(rk3528->regmap, ACODEC_ANA09,
190 ACODEC_LINEOUT_L_MUTE_MASK,
191 ACODEC_LINEOUT_L_WORK);
192 regmap_update_bits(rk3528->regmap, ACODEC_ANA0D,
193 ACODEC_LINEOUT_R_MUTE_MASK,
194 ACODEC_LINEOUT_R_WORK);
195 /* vendor step 11, select the gain */
196 /* vendor step 12, play music */
197
198 return 0;
199 }
200
rk3528_codec_dac_disable(struct rk3528_codec_priv * rk3528)201 static int rk3528_codec_dac_disable(struct rk3528_codec_priv *rk3528)
202 {
203 /* vendor step 0, keep the dac channel work and input the mute signal */
204 /* vendor step 1, select the gain */
205 /* vendor step 2 */
206 regmap_update_bits(rk3528->regmap, ACODEC_ANA09,
207 ACODEC_LINEOUT_L_MUTE_MASK,
208 ACODEC_LINEOUT_L_MUTE);
209 regmap_update_bits(rk3528->regmap, ACODEC_ANA0D,
210 ACODEC_LINEOUT_R_MUTE_MASK,
211 ACODEC_LINEOUT_R_MUTE);
212 /* vendor step 3 */
213 regmap_update_bits(rk3528->regmap, ACODEC_ANA09,
214 ACODEC_LINEOUT_L_INIT_MASK,
215 ACODEC_LINEOUT_L_INIT);
216 regmap_update_bits(rk3528->regmap, ACODEC_ANA0D,
217 ACODEC_LINEOUT_R_INIT_MASK,
218 ACODEC_LINEOUT_R_INIT);
219 /* vendor step 4 */
220 regmap_update_bits(rk3528->regmap, ACODEC_ANA09,
221 ACODEC_LINEOUT_L_MASK,
222 ACODEC_LINEOUT_L_DIS);
223 regmap_update_bits(rk3528->regmap, ACODEC_ANA0D,
224 ACODEC_LINEOUT_R_MASK,
225 ACODEC_LINEOUT_R_DIS);
226 /* vendor step 5 */
227 regmap_update_bits(rk3528->regmap, ACODEC_ANA08,
228 ACODEC_DAC_L_MASK,
229 ACODEC_DAC_L_DIS);
230 regmap_update_bits(rk3528->regmap, ACODEC_ANA0C,
231 ACODEC_DAC_R_MASK,
232 ACODEC_DAC_R_DIS);
233 /* vendor step 6 */
234 regmap_update_bits(rk3528->regmap, ACODEC_ANA08,
235 ACODEC_DAC_L_CLK_MASK,
236 ACODEC_DAC_L_CLK_DIS);
237 regmap_update_bits(rk3528->regmap, ACODEC_ANA0C,
238 ACODEC_DAC_R_CLK_MASK,
239 ACODEC_DAC_R_CLK_DIS);
240 /* vendor step 7 */
241 regmap_update_bits(rk3528->regmap, ACODEC_ANA08,
242 ACODEC_DAC_L_VREF_MASK,
243 ACODEC_DAC_L_VREF_DIS);
244 regmap_update_bits(rk3528->regmap, ACODEC_ANA0C,
245 ACODEC_DAC_R_VREF_MASK,
246 ACODEC_DAC_R_VREF_DIS);
247 /* vendor step 8 */
248 regmap_update_bits(rk3528->regmap, ACODEC_ANA08,
249 ACODEC_DAC_L_POP_CTRL_MASK,
250 ACODEC_DAC_L_POP_CTRL_OFF);
251 regmap_update_bits(rk3528->regmap, ACODEC_ANA0C,
252 ACODEC_DAC_R_POP_CTRL_MASK,
253 ACODEC_DAC_R_POP_CTRL_OFF);
254 /* vendor step 9 */
255 regmap_update_bits(rk3528->regmap, ACODEC_ANA08,
256 ACODEC_DAC_L_BUF_MASK,
257 ACODEC_DAC_L_BUF_DIS);
258 regmap_update_bits(rk3528->regmap, ACODEC_ANA0C,
259 ACODEC_DAC_R_BUF_MASK,
260 ACODEC_DAC_R_BUF_DIS);
261 /* vendor step 10 */
262 regmap_update_bits(rk3528->regmap, ACODEC_ANA00,
263 ACODEC_IBIAS_DAC_MASK,
264 ACODEC_IBIAS_DAC_DIS);
265 /* vendor step 9 */
266 regmap_update_bits(rk3528->regmap, ACODEC_ANA08,
267 ACODEC_DAC_L_INIT_MASK,
268 ACODEC_DAC_L_INIT);
269 regmap_update_bits(rk3528->regmap, ACODEC_ANA0C,
270 ACODEC_DAC_R_INIT_MASK,
271 ACODEC_DAC_R_INIT);
272
273 return 0;
274 }
275
rk3528_codec_dac_dig_config(struct rk3528_codec_priv * rk3528,struct snd_pcm_hw_params * params)276 static int rk3528_codec_dac_dig_config(struct rk3528_codec_priv *rk3528,
277 struct snd_pcm_hw_params *params)
278 {
279 unsigned int dac_aif1 = 0;
280
281 switch (params_format(params)) {
282 case SNDRV_PCM_FORMAT_S16_LE:
283 dac_aif1 |= ACODEC_DAC_I2S_16B;
284 break;
285 case SNDRV_PCM_FORMAT_S20_3LE:
286 dac_aif1 |= ACODEC_DAC_I2S_20B;
287 break;
288 case SNDRV_PCM_FORMAT_S24_LE:
289 dac_aif1 |= ACODEC_DAC_I2S_24B;
290 break;
291 case SNDRV_PCM_FORMAT_S32_LE:
292 dac_aif1 |= ACODEC_DAC_I2S_32B;
293 break;
294 default:
295 return -EINVAL;
296 }
297
298 dac_aif1 |= ACODEC_DAC_I2S_I2S;
299 regmap_update_bits(rk3528->regmap, ACODEC_DIG01,
300 ACODEC_DAC_I2S_WL_MASK |
301 ACODEC_DAC_I2S_FMT_MASK,
302 dac_aif1);
303 regmap_update_bits(rk3528->regmap, ACODEC_DIG02,
304 ACODEC_DAC_I2S_RST_MASK,
305 ACODEC_DAC_I2S_RST_P);
306
307 return 0;
308 }
309
rk3528_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)310 static int rk3528_set_dai_fmt(struct snd_soc_dai *codec_dai,
311 unsigned int fmt)
312 {
313 struct snd_soc_component *component = codec_dai->component;
314 struct rk3528_codec_priv *rk3528 = snd_soc_component_get_drvdata(component);
315 unsigned int dac_aif1 = 0, dac_aif2 = 0;
316
317 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
318 case SND_SOC_DAIFMT_CBS_CFS:
319 dac_aif2 |= ACODEC_DAC_I2S_MST_FUNC_SLAVE;
320 dac_aif2 |= ACODEC_DAC_I2S_MST_IO_SLAVE;
321 break;
322 case SND_SOC_DAIFMT_CBM_CFM:
323 dac_aif2 |= ACODEC_DAC_I2S_MST_FUNC_MASTER;
324 dac_aif2 |= ACODEC_DAC_I2S_MST_IO_MASTER;
325 break;
326 default:
327 return -EINVAL;
328 }
329
330 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
331 case SND_SOC_DAIFMT_I2S:
332 dac_aif1 |= ACODEC_DAC_I2S_I2S;
333 break;
334 case SND_SOC_DAIFMT_LEFT_J:
335 dac_aif1 |= ACODEC_DAC_I2S_LJM;
336 break;
337 default:
338 return -EINVAL;
339 }
340
341 regmap_update_bits(rk3528->regmap, ACODEC_DIG01,
342 ACODEC_DAC_I2S_FMT_MASK,
343 dac_aif1);
344 regmap_update_bits(rk3528->regmap, ACODEC_DIG02,
345 ACODEC_DAC_I2S_MST_FUNC_MASK |
346 ACODEC_DAC_I2S_MST_IO_MASK,
347 dac_aif2);
348
349 return 0;
350 }
351
rk3528_mute_stream(struct snd_soc_dai * dai,int mute,int stream)352 static int rk3528_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
353 {
354 struct snd_soc_component *component = dai->component;
355 struct rk3528_codec_priv *rk3528 = snd_soc_component_get_drvdata(component);
356
357 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
358 if (mute) {
359 /* Mute DAC LINEOUT */
360 regmap_update_bits(rk3528->regmap,
361 ACODEC_ANA09,
362 ACODEC_LINEOUT_L_MUTE_MASK,
363 ACODEC_LINEOUT_L_MUTE);
364 regmap_update_bits(rk3528->regmap,
365 ACODEC_ANA0D,
366 ACODEC_LINEOUT_R_MUTE_MASK,
367 ACODEC_LINEOUT_R_MUTE);
368 rk3528_codec_pa_ctrl(rk3528, false);
369 } else {
370 /* Unmute DAC LINEOUT */
371 regmap_update_bits(rk3528->regmap,
372 ACODEC_ANA09,
373 ACODEC_LINEOUT_L_MUTE_MASK,
374 ACODEC_LINEOUT_L_WORK);
375 regmap_update_bits(rk3528->regmap,
376 ACODEC_ANA0D,
377 ACODEC_LINEOUT_R_MUTE_MASK,
378 ACODEC_LINEOUT_R_WORK);
379 rk3528_codec_pa_ctrl(rk3528, true);
380 }
381 }
382
383 return 0;
384 }
385
rk3528_codec_default_gains(struct rk3528_codec_priv * rk3528)386 static int rk3528_codec_default_gains(struct rk3528_codec_priv *rk3528)
387 {
388 /* Prepare DAC gains */
389 /* set LINEOUT default gains */
390 regmap_update_bits(rk3528->regmap, ACODEC_DIG06,
391 ACODEC_DAC_DIG_GAIN_MASK,
392 ACODEC_DAC_DIG_GAIN(ACODEC_DAC_DIG_0DB));
393 regmap_update_bits(rk3528->regmap, ACODEC_ANA0B,
394 ACODEC_LINEOUT_L_GAIN_MASK,
395 ACODEC_DAC_LINEOUT_GAIN_0DB);
396 regmap_update_bits(rk3528->regmap, ACODEC_ANA0F,
397 ACODEC_LINEOUT_R_GAIN_MASK,
398 ACODEC_DAC_LINEOUT_GAIN_0DB);
399
400 return 0;
401 }
402
rk3528_codec_open_playback(struct rk3528_codec_priv * rk3528)403 static int rk3528_codec_open_playback(struct rk3528_codec_priv *rk3528)
404 {
405 rk3528_codec_dac_enable(rk3528);
406
407 return 0;
408 }
409
rk3528_codec_close_playback(struct rk3528_codec_priv * rk3528)410 static int rk3528_codec_close_playback(struct rk3528_codec_priv *rk3528)
411 {
412 rk3528_codec_dac_disable(rk3528);
413 return 0;
414 }
415
rk3528_codec_dlp_down(struct rk3528_codec_priv * rk3528)416 static int rk3528_codec_dlp_down(struct rk3528_codec_priv *rk3528)
417 {
418 return 0;
419 }
420
rk3528_codec_dlp_up(struct rk3528_codec_priv * rk3528)421 static int rk3528_codec_dlp_up(struct rk3528_codec_priv *rk3528)
422 {
423 rk3528_codec_power_on(rk3528);
424
425 return 0;
426 }
427
rk3528_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)428 static int rk3528_hw_params(struct snd_pcm_substream *substream,
429 struct snd_pcm_hw_params *params,
430 struct snd_soc_dai *dai)
431 {
432 struct snd_soc_component *component = dai->component;
433 struct rk3528_codec_priv *rk3528 = snd_soc_component_get_drvdata(component);
434
435 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
436 rk3528_codec_open_playback(rk3528);
437 rk3528_codec_dac_dig_config(rk3528, params);
438 }
439
440 return 0;
441 }
442
rk3528_pcm_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)443 static void rk3528_pcm_shutdown(struct snd_pcm_substream *substream,
444 struct snd_soc_dai *dai)
445 {
446 struct snd_soc_component *component = dai->component;
447 struct rk3528_codec_priv *rk3528 = snd_soc_component_get_drvdata(component);
448
449 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
450 rk3528_codec_close_playback(rk3528);
451
452 regcache_cache_only(rk3528->regmap, false);
453 regcache_sync(rk3528->regmap);
454 }
455
rk3528_codec_prepare(struct rk3528_codec_priv * rk3528)456 static int rk3528_codec_prepare(struct rk3528_codec_priv *rk3528)
457 {
458 /* Clear registers for ADC and DAC */
459 rk3528_codec_close_playback(rk3528);
460 rk3528_codec_default_gains(rk3528);
461
462 return 0;
463 }
464
rk3528_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)465 static int rk3528_set_sysclk(struct snd_soc_dai *dai, int clk_id,
466 unsigned int freq, int dir)
467 {
468 struct snd_soc_component *component = dai->component;
469 struct rk3528_codec_priv *rk3528 = snd_soc_component_get_drvdata(component);
470 int ret;
471
472 if (!freq)
473 return 0;
474
475 ret = clk_set_rate(rk3528->mclk, freq);
476 if (ret)
477 dev_err(rk3528->plat_dev, "Failed to set mclk %d\n", ret);
478
479 return ret;
480 }
481
482 static const struct snd_soc_dai_ops rk3528_dai_ops = {
483 .hw_params = rk3528_hw_params,
484 .set_fmt = rk3528_set_dai_fmt,
485 .mute_stream = rk3528_mute_stream,
486 .shutdown = rk3528_pcm_shutdown,
487 .set_sysclk = rk3528_set_sysclk,
488 };
489
490 static struct snd_soc_dai_driver rk3528_dai[] = {
491 {
492 .name = "rk3528-hifi",
493 .id = ACODEC_HIFI,
494 .playback = {
495 .stream_name = "HiFi Playback",
496 .channels_min = 1,
497 .channels_max = 2,
498 .rates = SNDRV_PCM_RATE_8000_192000,
499 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
500 SNDRV_PCM_FMTBIT_S24_LE |
501 SNDRV_PCM_FMTBIT_S32_LE),
502 },
503 .ops = &rk3528_dai_ops,
504 },
505 };
506
rk3528_codec_probe(struct snd_soc_component * component)507 static int rk3528_codec_probe(struct snd_soc_component *component)
508 {
509 struct rk3528_codec_priv *rk3528 = snd_soc_component_get_drvdata(component);
510
511 rk3528->component = component;
512 rk3528_codec_reset(component);
513 rk3528_codec_dlp_up(rk3528);
514 rk3528_codec_prepare(rk3528);
515 regcache_cache_only(rk3528->regmap, false);
516 regcache_sync(rk3528->regmap);
517
518 return 0;
519 }
520
rk3528_codec_remove(struct snd_soc_component * component)521 static void rk3528_codec_remove(struct snd_soc_component *component)
522 {
523 struct rk3528_codec_priv *rk3528 = snd_soc_component_get_drvdata(component);
524
525 rk3528_codec_pa_ctrl(rk3528, false);
526 rk3528_codec_power_off(rk3528);
527 regcache_cache_only(rk3528->regmap, false);
528 regcache_sync(rk3528->regmap);
529 }
530
rk3528_codec_suspend(struct snd_soc_component * component)531 static int rk3528_codec_suspend(struct snd_soc_component *component)
532 {
533 struct rk3528_codec_priv *rk3528 = snd_soc_component_get_drvdata(component);
534
535 rk3528_codec_dlp_down(rk3528);
536 regcache_cache_only(rk3528->regmap, true);
537 clk_disable_unprepare(rk3528->mclk);
538 clk_disable_unprepare(rk3528->pclk);
539
540 return 0;
541 }
542
rk3528_codec_resume(struct snd_soc_component * component)543 static int rk3528_codec_resume(struct snd_soc_component *component)
544 {
545 struct rk3528_codec_priv *rk3528 = snd_soc_component_get_drvdata(component);
546 int ret = 0;
547
548 ret = clk_prepare_enable(rk3528->pclk);
549 if (ret < 0) {
550 dev_err(rk3528->plat_dev,
551 "Failed to enable acodec pclk: %d\n", ret);
552 goto pclk_error;
553 }
554
555 ret = clk_prepare_enable(rk3528->mclk);
556 if (ret < 0) {
557 dev_err(rk3528->plat_dev,
558 "Failed to enable acodec mclk: %d\n", ret);
559 goto mclk_error;
560 }
561
562 regcache_cache_only(rk3528->regmap, false);
563 ret = regcache_sync(rk3528->regmap);
564 if (ret)
565 goto reg_error;
566
567 rk3528_codec_dlp_up(rk3528);
568
569 return 0;
570 reg_error:
571 clk_disable_unprepare(rk3528->mclk);
572 mclk_error:
573 clk_disable_unprepare(rk3528->pclk);
574 pclk_error:
575 return ret;
576 }
577
578 static const DECLARE_TLV_DB_SCALE(rk3528_codec_dac_lineout_gain_tlv,
579 -3900, 150, 600);
580
581 static const struct snd_kcontrol_new rk3528_codec_dapm_controls[] = {
582 /* DAC LINEOUT */
583 SOC_SINGLE_RANGE_TLV("DAC LEFT LINEOUT Volume",
584 ACODEC_ANA0B,
585 ACODEC_LINEOUT_L_GAIN_SHIFT,
586 ACODEC_DAC_LINEOUT_GAIN_MIN,
587 ACODEC_DAC_LINEOUT_GAIN_MAX,
588 0, rk3528_codec_dac_lineout_gain_tlv),
589 SOC_SINGLE_RANGE_TLV("DAC RIGHT LINEOUT Volume",
590 ACODEC_ANA0F,
591 ACODEC_LINEOUT_R_GAIN_SHIFT,
592 ACODEC_DAC_LINEOUT_GAIN_MIN,
593 ACODEC_DAC_LINEOUT_GAIN_MAX,
594 0, rk3528_codec_dac_lineout_gain_tlv),
595 };
596
597 static const struct snd_soc_component_driver soc_codec_dev_rk3528 = {
598 .probe = rk3528_codec_probe,
599 .remove = rk3528_codec_remove,
600 .suspend = rk3528_codec_suspend,
601 .resume = rk3528_codec_resume,
602 .controls = rk3528_codec_dapm_controls,
603 .num_controls = ARRAY_SIZE(rk3528_codec_dapm_controls),
604 };
605
606 /* Set the default value or reset value */
607 static const struct reg_default rk3528_codec_reg_defaults[] = {
608 { ACODEC_DIG00, 0x71 },
609 { ACODEC_DIG03, 0x53 },
610 { ACODEC_DIG07, 0x03 },
611 { ACODEC_DIG08, 0xc3 },
612 { ACODEC_DIG09, 0x28 },
613 { ACODEC_DIG0A, 0x1 },
614 { ACODEC_DIG0B, 0x80 },
615 { ACODEC_DIG0D, 0xc3 },
616 { ACODEC_DIG0E, 0xc3 },
617 { ACODEC_DIG10, 0xf1 },
618 { ACODEC_DIG11, 0xf1 },
619 { ACODEC_ANA02, 0x77 },
620 { ACODEC_ANA08, 0x20 },
621 { ACODEC_ANA0A, 0x8 },
622 { ACODEC_ANA0C, 0x20 },
623 { ACODEC_ANA0E, 0x8 },
624 };
625
rk3528_codec_volatile_reg(struct device * dev,unsigned int reg)626 static bool rk3528_codec_volatile_reg(struct device *dev, unsigned int reg)
627 {
628 switch (reg) {
629 case ACODEC_DIG00:
630 return true;
631 default:
632 return false;
633 }
634 return true;
635 }
636
637 static const struct regmap_config rk3528_codec_regmap_config = {
638 .reg_bits = 32,
639 .reg_stride = 4,
640 .val_bits = 32,
641 .max_register = ACODEC_REG_MAX,
642 .volatile_reg = rk3528_codec_volatile_reg,
643 .reg_defaults = rk3528_codec_reg_defaults,
644 .num_reg_defaults = ARRAY_SIZE(rk3528_codec_reg_defaults),
645 .cache_type = REGCACHE_FLAT,
646 };
647
648 static const struct of_device_id rk3528_codec_of_match[] = {
649 { .compatible = "rockchip,rk3528-codec", },
650 {},
651 };
652
653 MODULE_DEVICE_TABLE(of, rk3528_codec_of_match);
654
rk3528_platform_probe(struct platform_device * pdev)655 static int rk3528_platform_probe(struct platform_device *pdev)
656 {
657 struct device_node *np = pdev->dev.of_node;
658 struct rk3528_codec_priv *rk3528;
659 struct resource *res;
660 void __iomem *base;
661 int ret;
662
663 rk3528 = devm_kzalloc(&pdev->dev, sizeof(*rk3528), GFP_KERNEL);
664 if (!rk3528)
665 return -ENOMEM;
666
667 rk3528->plat_dev = &pdev->dev;
668 rk3528->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "acodec");
669 if (IS_ERR(rk3528->reset))
670 return PTR_ERR(rk3528->reset);
671
672 rk3528->pa_ctl_gpio = devm_gpiod_get_optional(&pdev->dev, "pa-ctl",
673 GPIOD_OUT_LOW);
674 if (IS_ERR(rk3528->pa_ctl_gpio)) {
675 dev_err(&pdev->dev, "Unable to claim gpio pa-ctl\n");
676 return -EINVAL;
677 }
678
679 if (rk3528->pa_ctl_gpio)
680 of_property_read_u32(np, "pa-ctl-delay-ms",
681 &rk3528->pa_ctl_delay_ms);
682
683 dev_info(&pdev->dev, "%s pa_ctl_gpio and pa_ctl_delay_ms: %d\n",
684 rk3528->pa_ctl_gpio ? "Use" : "No use",
685 rk3528->pa_ctl_delay_ms);
686
687 /* Close external PA during startup. */
688 rk3528_codec_pa_ctrl(rk3528, false);
689
690 rk3528->pclk = devm_clk_get(&pdev->dev, "pclk");
691 if (IS_ERR(rk3528->pclk)) {
692 dev_err(&pdev->dev, "Can't get acodec pclk\n");
693 return -EINVAL;
694 }
695
696 rk3528->mclk = devm_clk_get(&pdev->dev, "mclk");
697 if (IS_ERR(rk3528->mclk)) {
698 dev_err(&pdev->dev, "Can't get acodec mclk\n");
699 return -EINVAL;
700 }
701
702 ret = clk_prepare_enable(rk3528->pclk);
703 if (ret < 0) {
704 dev_err(&pdev->dev, "Failed to enable acodec pclk: %d\n", ret);
705 return ret;
706 }
707
708 ret = clk_prepare_enable(rk3528->mclk);
709 if (ret < 0) {
710 dev_err(&pdev->dev, "Failed to enable acodec mclk: %d\n", ret);
711 goto failed_1;
712 }
713
714 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
715 base = devm_ioremap_resource(&pdev->dev, res);
716 if (IS_ERR(base)) {
717 ret = PTR_ERR(base);
718 dev_err(&pdev->dev, "Failed to ioremap resource\n");
719 goto failed;
720 }
721
722 rk3528->regmap = devm_regmap_init_mmio(&pdev->dev, base,
723 &rk3528_codec_regmap_config);
724 if (IS_ERR(rk3528->regmap)) {
725 ret = PTR_ERR(rk3528->regmap);
726 dev_err(&pdev->dev, "Failed to regmap mmio\n");
727 goto failed;
728 }
729
730 platform_set_drvdata(pdev, rk3528);
731 ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_dev_rk3528,
732 rk3528_dai, ARRAY_SIZE(rk3528_dai));
733 if (ret < 0) {
734 dev_err(&pdev->dev, "Failed to register codec: %d\n", ret);
735 goto failed;
736 }
737
738 return ret;
739
740 failed:
741 clk_disable_unprepare(rk3528->mclk);
742 failed_1:
743 clk_disable_unprepare(rk3528->pclk);
744
745 return ret;
746 }
747
rk3528_platform_remove(struct platform_device * pdev)748 static int rk3528_platform_remove(struct platform_device *pdev)
749 {
750 struct rk3528_codec_priv *rk3528 =
751 (struct rk3528_codec_priv *)platform_get_drvdata(pdev);
752
753 clk_disable_unprepare(rk3528->mclk);
754 clk_disable_unprepare(rk3528->pclk);
755
756 return 0;
757 }
758
759 static struct platform_driver rk3528_codec_driver = {
760 .driver = {
761 .name = CODEC_DRV_NAME,
762 .of_match_table = of_match_ptr(rk3528_codec_of_match),
763 },
764 .probe = rk3528_platform_probe,
765 .remove = rk3528_platform_remove,
766 };
767 module_platform_driver(rk3528_codec_driver);
768
769 MODULE_DESCRIPTION("ASoC rk3528 Codec Driver");
770 MODULE_AUTHOR("Jason Zhu <jason.zhu@rock-chips.com>");
771 MODULE_LICENSE("GPL");
772