1 /*
2 * rk312x_codec.c
3 *
4 * Driver for rockchip rk312x codec
5 * Copyright (C) 2014
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 *
13 */
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/device.h>
18 #include <linux/delay.h>
19 #include <linux/clk.h>
20 #include <linux/version.h>
21 #include <linux/of.h>
22 #include <linux/of_gpio.h>
23 #include <linux/clk.h>
24 #include <linux/io.h>
25 #include <linux/rockchip/grf.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/regmap.h>
29 #include <linux/mfd/syscon.h>
30 #include <linux/slab.h>
31 #include <asm/dma.h>
32 #include <sound/core.h>
33 #include <sound/pcm.h>
34 #include <sound/pcm_params.h>
35 #include <sound/initval.h>
36 #include <sound/soc.h>
37 #include <sound/soc-dapm.h>
38 #include <sound/dmaengine_pcm.h>
39 #include <linux/io.h>
40 #include <linux/spinlock.h>
41 #include <sound/tlv.h>
42 #include <linux/extcon-provider.h>
43 #include "rk312x_codec.h"
44
45 static int debug = -1;
46 module_param(debug, int, S_IRUGO|S_IWUSR);
47
48 #define dbg_codec(level, fmt, arg...) \
49 do { \
50 if (debug >= level) \
51 printk(fmt , ## arg); \
52 } while (0)
53
54 #define DBG(fmt, ...) dbg_codec(0, fmt, ## __VA_ARGS__)
55
56 #define INVALID_GPIO -1
57 #define CODEC_SET_SPK 1
58 #define CODEC_SET_HP 2
59 #define SWITCH_SPK 1
60 #define GRF_ACODEC_CON 0x013c
61 #define GRF_SOC_STATUS0 0x014c
62 /* volume setting
63 * 0: -39dB
64 * 26: 0dB
65 * 31: 6dB
66 * Step: 1.5dB
67 */
68 #define OUT_VOLUME 25
69
70 /* capture vol set
71 * 0: -18db
72 * 12: 0db
73 * 31: 28.5db
74 * step: 1.5db
75 */
76 #define CAP_VOL 26 /*0-31 */
77 /*with capacity or not*/
78 #define WITH_CAP
79
80 struct rk312x_codec_priv {
81 void __iomem *regbase;
82 struct regmap *regmap;
83 struct regmap *grf;
84 struct device *dev;
85 unsigned int irq;
86 struct snd_soc_component *component;
87
88 unsigned int stereo_sysclk;
89 unsigned int rate;
90
91 int playback_active;
92 int capture_active;
93 struct gpio_desc *spk_ctl_gpio;
94 struct gpio_desc *hp_ctl_gpio;
95 int spk_mute_delay;
96 int hp_mute_delay;
97 int spk_hp_switch_gpio;
98 /* 1 spk; */
99 /* 0 hp; */
100 enum of_gpio_flags spk_io;
101
102 /* 0 for box; */
103 /* 1 default for mid; */
104 int rk312x_for_mid;
105 /* 1: for rk3128 */
106 /* 0: for rk3126 */
107 int is_rk3128;
108 int gpio_debug;
109 int codec_hp_det;
110 unsigned int spk_volume;
111 unsigned int hp_volume;
112 unsigned int capture_volume;
113
114 long int playback_path;
115 long int capture_path;
116 long int voice_call_path;
117 struct clk *pclk;
118 struct clk *mclk;
119 struct extcon_dev *edev;
120 struct work_struct work;
121 struct delayed_work init_delayed_work;
122 struct delayed_work mute_delayed_work;
123 struct delayed_work hpdet_work;
124 };
125
126 static const unsigned int headset_extcon_cable[] = {
127 EXTCON_JACK_MICROPHONE,
128 EXTCON_JACK_HEADPHONE,
129 EXTCON_NONE,
130 };
131
132 static struct rk312x_codec_priv *rk312x_priv;
133
134 #define RK312x_CODEC_ALL 0
135 #define RK312x_CODEC_PLAYBACK 1
136 #define RK312x_CODEC_CAPTURE 2
137 #define RK312x_CODEC_INCALL 3
138
139 #define RK312x_CODEC_WORK_NULL 0
140 #define RK312x_CODEC_WORK_POWER_DOWN 1
141 #define RK312x_CODEC_WORK_POWER_UP 2
142 static struct workqueue_struct *rk312x_codec_workq;
143
144 static void rk312x_codec_capture_work(struct work_struct *work);
145 static void rk312x_codec_unpop(struct work_struct *work);
146 static DECLARE_DELAYED_WORK(capture_delayed_work, rk312x_codec_capture_work);
147 static int rk312x_codec_work_capture_type = RK312x_CODEC_WORK_NULL;
148 /* static bool rk312x_for_mid = 1; */
149 static int rk312x_codec_power_up(int type);
150 static const unsigned int rk312x_reg_defaults[RK312x_PGAR_AGC_CTL5+1] = {
151 [RK312x_RESET] = 0x0003,
152 [RK312x_ADC_INT_CTL1] = 0x0050,
153 [RK312x_ADC_INT_CTL2] = 0x000e,
154 [RK312x_DAC_INT_CTL1] = 0x0050,
155 [RK312x_DAC_INT_CTL2] = 0x000e,
156 [RK312x_DAC_INT_CTL3] = 0x22,
157 [RK312x_ADC_MIC_CTL] = 0x0000,
158 [RK312x_BST_CTL] = 0x000,
159 [RK312x_ALC_MUNIN_CTL] = 0x0044,
160 [RK312x_BSTL_ALCL_CTL] = 0x000c,
161 [RK312x_ALCR_GAIN_CTL] = 0x000C,
162 [RK312x_ADC_ENABLE] = 0x0000,
163 [RK312x_DAC_CTL] = 0x0000,
164 [RK312x_DAC_ENABLE] = 0x0000,
165 [RK312x_HPMIX_CTL] = 0x0000,
166 [RK312x_HPMIX_S_SELECT] = 0x0000,
167 [RK312x_HPOUT_CTL] = 0x0000,
168 [RK312x_HPOUTL_GAIN] = 0x0000,
169 [RK312x_HPOUTR_GAIN] = 0x0000,
170 [RK312x_SELECT_CURRENT] = 0x003e,
171 [RK312x_PGAL_AGC_CTL1] = 0x0000,
172 [RK312x_PGAL_AGC_CTL2] = 0x0046,
173 [RK312x_PGAL_AGC_CTL3] = 0x0041,
174 [RK312x_PGAL_AGC_CTL4] = 0x002c,
175 [RK312x_PGAL_ASR_CTL] = 0x0000,
176 [RK312x_PGAL_AGC_MAX_H] = 0x0026,
177 [RK312x_PGAL_AGC_MAX_L] = 0x0040,
178 [RK312x_PGAL_AGC_MIN_H] = 0x0036,
179 [RK312x_PGAL_AGC_MIN_L] = 0x0020,
180 [RK312x_PGAL_AGC_CTL5] = 0x0038,
181 [RK312x_PGAR_AGC_CTL1] = 0x0000,
182 [RK312x_PGAR_AGC_CTL2] = 0x0046,
183 [RK312x_PGAR_AGC_CTL3] = 0x0041,
184 [RK312x_PGAR_AGC_CTL4] = 0x002c,
185 [RK312x_PGAR_ASR_CTL] = 0x0000,
186 [RK312x_PGAR_AGC_MAX_H] = 0x0026,
187 [RK312x_PGAR_AGC_MAX_L] = 0x0040,
188 [RK312x_PGAR_AGC_MIN_H] = 0x0036,
189 [RK312x_PGAR_AGC_MIN_L] = 0x0020,
190 [RK312x_PGAR_AGC_CTL5] = 0x0038,
191 };
192
rk312x_volatile_register(struct device * dev,unsigned int reg)193 static bool rk312x_volatile_register(struct device *dev, unsigned int reg)
194 {
195 switch (reg) {
196 case RK312x_RESET:
197 return true;
198 default:
199 return false;
200 }
201 }
202
rk312x_codec_register(struct device * dev,unsigned int reg)203 static bool rk312x_codec_register(struct device *dev, unsigned int reg)
204 {
205 switch (reg) {
206 case RK312x_RESET:
207 case RK312x_ADC_INT_CTL1:
208 case RK312x_ADC_INT_CTL2:
209 case RK312x_DAC_INT_CTL1:
210 case RK312x_DAC_INT_CTL2:
211 case RK312x_DAC_INT_CTL3:
212 case RK312x_ADC_MIC_CTL:
213 case RK312x_BST_CTL:
214 case RK312x_ALC_MUNIN_CTL:
215 case RK312x_BSTL_ALCL_CTL:
216 case RK312x_ALCR_GAIN_CTL:
217 case RK312x_ADC_ENABLE:
218 case RK312x_DAC_CTL:
219 case RK312x_DAC_ENABLE:
220 case RK312x_HPMIX_CTL:
221 case RK312x_HPMIX_S_SELECT:
222 case RK312x_HPOUT_CTL:
223 case RK312x_HPOUTL_GAIN:
224 case RK312x_HPOUTR_GAIN:
225 case RK312x_SELECT_CURRENT:
226 case RK312x_PGAL_AGC_CTL1:
227 case RK312x_PGAL_AGC_CTL2:
228 case RK312x_PGAL_AGC_CTL3:
229 case RK312x_PGAL_AGC_CTL4:
230 case RK312x_PGAL_ASR_CTL:
231 case RK312x_PGAL_AGC_MAX_H:
232 case RK312x_PGAL_AGC_MAX_L:
233 case RK312x_PGAL_AGC_MIN_H:
234 case RK312x_PGAL_AGC_MIN_L:
235 case RK312x_PGAL_AGC_CTL5:
236 case RK312x_PGAR_AGC_CTL1:
237 case RK312x_PGAR_AGC_CTL2:
238 case RK312x_PGAR_AGC_CTL3:
239 case RK312x_PGAR_AGC_CTL4:
240 case RK312x_PGAR_ASR_CTL:
241 case RK312x_PGAR_AGC_MAX_H:
242 case RK312x_PGAR_AGC_MAX_L:
243 case RK312x_PGAR_AGC_MIN_H:
244 case RK312x_PGAR_AGC_MIN_L:
245 case RK312x_PGAR_AGC_CTL5:
246 case RK312x_ALC_CTL:
247 return true;
248 default:
249 return false;
250 }
251 }
252
rk312x_codec_ctl_gpio(int gpio,int level)253 static int rk312x_codec_ctl_gpio(int gpio, int level)
254 {
255
256 if (!rk312x_priv) {
257 DBG("%s : rk312x is NULL\n", __func__);
258 return -EINVAL;
259 }
260
261 if ((gpio & CODEC_SET_SPK) && rk312x_priv &&
262 rk312x_priv->spk_ctl_gpio) {
263 gpiod_set_value(rk312x_priv->spk_ctl_gpio, level);
264 DBG(KERN_INFO"%s set spk clt %d\n", __func__, level);
265 msleep(rk312x_priv->spk_mute_delay);
266 }
267
268 if ((gpio & CODEC_SET_HP) && rk312x_priv &&
269 rk312x_priv->hp_ctl_gpio) {
270 gpiod_set_value(rk312x_priv->hp_ctl_gpio, level);
271 DBG(KERN_INFO"%s set hp clt %d\n", __func__, level);
272 msleep(rk312x_priv->hp_mute_delay);
273 }
274
275 return 0;
276 }
277
278 #if 0
279 static int switch_to_spk(int enable)
280 {
281 if (!rk312x_priv) {
282 DBG(KERN_ERR"%s : rk312x is NULL\n", __func__);
283 return -EINVAL;
284 }
285 if (enable) {
286 if (rk312x_priv->spk_hp_switch_gpio != INVALID_GPIO) {
287 gpio_set_value(rk312x_priv->spk_hp_switch_gpio, rk312x_priv->spk_io);
288 DBG(KERN_INFO"%s switch to spk\n", __func__);
289 msleep(rk312x_priv->spk_mute_delay);
290 }
291 } else {
292 if (rk312x_priv->spk_hp_switch_gpio != INVALID_GPIO) {
293 gpio_set_value(rk312x_priv->spk_hp_switch_gpio, !rk312x_priv->spk_io);
294 DBG(KERN_INFO"%s switch to hp\n", __func__);
295 msleep(rk312x_priv->hp_mute_delay);
296 }
297 }
298 return 0;
299 }
300 #endif
301
rk312x_reset(struct snd_soc_component * component)302 static int rk312x_reset(struct snd_soc_component *component)
303 {
304 DBG("%s\n", __func__);
305 regmap_write(rk312x_priv->regmap, RK312x_RESET, 0x00);
306 mdelay(10);
307 regmap_write(rk312x_priv->regmap, RK312x_RESET, 0x43);
308 mdelay(10);
309
310 return 0;
311 }
312
313 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -3900, 150, 0);
314 static const DECLARE_TLV_DB_SCALE(pga_vol_tlv, -1800, 150, 0);
315 static const DECLARE_TLV_DB_SCALE(bst_vol_tlv, 0, 2000, 0);
316 static const DECLARE_TLV_DB_SCALE(pga_agc_max_vol_tlv, -1350, 600, 0);
317 static const DECLARE_TLV_DB_SCALE(pga_agc_min_vol_tlv, -1800, 600, 0);
318
319 static const char *const rk312x_input_mode[] = {
320 "Differential", "Single-Ended"};
321
322 static const char *const rk312x_micbias_ratio[] = {
323 "1.0 Vref", "1.1 Vref",
324 "1.2 Vref", "1.3 Vref",
325 "1.4 Vref", "1.5 Vref",
326 "1.6 Vref", "1.7 Vref",};
327
328 static const char *const rk312x_dis_en_sel[] = {"Disable", "Enable"};
329
330 static const char *const rk312x_pga_agc_way[] = {"Normal", "Jack"};
331
332 static const char *const rk312x_agc_backup_way[] = {
333 "Normal", "Jack1", "Jack2", "Jack3"};
334
335 static const char *const rk312x_pga_agc_hold_time[] = {
336 "0ms", "2ms", "4ms", "8ms",
337 "16ms", "32ms", "64ms",
338 "128ms", "256ms", "512ms", "1s"};
339
340 static const char *const rk312x_pga_agc_ramp_up_time[] = {
341 "Normal:500us Jack:125us",
342 "Normal:1ms Jack:250us",
343 "Normal:2ms Jack:500us",
344 "Normal:4ms Jack:1ms",
345 "Normal:8ms Jack:2ms",
346 "Normal:16ms Jack:4ms",
347 "Normal:32ms Jack:8ms",
348 "Normal:64ms Jack:16ms",
349 "Normal:128ms Jack:32ms",
350 "Normal:256ms Jack:64ms",
351 "Normal:512ms Jack:128ms"};
352
353 static const char *const rk312x_pga_agc_ramp_down_time[] = {
354 "Normal:125us Jack:32us",
355 "Normal:250us Jack:64us",
356 "Normal:500us Jack:125us",
357 "Normal:1ms Jack:250us",
358 "Normal:2ms Jack:500us",
359 "Normal:4ms Jack:1ms",
360 "Normal:8ms Jack:2ms",
361 "Normal:16ms Jack:4ms",
362 "Normal:32ms Jack:8ms",
363 "Normal:64ms Jack:16ms",
364 "Normal:128ms Jack:32ms"};
365
366 static const char *const rk312x_pga_agc_mode[] = {"Normal", "Limiter"};
367
368 static const char *const rk312x_pga_agc_recovery_mode[] = {
369 "Right Now", "After AGC to Limiter"};
370
371 static const char *const rk312x_pga_agc_noise_gate_threhold[] = {
372 "-39dB", "-45dB", "-51dB",
373 "-57dB", "-63dB", "-69dB", "-75dB", "-81dB"};
374
375 static const char *const rk312x_pga_agc_update_gain[] = {
376 "Right Now", "After 1st Zero Cross"};
377
378 static const char *const rk312x_pga_agc_approximate_sample_rate[] = {
379 "96KHZ", "48KHz", "441KHZ", "32KHz",
380 "24KHz", "16KHz", "12KHz", "8KHz"};
381
382 static const struct soc_enum rk312x_bst_enum[] = {
383 SOC_ENUM_SINGLE(RK312x_BSTL_ALCL_CTL,
384 RK312x_BSTL_MODE_SFT, 2,
385 rk312x_input_mode),
386 };
387
388
389 static const struct soc_enum rk312x_micbias_enum[] = {
390 SOC_ENUM_SINGLE(RK312x_ADC_MIC_CTL,
391 RK312x_MICBIAS_VOL_SHT, 8,
392 rk312x_micbias_ratio),
393 };
394
395 static const struct soc_enum rk312x_agcl_enum[] = {
396 SOC_ENUM_SINGLE(RK312x_PGAL_AGC_CTL1,
397 RK312x_PGA_AGC_BK_WAY_SFT, 4,
398 rk312x_agc_backup_way),/*0*/
399 SOC_ENUM_SINGLE(RK312x_PGAL_AGC_CTL1,
400 RK312x_PGA_AGC_WAY_SFT, 2,
401 rk312x_pga_agc_way),/*1*/
402 SOC_ENUM_SINGLE(RK312x_PGAL_AGC_CTL1,
403 RK312x_PGA_AGC_HOLD_T_SFT, 11,
404 rk312x_pga_agc_hold_time),/*2*/
405 SOC_ENUM_SINGLE(RK312x_PGAL_AGC_CTL2,
406 RK312x_PGA_AGC_GRU_T_SFT, 11,
407 rk312x_pga_agc_ramp_up_time),/*3*/
408 SOC_ENUM_SINGLE(RK312x_PGAL_AGC_CTL2,
409 RK312x_PGA_AGC_GRD_T_SFT, 11,
410 rk312x_pga_agc_ramp_down_time),/*4*/
411 SOC_ENUM_SINGLE(RK312x_PGAL_AGC_CTL3,
412 RK312x_PGA_AGC_MODE_SFT, 2,
413 rk312x_pga_agc_mode),/*5*/
414 SOC_ENUM_SINGLE(RK312x_PGAL_AGC_CTL3,
415 RK312x_PGA_AGC_ZO_SFT, 2,
416 rk312x_dis_en_sel),/*6*/
417 SOC_ENUM_SINGLE(RK312x_PGAL_AGC_CTL3,
418 RK312x_PGA_AGC_REC_MODE_SFT, 2,
419 rk312x_pga_agc_recovery_mode),/*7*/
420 SOC_ENUM_SINGLE(RK312x_PGAL_AGC_CTL3,
421 RK312x_PGA_AGC_FAST_D_SFT, 2,
422 rk312x_dis_en_sel),/*8*/
423 SOC_ENUM_SINGLE(RK312x_PGAL_AGC_CTL3,
424 RK312x_PGA_AGC_NG_SFT, 2,
425 rk312x_dis_en_sel),/*9*/
426 SOC_ENUM_SINGLE(RK312x_PGAL_AGC_CTL3,
427 RK312x_PGA_AGC_NG_THR_SFT, 8,
428 rk312x_pga_agc_noise_gate_threhold),/*10*/
429 SOC_ENUM_SINGLE(RK312x_PGAL_AGC_CTL4,
430 RK312x_PGA_AGC_ZO_MODE_SFT, 2,
431 rk312x_pga_agc_update_gain),/*11*/
432 SOC_ENUM_SINGLE(RK312x_PGAL_ASR_CTL,
433 RK312x_PGA_SLOW_CLK_SFT, 2,
434 rk312x_dis_en_sel),/*12*/
435 SOC_ENUM_SINGLE(RK312x_PGAL_ASR_CTL,
436 RK312x_PGA_ASR_SFT, 8,
437 rk312x_pga_agc_approximate_sample_rate),/*13*/
438 SOC_ENUM_SINGLE(RK312x_PGAL_AGC_CTL5,
439 RK312x_PGA_AGC_SFT, 2,
440 rk312x_dis_en_sel),/*14*/
441 };
442
443 static const struct soc_enum rk312x_agcr_enum[] = {
444 SOC_ENUM_SINGLE(RK312x_PGAR_AGC_CTL1,
445 RK312x_PGA_AGC_BK_WAY_SFT, 4,
446 rk312x_agc_backup_way),/*0*/
447 SOC_ENUM_SINGLE(RK312x_PGAR_AGC_CTL1,
448 RK312x_PGA_AGC_WAY_SFT, 2,
449 rk312x_pga_agc_way),/*1*/
450 SOC_ENUM_SINGLE(RK312x_PGAR_AGC_CTL1,
451 RK312x_PGA_AGC_HOLD_T_SFT, 11,
452 rk312x_pga_agc_hold_time),/*2*/
453 SOC_ENUM_SINGLE(RK312x_PGAR_AGC_CTL2,
454 RK312x_PGA_AGC_GRU_T_SFT, 11,
455 rk312x_pga_agc_ramp_up_time),/*3*/
456 SOC_ENUM_SINGLE(RK312x_PGAR_AGC_CTL2,
457 RK312x_PGA_AGC_GRD_T_SFT, 11,
458 rk312x_pga_agc_ramp_down_time),/*4*/
459 SOC_ENUM_SINGLE(RK312x_PGAR_AGC_CTL3,
460 RK312x_PGA_AGC_MODE_SFT, 2,
461 rk312x_pga_agc_mode),/*5*/
462 SOC_ENUM_SINGLE(RK312x_PGAR_AGC_CTL3,
463 RK312x_PGA_AGC_ZO_SFT, 2,
464 rk312x_dis_en_sel),/*6*/
465 SOC_ENUM_SINGLE(RK312x_PGAR_AGC_CTL3,
466 RK312x_PGA_AGC_REC_MODE_SFT, 2,
467 rk312x_pga_agc_recovery_mode),/*7*/
468 SOC_ENUM_SINGLE(RK312x_PGAR_AGC_CTL3,
469 RK312x_PGA_AGC_FAST_D_SFT, 2,
470 rk312x_dis_en_sel),/*8*/
471 SOC_ENUM_SINGLE(RK312x_PGAR_AGC_CTL3,
472 RK312x_PGA_AGC_NG_SFT, 2, rk312x_dis_en_sel),/*9*/
473 SOC_ENUM_SINGLE(RK312x_PGAR_AGC_CTL3,
474 RK312x_PGA_AGC_NG_THR_SFT, 8,
475 rk312x_pga_agc_noise_gate_threhold),/*10*/
476 SOC_ENUM_SINGLE(RK312x_PGAR_AGC_CTL4,
477 RK312x_PGA_AGC_ZO_MODE_SFT, 2,
478 rk312x_pga_agc_update_gain),/*11*/
479 SOC_ENUM_SINGLE(RK312x_PGAR_ASR_CTL,
480 RK312x_PGA_SLOW_CLK_SFT, 2,
481 rk312x_dis_en_sel),/*12*/
482 SOC_ENUM_SINGLE(RK312x_PGAR_ASR_CTL,
483 RK312x_PGA_ASR_SFT, 8,
484 rk312x_pga_agc_approximate_sample_rate),/*13*/
485 SOC_ENUM_SINGLE(RK312x_PGAR_AGC_CTL5,
486 RK312x_PGA_AGC_SFT, 2,
487 rk312x_dis_en_sel),/*14*/
488 };
489
490 static const struct snd_kcontrol_new rk312x_snd_controls[] = {
491 /* Add for set voice volume */
492 SOC_DOUBLE_R_TLV("Speaker Playback Volume", RK312x_HPOUTL_GAIN,
493 RK312x_HPOUTR_GAIN, RK312x_HPOUT_GAIN_SFT,
494 31, 0, out_vol_tlv),
495 SOC_DOUBLE("Speaker Playback Switch", RK312x_HPOUT_CTL,
496 RK312x_HPOUTL_MUTE_SHT, RK312x_HPOUTR_MUTE_SHT, 1, 0),
497 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RK312x_HPOUTL_GAIN,
498 RK312x_HPOUTR_GAIN, RK312x_HPOUT_GAIN_SFT,
499 31, 0, out_vol_tlv),
500 SOC_DOUBLE("Headphone Playback Switch", RK312x_HPOUT_CTL,
501 RK312x_HPOUTL_MUTE_SHT, RK312x_HPOUTR_MUTE_SHT, 1, 0),
502 SOC_DOUBLE_R_TLV("Earpiece Playback Volume", RK312x_HPOUTL_GAIN,
503 RK312x_HPOUTR_GAIN, RK312x_HPOUT_GAIN_SFT,
504 31, 0, out_vol_tlv),
505 SOC_DOUBLE("Earpiece Playback Switch", RK312x_HPOUT_CTL,
506 RK312x_HPOUTL_MUTE_SHT, RK312x_HPOUTR_MUTE_SHT, 1, 0),
507
508
509 /* Add for set capture mute */
510 SOC_SINGLE_TLV("Main Mic Capture Volume", RK312x_BST_CTL,
511 RK312x_BSTL_GAIN_SHT, 1, 0, bst_vol_tlv),
512 SOC_SINGLE("Main Mic Capture Switch", RK312x_BST_CTL,
513 RK312x_BSTL_MUTE_SHT, 1, 0),
514 SOC_SINGLE_TLV("Headset Mic Capture Volume", RK312x_BST_CTL,
515 RK312x_BSTR_GAIN_SHT, 1, 0, bst_vol_tlv),
516 SOC_SINGLE("Headset Mic Capture Switch", RK312x_BST_CTL,
517 RK312x_BSTR_MUTE_SHT, 1, 0),
518
519 SOC_SINGLE("ALCL Switch", RK312x_ALC_MUNIN_CTL,
520 RK312x_ALCL_MUTE_SHT, 1, 0),
521 SOC_SINGLE_TLV("ALCL Capture Volume", RK312x_BSTL_ALCL_CTL,
522 RK312x_ALCL_GAIN_SHT, 31, 0, pga_vol_tlv),
523 SOC_SINGLE("ALCR Switch", RK312x_ALC_MUNIN_CTL,
524 RK312x_ALCR_MUTE_SHT, 1, 0),
525 SOC_SINGLE_TLV("ALCR Capture Volume", RK312x_ALCR_GAIN_CTL,
526 RK312x_ALCL_GAIN_SHT, 31, 0, pga_vol_tlv),
527
528 SOC_ENUM("BST_L Mode", rk312x_bst_enum[0]),
529
530 SOC_ENUM("Micbias Voltage", rk312x_micbias_enum[0]),
531 SOC_ENUM("PGAL AGC Back Way", rk312x_agcl_enum[0]),
532 SOC_ENUM("PGAL AGC Way", rk312x_agcl_enum[1]),
533 SOC_ENUM("PGAL AGC Hold Time", rk312x_agcl_enum[2]),
534 SOC_ENUM("PGAL AGC Ramp Up Time", rk312x_agcl_enum[3]),
535 SOC_ENUM("PGAL AGC Ramp Down Time", rk312x_agcl_enum[4]),
536 SOC_ENUM("PGAL AGC Mode", rk312x_agcl_enum[5]),
537 SOC_ENUM("PGAL AGC Gain Update Zero Enable", rk312x_agcl_enum[6]),
538 SOC_ENUM("PGAL AGC Gain Recovery LPGA VOL", rk312x_agcl_enum[7]),
539 SOC_ENUM("PGAL AGC Fast Decrement Enable", rk312x_agcl_enum[8]),
540 SOC_ENUM("PGAL AGC Noise Gate Enable", rk312x_agcl_enum[9]),
541 SOC_ENUM("PGAL AGC Noise Gate Threhold", rk312x_agcl_enum[10]),
542 SOC_ENUM("PGAL AGC Upate Gain", rk312x_agcl_enum[11]),
543 SOC_ENUM("PGAL AGC Slow Clock Enable", rk312x_agcl_enum[12]),
544 SOC_ENUM("PGAL AGC Approximate Sample Rate", rk312x_agcl_enum[13]),
545 SOC_ENUM("PGAL AGC Enable", rk312x_agcl_enum[14]),
546
547 SOC_SINGLE_TLV("PGAL AGC Volume", RK312x_PGAL_AGC_CTL4,
548 RK312x_PGA_AGC_VOL_SFT, 31, 0, pga_vol_tlv),
549
550 SOC_SINGLE("PGAL AGC Max Level High 8 Bits",
551 RK312x_PGAL_AGC_MAX_H,
552 0, 255, 0),
553 SOC_SINGLE("PGAL AGC Max Level Low 8 Bits",
554 RK312x_PGAL_AGC_MAX_L,
555 0, 255, 0),
556 SOC_SINGLE("PGAL AGC Min Level High 8 Bits",
557 RK312x_PGAL_AGC_MIN_H,
558 0, 255, 0),
559 SOC_SINGLE("PGAL AGC Min Level Low 8 Bits",
560 RK312x_PGAL_AGC_MIN_L,
561 0, 255, 0),
562
563 SOC_SINGLE_TLV("PGAL AGC Max Gain",
564 RK312x_PGAL_AGC_CTL5,
565 RK312x_PGA_AGC_MAX_G_SFT, 7, 0,
566 pga_agc_max_vol_tlv),
567 /* AGC enable and 0x0a bit 5 is 1 */
568 SOC_SINGLE_TLV("PGAL AGC Min Gain", RK312x_PGAL_AGC_CTL5,
569 RK312x_PGA_AGC_MIN_G_SFT, 7, 0, pga_agc_min_vol_tlv),
570 /* AGC enable and 0x0a bit 5 is 1 */
571
572 SOC_ENUM("PGAR AGC Back Way", rk312x_agcr_enum[0]),
573 SOC_ENUM("PGAR AGC Way", rk312x_agcr_enum[1]),
574 SOC_ENUM("PGAR AGC Hold Time", rk312x_agcr_enum[2]),
575 SOC_ENUM("PGAR AGC Ramp Up Time", rk312x_agcr_enum[3]),
576 SOC_ENUM("PGAR AGC Ramp Down Time", rk312x_agcr_enum[4]),
577 SOC_ENUM("PGAR AGC Mode", rk312x_agcr_enum[5]),
578 SOC_ENUM("PGAR AGC Gain Update Zero Enable", rk312x_agcr_enum[6]),
579 SOC_ENUM("PGAR AGC Gain Recovery LPGA VOL", rk312x_agcr_enum[7]),
580 SOC_ENUM("PGAR AGC Fast Decrement Enable", rk312x_agcr_enum[8]),
581 SOC_ENUM("PGAR AGC Noise Gate Enable", rk312x_agcr_enum[9]),
582 SOC_ENUM("PGAR AGC Noise Gate Threhold", rk312x_agcr_enum[10]),
583 SOC_ENUM("PGAR AGC Upate Gain", rk312x_agcr_enum[11]),
584 SOC_ENUM("PGAR AGC Slow Clock Enable", rk312x_agcr_enum[12]),
585 SOC_ENUM("PGAR AGC Approximate Sample Rate", rk312x_agcr_enum[13]),
586 SOC_ENUM("PGAR AGC Enable", rk312x_agcr_enum[14]),
587 /* AGC disable and 0x0a bit 4 is 1 */
588 SOC_SINGLE_TLV("PGAR AGC Volume", RK312x_PGAR_AGC_CTL4,
589 RK312x_PGA_AGC_VOL_SFT, 31, 0, pga_vol_tlv),
590
591 SOC_SINGLE("PGAR AGC Max Level High 8 Bits", RK312x_PGAR_AGC_MAX_H,
592 0, 255, 0),
593 SOC_SINGLE("PGAR AGC Max Level Low 8 Bits", RK312x_PGAR_AGC_MAX_L,
594 0, 255, 0),
595 SOC_SINGLE("PGAR AGC Min Level High 8 Bits", RK312x_PGAR_AGC_MIN_H,
596 0, 255, 0),
597 SOC_SINGLE("PGAR AGC Min Level Low 8 Bits", RK312x_PGAR_AGC_MIN_L,
598 0, 255, 0),
599 /* AGC enable and 0x06 bit 4 is 1 */
600 SOC_SINGLE_TLV("PGAR AGC Max Gain", RK312x_PGAR_AGC_CTL5,
601 RK312x_PGA_AGC_MAX_G_SFT, 7, 0, pga_agc_max_vol_tlv),
602 /* AGC enable and 0x06 bit 4 is 1 */
603 SOC_SINGLE_TLV("PGAR AGC Min Gain", RK312x_PGAR_AGC_CTL5,
604 RK312x_PGA_AGC_MIN_G_SFT, 7, 0, pga_agc_min_vol_tlv),
605
606 };
607
608 /* For tiny alsa playback/capture/voice call path */
609 static const char *const rk312x_playback_path_mode[] = {
610 "OFF", "RCV", "SPK", "HP", "HP_NO_MIC",
611 "BT", "SPK_HP", "RING_SPK", "RING_HP",
612 "RING_HP_NO_MIC", "RING_SPK_HP"};
613
614 static const char *const rk312x_capture_path_mode[] = {
615 "MIC OFF", "Main Mic", "Hands Free Mic", "BT Sco Mic"};
616
617 static const char *const rk312x_voice_call_path_mode[] = {
618 "OFF", "RCV", "SPK", "HP", "HP_NO_MIC", "BT"};
619
620
621 static SOC_ENUM_SINGLE_DECL(rk312x_playback_path_type, 0, 0,
622 rk312x_playback_path_mode);
623 static SOC_ENUM_SINGLE_DECL(rk312x_capture_path_type, 0, 0,
624 rk312x_capture_path_mode);
625 static SOC_ENUM_SINGLE_DECL(rk312x_voice_call_path_type, 0, 0,
626 rk312x_voice_call_path_mode);
627
628
629 /* static int rk312x_codec_power_up(int type); */
630 static int rk312x_codec_power_down(int type);
631
rk312x_codec_mute_dac(int mute)632 int rk312x_codec_mute_dac(int mute)
633 {
634 if (!rk312x_priv) {
635 DBG("%s : rk312x_priv is NULL\n", __func__);
636 return -EINVAL;
637 }
638 if (mute) {
639 snd_soc_component_write(rk312x_priv->component, 0xb4, 0x40);
640 snd_soc_component_write(rk312x_priv->component, 0xb8, 0x40);
641 }
642 return 0;
643 }
644 EXPORT_SYMBOL(rk312x_codec_mute_dac);
645
rk312x_playback_path_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)646 static int rk312x_playback_path_get(struct snd_kcontrol *kcontrol,
647 struct snd_ctl_elem_value *ucontrol)
648 {
649 if (!rk312x_priv) {
650 DBG("%s : rk312x_priv is NULL\n", __func__);
651 return -EINVAL;
652 }
653
654 DBG("%s : playback_path = %ld\n",
655 __func__, ucontrol->value.integer.value[0]);
656
657 ucontrol->value.integer.value[0] = rk312x_priv->playback_path;
658
659 return 0;
660 }
661
rk312x_playback_path_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)662 static int rk312x_playback_path_put(struct snd_kcontrol *kcontrol,
663 struct snd_ctl_elem_value *ucontrol)
664 {
665 long int pre_path;
666
667 if (!rk312x_priv) {
668 DBG("%s : rk312x_priv is NULL\n", __func__);
669 return -EINVAL;
670 }
671
672 if (rk312x_priv->playback_path ==
673 ucontrol->value.integer.value[0]) {
674 DBG("%s : playback_path is not changed!\n", __func__);
675 return 0;
676 }
677
678 pre_path = rk312x_priv->playback_path;
679 rk312x_priv->playback_path = ucontrol->value.integer.value[0];
680
681 DBG("%s : set playback_path = %ld\n", __func__,
682 rk312x_priv->playback_path);
683
684 switch (rk312x_priv->playback_path) {
685 case OFF:
686 if (pre_path != OFF)
687 rk312x_codec_power_down(RK312x_CODEC_PLAYBACK);
688 break;
689 case RCV:
690 break;
691 case SPK_PATH:
692 case RING_SPK:
693 if (pre_path == OFF) {
694 rk312x_codec_power_up(RK312x_CODEC_PLAYBACK);
695 snd_soc_component_write(rk312x_priv->component,
696 0xb4, rk312x_priv->spk_volume);
697 snd_soc_component_write(rk312x_priv->component,
698 0xb8, rk312x_priv->spk_volume);
699 }
700 break;
701 case HP_PATH:
702 case HP_NO_MIC:
703 case RING_HP:
704 case RING_HP_NO_MIC:
705 if (pre_path == OFF) {
706 rk312x_codec_power_up(RK312x_CODEC_PLAYBACK);
707 snd_soc_component_write(rk312x_priv->component,
708 0xb4, rk312x_priv->hp_volume);
709 snd_soc_component_write(rk312x_priv->component,
710 0xb8, rk312x_priv->hp_volume);
711 }
712 break;
713 case BT:
714 break;
715 case SPK_HP:
716 case RING_SPK_HP:
717 if (pre_path == OFF) {
718 rk312x_codec_power_up(RK312x_CODEC_PLAYBACK);
719 snd_soc_component_write(rk312x_priv->component,
720 0xb4, rk312x_priv->spk_volume);
721 snd_soc_component_write(rk312x_priv->component,
722 0xb8, rk312x_priv->spk_volume);
723 }
724 break;
725 default:
726 return -EINVAL;
727 }
728
729 return 0;
730 }
731
rk312x_capture_path_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)732 static int rk312x_capture_path_get(struct snd_kcontrol *kcontrol,
733 struct snd_ctl_elem_value *ucontrol)
734 {
735 if (!rk312x_priv) {
736 DBG("%s : rk312x_priv is NULL\n", __func__);
737 return -EINVAL;
738 }
739
740 DBG("%s : capture_path = %ld\n", __func__,
741 ucontrol->value.integer.value[0]);
742
743 ucontrol->value.integer.value[0] = rk312x_priv->capture_path;
744
745 return 0;
746 }
747
rk312x_capture_path_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)748 static int rk312x_capture_path_put(struct snd_kcontrol *kcontrol,
749 struct snd_ctl_elem_value *ucontrol)
750 {
751 long int pre_path;
752
753 if (!rk312x_priv) {
754 DBG("%s : rk312x_priv is NULL\n", __func__);
755 return -EINVAL;
756 }
757
758 if (rk312x_priv->capture_path == ucontrol->value.integer.value[0])
759 DBG("%s : capture_path is not changed!\n", __func__);
760
761 pre_path = rk312x_priv->capture_path;
762 rk312x_priv->capture_path = ucontrol->value.integer.value[0];
763
764 DBG("%s : set capture_path = %ld\n", __func__,
765 rk312x_priv->capture_path);
766
767 switch (rk312x_priv->capture_path) {
768 case MIC_OFF:
769 if (pre_path != MIC_OFF)
770 rk312x_codec_power_down(RK312x_CODEC_CAPTURE);
771 break;
772 case Main_Mic:
773 if (pre_path == MIC_OFF) {
774 rk312x_codec_power_up(RK312x_CODEC_CAPTURE);
775 snd_soc_component_write(rk312x_priv->component, 0x10c,
776 0x20 | rk312x_priv->capture_volume);
777 snd_soc_component_write(rk312x_priv->component, 0x14c,
778 0x20 | rk312x_priv->capture_volume);
779 }
780 break;
781 case Hands_Free_Mic:
782 if (pre_path == MIC_OFF) {
783 rk312x_codec_power_up(RK312x_CODEC_CAPTURE);
784 snd_soc_component_write(rk312x_priv->component,
785 0x10c, 0x20 | rk312x_priv->capture_volume);
786 snd_soc_component_write(rk312x_priv->component,
787 0x14c, 0x20 | rk312x_priv->capture_volume);
788 }
789 break;
790 case BT_Sco_Mic:
791 break;
792
793 default:
794 return -EINVAL;
795 }
796
797 return 0;
798 }
799
rk312x_voice_call_path_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)800 static int rk312x_voice_call_path_get(struct snd_kcontrol *kcontrol,
801 struct snd_ctl_elem_value *ucontrol)
802 {
803 if (!rk312x_priv) {
804 DBG("%s : rk312x_priv is NULL\n", __func__);
805 return -EINVAL;
806 }
807
808 DBG("%s : playback_path = %ld\n", __func__,
809 ucontrol->value.integer.value[0]);
810
811 ucontrol->value.integer.value[0] = rk312x_priv->voice_call_path;
812
813 return 0;
814 }
815
rk312x_voice_call_path_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)816 static int rk312x_voice_call_path_put(struct snd_kcontrol *kcontrol,
817 struct snd_ctl_elem_value *ucontrol)
818 {
819 long int pre_path;
820
821 if (!rk312x_priv) {
822 DBG("%s : rk312x_priv is NULL\n", __func__);
823 return -EINVAL;
824 }
825
826 if (rk312x_priv->voice_call_path == ucontrol->value.integer.value[0])
827 DBG("%s : playback_path is not changed!\n", __func__);
828
829 pre_path = rk312x_priv->voice_call_path;
830 rk312x_priv->voice_call_path = ucontrol->value.integer.value[0];
831
832 DBG("%s : set playback_path = %ld\n", __func__,
833 rk312x_priv->voice_call_path);
834
835 /* open playback route for incall route and keytone */
836 if (pre_path == OFF) {
837 if (rk312x_priv->playback_path != OFF) {
838 /* mute output for incall route pop nosie */
839 mdelay(100);
840 } else {
841 rk312x_codec_power_up(RK312x_CODEC_PLAYBACK);
842 snd_soc_component_write(rk312x_priv->component,
843 0xb4, rk312x_priv->spk_volume);
844 snd_soc_component_write(rk312x_priv->component,
845 0xb8, rk312x_priv->spk_volume);
846 }
847 }
848
849 switch (rk312x_priv->voice_call_path) {
850 case OFF:
851 if (pre_path != MIC_OFF)
852 rk312x_codec_power_down(RK312x_CODEC_CAPTURE);
853 break;
854 case RCV:
855 break;
856 case SPK_PATH:
857 /* open incall route */
858 if (pre_path == OFF || pre_path == RCV || pre_path == BT)
859 rk312x_codec_power_up(RK312x_CODEC_INCALL);
860
861 break;
862 case HP_PATH:
863 case HP_NO_MIC:
864 /* open incall route */
865 if (pre_path == OFF || pre_path == RCV || pre_path == BT)
866 rk312x_codec_power_up(RK312x_CODEC_INCALL);
867 break;
868 case BT:
869 break;
870 default:
871 return -EINVAL;
872 }
873
874 return 0;
875 }
876
877 static const struct snd_kcontrol_new rk312x_snd_path_controls[] = {
878 SOC_ENUM_EXT("Playback Path", rk312x_playback_path_type,
879 rk312x_playback_path_get, rk312x_playback_path_put),
880 SOC_ENUM_EXT("Capture MIC Path", rk312x_capture_path_type,
881 rk312x_capture_path_get, rk312x_capture_path_put),
882 SOC_ENUM_EXT("Voice Call Path", rk312x_voice_call_path_type,
883 rk312x_voice_call_path_get, rk312x_voice_call_path_put),
884 };
885
rk312x_dacl_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)886 static int rk312x_dacl_event(struct snd_soc_dapm_widget *w,
887 struct snd_kcontrol *kcontrol,
888 int event)
889 {
890 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
891
892 switch (event) {
893 case SND_SOC_DAPM_POST_PMU:
894 snd_soc_component_update_bits(component, RK312x_DAC_ENABLE,
895 RK312x_DACL_WORK, 0);
896 snd_soc_component_update_bits(component, RK312x_DAC_ENABLE,
897 RK312x_DACL_EN | RK312x_DACL_CLK_EN,
898 RK312x_DACL_EN | RK312x_DACL_CLK_EN);
899 snd_soc_component_update_bits(component, RK312x_DAC_ENABLE,
900 RK312x_DACL_WORK, RK312x_DACL_WORK);
901 break;
902
903 case SND_SOC_DAPM_POST_PMD:
904 snd_soc_component_update_bits(component, RK312x_DAC_ENABLE,
905 RK312x_DACL_EN | RK312x_DACL_CLK_EN, 0);
906 snd_soc_component_update_bits(component, RK312x_DAC_ENABLE,
907 RK312x_DACL_WORK, 0);
908 break;
909
910 default:
911 return 0;
912 }
913
914 return 0;
915 }
916
rk312x_dacr_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)917 static int rk312x_dacr_event(struct snd_soc_dapm_widget *w,
918 struct snd_kcontrol *kcontrol,
919 int event)
920 {
921 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
922
923 switch (event) {
924 case SND_SOC_DAPM_POST_PMU:
925 snd_soc_component_update_bits(component, RK312x_DAC_ENABLE,
926 RK312x_DACR_WORK, 0);
927 snd_soc_component_update_bits(component, RK312x_DAC_ENABLE,
928 RK312x_DACR_EN
929 | RK312x_DACR_CLK_EN,
930 RK312x_DACR_EN
931 | RK312x_DACR_CLK_EN);
932 snd_soc_component_update_bits(component, RK312x_DAC_ENABLE,
933 RK312x_DACR_WORK,
934 RK312x_DACR_WORK);
935 break;
936
937 case SND_SOC_DAPM_POST_PMD:
938 snd_soc_component_update_bits(component, RK312x_DAC_ENABLE,
939 RK312x_DACR_EN
940 | RK312x_DACR_CLK_EN, 0);
941 snd_soc_component_update_bits(component, RK312x_DAC_ENABLE,
942 RK312x_DACR_WORK, 0);
943 break;
944
945 default:
946 return 0;
947 }
948
949 return 0;
950 }
951
rk312x_adcl_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)952 static int rk312x_adcl_event(struct snd_soc_dapm_widget *w,
953 struct snd_kcontrol *kcontrol, int event)
954 {
955 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
956
957 switch (event) {
958 case SND_SOC_DAPM_POST_PMU:
959 snd_soc_component_update_bits(component, RK312x_ADC_ENABLE,
960 RK312x_ADCL_CLK_EN_SFT
961 | RK312x_ADCL_AMP_EN_SFT,
962 RK312x_ADCL_CLK_EN
963 | RK312x_ADCL_AMP_EN);
964 break;
965
966 case SND_SOC_DAPM_POST_PMD:
967 snd_soc_component_update_bits(component, RK312x_ADC_ENABLE,
968 RK312x_ADCL_CLK_EN_SFT
969 | RK312x_ADCL_AMP_EN_SFT, 0);
970 break;
971
972 default:
973 return 0;
974 }
975
976 return 0;
977 }
978
rk312x_adcr_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)979 static int rk312x_adcr_event(struct snd_soc_dapm_widget *w,
980 struct snd_kcontrol *kcontrol, int event)
981 {
982 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
983
984 switch (event) {
985 case SND_SOC_DAPM_POST_PMU:
986 snd_soc_component_update_bits(component, RK312x_ADC_ENABLE,
987 RK312x_ADCR_CLK_EN_SFT
988 | RK312x_ADCR_AMP_EN_SFT,
989 RK312x_ADCR_CLK_EN
990 | RK312x_ADCR_AMP_EN);
991 break;
992
993 case SND_SOC_DAPM_POST_PMD:
994 snd_soc_component_update_bits(component, RK312x_ADC_ENABLE,
995 RK312x_ADCR_CLK_EN_SFT
996 | RK312x_ADCR_AMP_EN_SFT, 0);
997 break;
998
999 default:
1000 return 0;
1001 }
1002
1003 return 0;
1004 }
1005
1006 /* HPmix */
1007 static const struct snd_kcontrol_new rk312x_hpmixl[] = {
1008 SOC_DAPM_SINGLE("ALCR Switch", RK312x_HPMIX_S_SELECT,
1009 RK312x_HPMIXL_SEL_ALCR_SFT, 1, 0),
1010 SOC_DAPM_SINGLE("ALCL Switch", RK312x_HPMIX_S_SELECT,
1011 RK312x_HPMIXL_SEL_ALCL_SFT, 1, 0),
1012 SOC_DAPM_SINGLE("DACL Switch", RK312x_HPMIX_S_SELECT,
1013 RK312x_HPMIXL_SEL_DACL_SFT, 1, 0),
1014 };
1015
1016 static const struct snd_kcontrol_new rk312x_hpmixr[] = {
1017 SOC_DAPM_SINGLE("ALCR Switch", RK312x_HPMIX_S_SELECT,
1018 RK312x_HPMIXR_SEL_ALCR_SFT, 1, 0),
1019 SOC_DAPM_SINGLE("ALCL Switch", RK312x_HPMIX_S_SELECT,
1020 RK312x_HPMIXR_SEL_ALCL_SFT, 1, 0),
1021 SOC_DAPM_SINGLE("DACR Switch", RK312x_HPMIX_S_SELECT,
1022 RK312x_HPMIXR_SEL_DACR_SFT, 1, 0),
1023 };
1024
rk312x_hpmixl_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1025 static int rk312x_hpmixl_event(struct snd_soc_dapm_widget *w,
1026 struct snd_kcontrol *kcontrol, int event)
1027 {
1028 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1029
1030 switch (event) {
1031 case SND_SOC_DAPM_POST_PMU:
1032 snd_soc_component_update_bits(component, RK312x_DAC_CTL,
1033 RK312x_ZO_DET_VOUTR_SFT,
1034 RK312x_ZO_DET_VOUTR_EN);
1035 snd_soc_component_update_bits(component, RK312x_DAC_CTL,
1036 RK312x_ZO_DET_VOUTL_SFT,
1037 RK312x_ZO_DET_VOUTL_EN);
1038 break;
1039
1040 case SND_SOC_DAPM_PRE_PMD:
1041 snd_soc_component_update_bits(component, RK312x_DAC_CTL,
1042 RK312x_ZO_DET_VOUTR_SFT,
1043 RK312x_ZO_DET_VOUTR_DIS);
1044 snd_soc_component_update_bits(component, RK312x_DAC_CTL,
1045 RK312x_ZO_DET_VOUTL_SFT,
1046 RK312x_ZO_DET_VOUTL_DIS);
1047 break;
1048
1049 default:
1050 return 0;
1051 }
1052
1053 return 0;
1054 }
1055
rk312x_hpmixr_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1056 static int rk312x_hpmixr_event(struct snd_soc_dapm_widget *w,
1057 struct snd_kcontrol *kcontrol, int event)
1058 {
1059 #if 0
1060 switch (event) {
1061 case SND_SOC_DAPM_POST_PMU:
1062 snd_soc_component_update_bits(component, RK312x_HPMIX_CTL,
1063 RK312x_HPMIXR_WORK2, RK312x_HPMIXR_WORK2);
1064 break;
1065
1066 case SND_SOC_DAPM_PRE_PMD:
1067 snd_soc_component_update_bits(component, RK312x_HPMIX_CTL,
1068 RK312x_HPMIXR_WORK2, 0);
1069 break;
1070
1071 default:
1072 return 0;
1073 }
1074 #endif
1075 return 0;
1076 }
1077
1078 /* HP MUX */
1079
1080 static const char *const hpl_sel[] = {"HPMIXL", "DACL"};
1081
1082 static const struct soc_enum hpl_sel_enum =
1083 SOC_ENUM_SINGLE(RK312x_HPMIX_S_SELECT, RK312x_HPMIXL_BYPASS_SFT,
1084 ARRAY_SIZE(hpl_sel), hpl_sel);
1085
1086 static const struct snd_kcontrol_new hpl_sel_mux =
1087 SOC_DAPM_ENUM("HPL select Mux", hpl_sel_enum);
1088
1089 static const char *const hpr_sel[] = {"HPMIXR", "DACR"};
1090
1091 static const struct soc_enum hpr_sel_enum =
1092 SOC_ENUM_SINGLE(RK312x_HPMIX_S_SELECT, RK312x_HPMIXR_BYPASS_SFT,
1093 ARRAY_SIZE(hpr_sel), hpr_sel);
1094
1095 static const struct snd_kcontrol_new hpr_sel_mux =
1096 SOC_DAPM_ENUM("HPR select Mux", hpr_sel_enum);
1097
1098 /* IN_L MUX */
1099 static const char *const lnl_sel[] = {"NO", "BSTL", "LINEL", "NOUSE"};
1100
1101 static const struct soc_enum lnl_sel_enum =
1102 SOC_ENUM_SINGLE(RK312x_ALC_MUNIN_CTL, RK312x_MUXINL_F_SHT,
1103 ARRAY_SIZE(lnl_sel), lnl_sel);
1104
1105 static const struct snd_kcontrol_new lnl_sel_mux =
1106 SOC_DAPM_ENUM("MUXIN_L select", lnl_sel_enum);
1107
1108 /* IN_R MUX */
1109 static const char *const lnr_sel[] = {"NO", "BSTR", "LINER", "NOUSE"};
1110
1111 static const struct soc_enum lnr_sel_enum =
1112 SOC_ENUM_SINGLE(RK312x_ALC_MUNIN_CTL, RK312x_MUXINR_F_SHT,
1113 ARRAY_SIZE(lnr_sel), lnr_sel);
1114
1115 static const struct snd_kcontrol_new lnr_sel_mux =
1116 SOC_DAPM_ENUM("MUXIN_R select", lnr_sel_enum);
1117
1118
1119 static const struct snd_soc_dapm_widget rk312x_dapm_widgets[] = {
1120 /* microphone bias */
1121 SND_SOC_DAPM_MICBIAS("Mic Bias", RK312x_ADC_MIC_CTL,
1122 RK312x_MICBIAS_VOL_ENABLE, 0),
1123
1124 /* DACs */
1125 SND_SOC_DAPM_DAC_E("DACL", NULL, SND_SOC_NOPM,
1126 0, 0, rk312x_dacl_event,
1127 SND_SOC_DAPM_POST_PMD
1128 | SND_SOC_DAPM_POST_PMU),
1129 SND_SOC_DAPM_DAC_E("DACR", NULL, SND_SOC_NOPM,
1130 0, 0, rk312x_dacr_event,
1131 SND_SOC_DAPM_POST_PMD
1132 | SND_SOC_DAPM_POST_PMU),
1133
1134 /* ADCs */
1135 SND_SOC_DAPM_ADC_E("ADCL", NULL, SND_SOC_NOPM,
1136 0, 0, rk312x_adcl_event,
1137 SND_SOC_DAPM_POST_PMD
1138 | SND_SOC_DAPM_POST_PMU),
1139 SND_SOC_DAPM_ADC_E("ADCR", NULL, SND_SOC_NOPM,
1140 0, 0, rk312x_adcr_event,
1141 SND_SOC_DAPM_POST_PMD
1142 | SND_SOC_DAPM_POST_PMU),
1143
1144 /* PGA */
1145 SND_SOC_DAPM_PGA("BSTL", RK312x_BST_CTL,
1146 RK312x_BSTL_PWRD_SFT, 0, NULL, 0),
1147 SND_SOC_DAPM_PGA("BSTR", RK312x_BST_CTL,
1148 RK312x_BSTR_PWRD_SFT, 0, NULL, 0),
1149 SND_SOC_DAPM_PGA("ALCL", RK312x_ALC_MUNIN_CTL,
1150 RK312x_ALCL_PWR_SHT , 0, NULL, 0),
1151 SND_SOC_DAPM_PGA("ALCR", RK312x_ALC_MUNIN_CTL,
1152 RK312x_ALCR_PWR_SHT , 0, NULL, 0),
1153 SND_SOC_DAPM_PGA("HPL", RK312x_HPOUT_CTL,
1154 RK312x_HPOUTL_PWR_SHT, 0, NULL, 0),
1155 SND_SOC_DAPM_PGA("HPR", RK312x_HPOUT_CTL,
1156 RK312x_HPOUTR_PWR_SHT, 0, NULL, 0),
1157
1158 /* MIXER */
1159 SND_SOC_DAPM_MIXER_E("HPMIXL", RK312x_HPMIX_CTL,
1160 RK312x_HPMIXL_SFT, 0,
1161 rk312x_hpmixl,
1162 ARRAY_SIZE(rk312x_hpmixl),
1163 rk312x_hpmixl_event,
1164 SND_SOC_DAPM_PRE_PMD
1165 | SND_SOC_DAPM_POST_PMU),
1166 SND_SOC_DAPM_MIXER_E("HPMIXR", RK312x_HPMIX_CTL,
1167 RK312x_HPMIXR_SFT, 0,
1168 rk312x_hpmixr,
1169 ARRAY_SIZE(rk312x_hpmixr),
1170 rk312x_hpmixr_event,
1171 SND_SOC_DAPM_PRE_PMD
1172 | SND_SOC_DAPM_POST_PMU),
1173
1174 /* MUX */
1175 SND_SOC_DAPM_MUX("IN_R Mux", SND_SOC_NOPM, 0, 0,
1176 &lnr_sel_mux),
1177 SND_SOC_DAPM_MUX("IN_L Mux", SND_SOC_NOPM, 0, 0,
1178 &lnl_sel_mux),
1179 SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0,
1180 &hpl_sel_mux),
1181 SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0,
1182 &hpr_sel_mux),
1183
1184 /* Audio Interface */
1185 SND_SOC_DAPM_AIF_IN("I2S DAC", "HiFi Playback", 0,
1186 SND_SOC_NOPM, 0, 0),
1187 SND_SOC_DAPM_AIF_OUT("I2S ADC", "HiFi Capture", 0,
1188 SND_SOC_NOPM, 0, 0),
1189
1190 /* Input */
1191 SND_SOC_DAPM_INPUT("LINEL"),
1192 SND_SOC_DAPM_INPUT("LINER"),
1193 SND_SOC_DAPM_INPUT("MICP"),
1194 SND_SOC_DAPM_INPUT("MICN"),
1195
1196 /* Output */
1197 SND_SOC_DAPM_OUTPUT("HPOUTL"),
1198 SND_SOC_DAPM_OUTPUT("HPOUTR"),
1199
1200 };
1201
1202 static const struct snd_soc_dapm_route rk312x_dapm_routes[] = {
1203 /* Input */
1204 {"BSTR", NULL, "MICP"},
1205 {"BSTL", NULL, "MICP"},
1206 {"BSTL", NULL, "MICN"},
1207
1208 {"IN_R Mux", "LINER", "LINER"},
1209 {"IN_R Mux", "BSTR", "BSTR"},
1210 {"IN_L Mux", "LINEL", "LINEL"},
1211 {"IN_L Mux", "BSTL", "BSTL"},
1212
1213 {"ALCL", NULL, "IN_L Mux"},
1214 {"ALCR", NULL, "IN_R Mux"},
1215
1216
1217 {"ADCR", NULL, "ALCR"},
1218 {"ADCL", NULL, "ALCL"},
1219
1220 {"I2S ADC", NULL, "ADCR"},
1221 {"I2S ADC", NULL, "ADCL"},
1222
1223 /* Output */
1224
1225 {"DACR", NULL, "I2S DAC"},
1226 {"DACL", NULL, "I2S DAC"},
1227
1228 {"HPMIXR", "ALCR Switch", "ALCR"},
1229 {"HPMIXR", "ALCL Switch", "ALCL"},
1230 {"HPMIXR", "DACR Switch", "DACR"},
1231
1232 {"HPMIXL", "ALCR Switch", "ALCR"},
1233 {"HPMIXL", "ALCL Switch", "ALCL"},
1234 {"HPMIXL", "DACL Switch", "DACL"},
1235
1236
1237 {"HPR Mux", "DACR", "DACR"},
1238 {"HPR Mux", "HPMIXR", "HPMIXR"},
1239 {"HPL Mux", "DACL", "DACL"},
1240 {"HPL Mux", "HPMIXL", "HPMIXL"},
1241
1242 {"HPR", NULL, "HPR Mux"},
1243 {"HPL", NULL, "HPL Mux"},
1244
1245 {"HPOUTR", NULL, "HPR"},
1246 {"HPOUTL", NULL, "HPL"},
1247 };
1248
rk312x_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)1249 static int rk312x_set_bias_level(struct snd_soc_component *component,
1250 enum snd_soc_bias_level level)
1251 {
1252 DBG("%s level=%d\n", __func__, level);
1253
1254 switch (level) {
1255 case SND_SOC_BIAS_ON:
1256 break;
1257
1258 case SND_SOC_BIAS_PREPARE:
1259 break;
1260
1261 case SND_SOC_BIAS_STANDBY:
1262 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1263 regmap_write(rk312x_priv->regmap, RK312x_DAC_INT_CTL3, 0x32);
1264 snd_soc_component_update_bits(component, RK312x_ADC_MIC_CTL,
1265 RK312x_ADC_CURRENT_ENABLE,
1266 RK312x_ADC_CURRENT_ENABLE);
1267 snd_soc_component_update_bits(component, RK312x_DAC_CTL,
1268 RK312x_CURRENT_EN,
1269 RK312x_CURRENT_EN);
1270 /* set power */
1271 snd_soc_component_update_bits(component, RK312x_ADC_ENABLE,
1272 RK312x_ADCL_REF_VOL_EN_SFT
1273 | RK312x_ADCR_REF_VOL_EN_SFT,
1274 RK312x_ADCL_REF_VOL_EN
1275 | RK312x_ADCR_REF_VOL_EN);
1276
1277 snd_soc_component_update_bits(component, RK312x_ADC_MIC_CTL,
1278 RK312x_ADCL_ZERO_DET_EN_SFT
1279 | RK312x_ADCR_ZERO_DET_EN_SFT,
1280 RK312x_ADCL_ZERO_DET_EN
1281 | RK312x_ADCR_ZERO_DET_EN);
1282
1283 snd_soc_component_update_bits(component, RK312x_DAC_CTL,
1284 RK312x_REF_VOL_DACL_EN_SFT
1285 | RK312x_REF_VOL_DACR_EN_SFT,
1286 RK312x_REF_VOL_DACL_EN
1287 | RK312x_REF_VOL_DACR_EN);
1288
1289 snd_soc_component_update_bits(component, RK312x_DAC_ENABLE,
1290 RK312x_DACL_REF_VOL_EN_SFT
1291 | RK312x_DACR_REF_VOL_EN_SFT,
1292 RK312x_DACL_REF_VOL_EN
1293 | RK312x_DACR_REF_VOL_EN);
1294 }
1295 break;
1296
1297 case SND_SOC_BIAS_OFF:
1298 snd_soc_component_update_bits(component, RK312x_DAC_ENABLE,
1299 RK312x_DACL_REF_VOL_EN_SFT
1300 | RK312x_DACR_REF_VOL_EN_SFT, 0);
1301 snd_soc_component_update_bits(component, RK312x_DAC_CTL,
1302 RK312x_REF_VOL_DACL_EN_SFT
1303 | RK312x_REF_VOL_DACR_EN_SFT, 0);
1304 snd_soc_component_update_bits(component, RK312x_ADC_MIC_CTL,
1305 RK312x_ADCL_ZERO_DET_EN_SFT
1306 | RK312x_ADCR_ZERO_DET_EN_SFT, 0);
1307 snd_soc_component_update_bits(component, RK312x_ADC_ENABLE,
1308 RK312x_ADCL_REF_VOL_EN_SFT
1309 | RK312x_ADCR_REF_VOL_EN_SFT, 0);
1310 snd_soc_component_update_bits(component, RK312x_ADC_MIC_CTL,
1311 RK312x_ADC_CURRENT_ENABLE, 0);
1312 snd_soc_component_update_bits(component, RK312x_DAC_CTL,
1313 RK312x_CURRENT_EN, 0);
1314 regmap_write(rk312x_priv->regmap, RK312x_DAC_INT_CTL3, 0x22);
1315 break;
1316 }
1317
1318 return 0;
1319 }
1320
rk312x_set_dai_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)1321 static int rk312x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1322 int clk_id, unsigned int freq, int dir)
1323 {
1324 struct rk312x_codec_priv *rk312x = rk312x_priv;
1325
1326 if (!rk312x) {
1327 DBG("%s : rk312x is NULL\n", __func__);
1328 return -EINVAL;
1329 }
1330
1331 rk312x->stereo_sysclk = freq;
1332
1333 return 0;
1334 }
1335
rk312x_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)1336 static int rk312x_set_dai_fmt(struct snd_soc_dai *codec_dai,
1337 unsigned int fmt)
1338 {
1339 struct snd_soc_component *component = codec_dai->component;
1340 unsigned int adc_aif1 = 0, adc_aif2 = 0, dac_aif1 = 0, dac_aif2 = 0;
1341
1342 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1343 case SND_SOC_DAIFMT_CBS_CFS:
1344 adc_aif2 |= RK312x_I2S_MODE_SLV;
1345 break;
1346 case SND_SOC_DAIFMT_CBM_CFM:
1347 adc_aif2 |= RK312x_I2S_MODE_MST;
1348 break;
1349 default:
1350 DBG("%s : set master mask failed!\n", __func__);
1351 return -EINVAL;
1352 }
1353
1354 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1355 case SND_SOC_DAIFMT_DSP_A:
1356 adc_aif1 |= RK312x_ADC_DF_PCM;
1357 dac_aif1 |= RK312x_DAC_DF_PCM;
1358 break;
1359 case SND_SOC_DAIFMT_DSP_B:
1360 break;
1361 case SND_SOC_DAIFMT_I2S:
1362 adc_aif1 |= RK312x_ADC_DF_I2S;
1363 dac_aif1 |= RK312x_DAC_DF_I2S;
1364 break;
1365 case SND_SOC_DAIFMT_RIGHT_J:
1366 adc_aif1 |= RK312x_ADC_DF_RJ;
1367 dac_aif1 |= RK312x_DAC_DF_RJ;
1368 break;
1369 case SND_SOC_DAIFMT_LEFT_J:
1370 adc_aif1 |= RK312x_ADC_DF_LJ;
1371 dac_aif1 |= RK312x_DAC_DF_LJ;
1372 break;
1373 default:
1374 DBG("%s : set format failed!\n", __func__);
1375 return -EINVAL;
1376 }
1377
1378 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1379 case SND_SOC_DAIFMT_NB_NF:
1380 adc_aif1 |= RK312x_ALRCK_POL_DIS;
1381 adc_aif2 |= RK312x_ABCLK_POL_DIS;
1382 dac_aif1 |= RK312x_DLRCK_POL_DIS;
1383 dac_aif2 |= RK312x_DBCLK_POL_DIS;
1384 break;
1385 case SND_SOC_DAIFMT_IB_IF:
1386 adc_aif1 |= RK312x_ALRCK_POL_EN;
1387 adc_aif2 |= RK312x_ABCLK_POL_EN;
1388 dac_aif1 |= RK312x_DLRCK_POL_EN;
1389 dac_aif2 |= RK312x_DBCLK_POL_EN;
1390 break;
1391 case SND_SOC_DAIFMT_IB_NF:
1392 adc_aif1 |= RK312x_ALRCK_POL_DIS;
1393 adc_aif2 |= RK312x_ABCLK_POL_EN;
1394 dac_aif1 |= RK312x_DLRCK_POL_DIS;
1395 dac_aif2 |= RK312x_DBCLK_POL_EN;
1396 break;
1397 case SND_SOC_DAIFMT_NB_IF:
1398 adc_aif1 |= RK312x_ALRCK_POL_EN;
1399 adc_aif2 |= RK312x_ABCLK_POL_DIS;
1400 dac_aif1 |= RK312x_DLRCK_POL_EN;
1401 dac_aif2 |= RK312x_DBCLK_POL_DIS;
1402 break;
1403 default:
1404 DBG("%s : set dai format failed!\n", __func__);
1405 return -EINVAL;
1406 }
1407
1408 snd_soc_component_update_bits(component, RK312x_ADC_INT_CTL1,
1409 RK312x_ALRCK_POL_MASK
1410 | RK312x_ADC_DF_MASK, adc_aif1);
1411 snd_soc_component_update_bits(component, RK312x_ADC_INT_CTL2,
1412 RK312x_ABCLK_POL_MASK
1413 | RK312x_I2S_MODE_MASK, adc_aif2);
1414 snd_soc_component_update_bits(component, RK312x_DAC_INT_CTL1,
1415 RK312x_DLRCK_POL_MASK
1416 | RK312x_DAC_DF_MASK, dac_aif1);
1417 snd_soc_component_update_bits(component, RK312x_DAC_INT_CTL2,
1418 RK312x_DBCLK_POL_MASK, dac_aif2);
1419
1420 return 0;
1421 }
1422
rk312x_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1423 static int rk312x_hw_params(struct snd_pcm_substream *substream,
1424 struct snd_pcm_hw_params *params,
1425 struct snd_soc_dai *dai)
1426 {
1427 struct snd_soc_component *component = dai->component;
1428 struct rk312x_codec_priv *rk312x = rk312x_priv;
1429 unsigned int rate = params_rate(params);
1430 unsigned int div;
1431 unsigned int adc_aif1 = 0, adc_aif2 = 0, dac_aif1 = 0, dac_aif2 = 0;
1432
1433 if (!rk312x) {
1434 DBG("%s : rk312x is NULL\n", __func__);
1435 return -EINVAL;
1436 }
1437
1438 /* bclk = codec_clk / 4 */
1439 /* lrck = bclk / (wl * 2) */
1440 div = (((rk312x->stereo_sysclk / 4) / rate) / 2);
1441
1442 if ((rk312x->stereo_sysclk % (4 * rate * 2) > 0) ||
1443 (div != 16 && div != 20 && div != 24 && div != 32)) {
1444 DBG("%s : need PLL\n", __func__);
1445 return -EINVAL;
1446 }
1447
1448 switch (div) {
1449 case 16:
1450 adc_aif2 |= RK312x_ADC_WL_16;
1451 dac_aif2 |= RK312x_DAC_WL_16;
1452 break;
1453 case 20:
1454 adc_aif2 |= RK312x_ADC_WL_20;
1455 dac_aif2 |= RK312x_DAC_WL_20;
1456 break;
1457 case 24:
1458 adc_aif2 |= RK312x_ADC_WL_24;
1459 dac_aif2 |= RK312x_DAC_WL_24;
1460 break;
1461 case 32:
1462 adc_aif2 |= RK312x_ADC_WL_32;
1463 dac_aif2 |= RK312x_DAC_WL_32;
1464 break;
1465 default:
1466 return -EINVAL;
1467 }
1468
1469
1470 DBG("%s : MCLK = %dHz, sample rate = %dHz, div = %d\n",
1471 __func__, rk312x->stereo_sysclk, rate, div);
1472
1473 switch (params_format(params)) {
1474 case SNDRV_PCM_FORMAT_S16_LE:
1475 adc_aif1 |= RK312x_ADC_VWL_16;
1476 dac_aif1 |= RK312x_DAC_VWL_16;
1477 break;
1478 case SNDRV_PCM_FORMAT_S20_3LE:
1479 adc_aif1 |= RK312x_ADC_VWL_20;
1480 dac_aif1 |= RK312x_DAC_VWL_20;
1481 break;
1482 case SNDRV_PCM_FORMAT_S24_LE:
1483 adc_aif1 |= RK312x_ADC_VWL_24;
1484 dac_aif1 |= RK312x_DAC_VWL_24;
1485 break;
1486 case SNDRV_PCM_FORMAT_S32_LE:
1487 adc_aif1 |= RK312x_ADC_VWL_32;
1488 dac_aif1 |= RK312x_DAC_VWL_32;
1489 break;
1490 default:
1491 return -EINVAL;
1492 }
1493
1494 switch (params_channels(params)) {
1495 case RK312x_MONO:
1496 adc_aif1 |= RK312x_ADC_TYPE_MONO;
1497 DBG("mono\n");
1498 break;
1499 case RK312x_STEREO:
1500 adc_aif1 |= RK312x_ADC_TYPE_STEREO;
1501 DBG("stero\n");
1502 break;
1503 default:
1504 return -EINVAL;
1505 }
1506
1507 adc_aif1 |= RK312x_ADC_SWAP_DIS;
1508 adc_aif2 |= RK312x_ADC_RST_DIS;
1509 dac_aif1 |= RK312x_DAC_SWAP_DIS;
1510 dac_aif2 |= RK312x_DAC_RST_DIS;
1511
1512 rk312x->rate = rate;
1513
1514 snd_soc_component_update_bits(component, RK312x_ADC_INT_CTL1,
1515 RK312x_ADC_VWL_MASK
1516 | RK312x_ADC_SWAP_MASK
1517 | RK312x_ADC_TYPE_MASK, adc_aif1);
1518 snd_soc_component_update_bits(component, RK312x_ADC_INT_CTL2,
1519 RK312x_ADC_WL_MASK
1520 | RK312x_ADC_RST_MASK, adc_aif2);
1521 snd_soc_component_update_bits(component, RK312x_DAC_INT_CTL1,
1522 RK312x_DAC_VWL_MASK
1523 | RK312x_DAC_SWAP_MASK, dac_aif1);
1524 snd_soc_component_update_bits(component, RK312x_DAC_INT_CTL2,
1525 RK312x_DAC_WL_MASK
1526 | RK312x_DAC_RST_MASK, dac_aif2);
1527
1528 return 0;
1529 }
1530
rk312x_codec_unpop(struct work_struct * work)1531 static void rk312x_codec_unpop(struct work_struct *work)
1532 {
1533 rk312x_codec_ctl_gpio(CODEC_SET_SPK, 1);
1534 }
1535
rk312x_digital_mute(struct snd_soc_dai * dai,int mute,int stream)1536 static int rk312x_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
1537 {
1538
1539 if (mute) {
1540 rk312x_codec_ctl_gpio(CODEC_SET_SPK, 0);
1541 rk312x_codec_ctl_gpio(CODEC_SET_HP, 0);
1542 } else {
1543 if (!rk312x_priv->rk312x_for_mid) {
1544 schedule_delayed_work(&rk312x_priv->mute_delayed_work,
1545 msecs_to_jiffies(rk312x_priv->spk_mute_delay));
1546 } else {
1547 switch (rk312x_priv->playback_path) {
1548 case SPK_PATH:
1549 case RING_SPK:
1550 rk312x_codec_ctl_gpio(CODEC_SET_SPK, 1);
1551 rk312x_codec_ctl_gpio(CODEC_SET_HP, 0);
1552 break;
1553 case HP_PATH:
1554 case HP_NO_MIC:
1555 case RING_HP:
1556 case RING_HP_NO_MIC:
1557 rk312x_codec_ctl_gpio(CODEC_SET_SPK, 0);
1558 rk312x_codec_ctl_gpio(CODEC_SET_HP, 1);
1559 break;
1560 case SPK_HP:
1561 case RING_SPK_HP:
1562 rk312x_codec_ctl_gpio(CODEC_SET_SPK, 1);
1563 rk312x_codec_ctl_gpio(CODEC_SET_HP, 1);
1564 break;
1565 default:
1566 break;
1567 }
1568 }
1569 }
1570 return 0;
1571 }
1572
1573 static struct rk312x_reg_val_typ playback_power_up_list[] = {
1574 {0x18, 0x32},
1575 {0xa0, 0x40|0x08},
1576 {0xa0, 0x62|0x08},
1577
1578 {0xb4, 0x80},
1579 {0xb8, 0x80},
1580 {0xa8, 0x44},
1581 {0xa8, 0x55},
1582
1583 {0xb0, 0x90},
1584 {0xb0, 0xd8},
1585
1586 {0xa4, 0x88},
1587 {0xa4, 0xcc},
1588 {0xa4, 0xee},
1589 {0xa4, 0xff},
1590
1591 {0xac, 0x11}, /*DAC*/
1592 {0xa8, 0x77},
1593 {0xb0, 0xfc},
1594
1595 {0xb4, OUT_VOLUME},
1596 {0xb8, OUT_VOLUME},
1597 {0xb0, 0xff},
1598 {0xa0, 0x73|0x08},
1599 };
1600 #define RK312x_CODEC_PLAYBACK_POWER_UP_LIST_LEN ARRAY_SIZE( \
1601 playback_power_up_list)
1602
1603 static struct rk312x_reg_val_typ playback_power_down_list[] = {
1604 {0xb0, 0xdb},
1605 {0xa8, 0x44},
1606 {0xac, 0x00},
1607 {0xb0, 0x92},
1608 {0xa0, 0x22|0x08},
1609 {0xb0, 0x00},
1610 {0xa8, 0x00},
1611 {0xa4, 0x00},
1612 {0xa0, 0x00|0x08},
1613 {0x18, 0x22},
1614 #ifdef WITH_CAP
1615 /* {0xbc, 0x08},*/
1616 #endif
1617 {0xb4, 0x0},
1618 {0xb8, 0x0},
1619 {0x18, 0x22},
1620 };
1621 #define RK312x_CODEC_PLAYBACK_POWER_DOWN_LIST_LEN ARRAY_SIZE( \
1622 playback_power_down_list)
1623
1624 static struct rk312x_reg_val_typ capture_power_up_list[] = {
1625 {0x88, 0x80},
1626 {0x88, 0xc0},
1627 {0x88, 0xc7},
1628 {0x9c, 0x88},
1629 {0x8c, 0x04},
1630 {0x90, 0x66},
1631 {0x9c, 0xcc},
1632 {0x9c, 0xee},
1633 {0x8c, 0x07},
1634 {0x90, 0x77},
1635 {0x94, 0x20 | CAP_VOL},
1636 {0x98, CAP_VOL},
1637 {0x88, 0xf7},
1638 {0x28, 0x3c},
1639 /* {0x124, 0x78}, */
1640 /* {0x164, 0x78}, */
1641 {0x10c, 0x20 | CAP_VOL},
1642 {0x14c, 0x20 | CAP_VOL},
1643 /*close left channel*/
1644 {0x90, 0x07},
1645 {0x88, 0xd7},
1646 {0x8c, 0x07},
1647 {0x9c, 0x0e},
1648
1649 };
1650 #define RK312x_CODEC_CAPTURE_POWER_UP_LIST_LEN ARRAY_SIZE(capture_power_up_list)
1651
1652 static struct rk312x_reg_val_typ capture_power_down_list[] = {
1653 {0x9c, 0xcc},
1654 {0x90, 0x66},
1655 {0x8c, 0x44},
1656 {0x9c, 0x88},
1657 {0x88, 0xc7},
1658 {0x88, 0xc0},
1659 {0x88, 0x80},
1660 {0x8c, 0x00},
1661 {0X94, 0x0c},
1662 {0X98, 0x0c},
1663 {0x9c, 0x00},
1664 {0x88, 0x00},
1665 {0x90, 0x44},
1666 {0x28, 0x0c},
1667 {0x10c, 0x2c},
1668 {0x14c, 0x2c},
1669 /* {0x124, 0x38}, */
1670 /* {0x164, 0x38}, */
1671 };
1672 #define RK312x_CODEC_CAPTURE_POWER_DOWN_LIST_LEN ARRAY_SIZE(\
1673 capture_power_down_list)
1674
rk312x_codec_power_up(int type)1675 static int rk312x_codec_power_up(int type)
1676 {
1677 struct snd_soc_component *component;
1678 int i;
1679
1680 if (!rk312x_priv || !rk312x_priv->component) {
1681 DBG("%s : rk312x_priv or rk312x_priv->codec is NULL\n",
1682 __func__);
1683 return -EINVAL;
1684 }
1685 component = rk312x_priv->component;
1686
1687 DBG("%s : power up %s%s\n", __func__,
1688 type == RK312x_CODEC_PLAYBACK ? "playback" : "",
1689 type == RK312x_CODEC_CAPTURE ? "capture" : "");
1690
1691 if (type == RK312x_CODEC_PLAYBACK) {
1692 for (i = 0; i < RK312x_CODEC_PLAYBACK_POWER_UP_LIST_LEN; i++) {
1693 snd_soc_component_write(component,
1694 playback_power_up_list[i].reg,
1695 playback_power_up_list[i].value);
1696 usleep_range(1000, 1100);
1697 }
1698 } else if (type == RK312x_CODEC_CAPTURE) {
1699 if (rk312x_priv->rk312x_for_mid == 1) {
1700 for (i = 0;
1701 i < RK312x_CODEC_CAPTURE_POWER_UP_LIST_LEN;
1702 i++) {
1703 snd_soc_component_write(component,
1704 capture_power_up_list[i].reg,
1705 capture_power_up_list[i].value);
1706 }
1707 } else {
1708 for (i = 0;
1709 i < RK312x_CODEC_CAPTURE_POWER_UP_LIST_LEN - 4;
1710 i++) {
1711 snd_soc_component_write(component,
1712 capture_power_up_list[i].reg,
1713 capture_power_up_list[i].value);
1714 }
1715 }
1716 } else if (type == RK312x_CODEC_INCALL) {
1717 snd_soc_component_update_bits(component, RK312x_ALC_MUNIN_CTL,
1718 RK312x_MUXINL_F_MSK | RK312x_MUXINR_F_MSK,
1719 RK312x_MUXINR_F_INR | RK312x_MUXINL_F_INL);
1720 }
1721
1722 return 0;
1723 }
1724
rk312x_codec_power_down(int type)1725 static int rk312x_codec_power_down(int type)
1726 {
1727 struct snd_soc_component *component;
1728 int i;
1729
1730 if (!rk312x_priv || !rk312x_priv->component) {
1731 DBG("%s : rk312x_priv or rk312x_priv->component is NULL\n",
1732 __func__);
1733 return -EINVAL;
1734 }
1735 component = rk312x_priv->component;
1736
1737 DBG("%s : power down %s%s%s\n", __func__,
1738 type == RK312x_CODEC_PLAYBACK ? "playback" : "",
1739 type == RK312x_CODEC_CAPTURE ? "capture" : "",
1740 type == RK312x_CODEC_ALL ? "all" : "");
1741
1742 if ((type == RK312x_CODEC_CAPTURE) || (type == RK312x_CODEC_INCALL)) {
1743 for (i = 0; i < RK312x_CODEC_CAPTURE_POWER_DOWN_LIST_LEN; i++) {
1744 snd_soc_component_write(component,
1745 capture_power_down_list[i].reg,
1746 capture_power_down_list[i].value);
1747 }
1748 } else if (type == RK312x_CODEC_PLAYBACK) {
1749 for (i = 0;
1750 i < RK312x_CODEC_PLAYBACK_POWER_DOWN_LIST_LEN;
1751 i++) {
1752 snd_soc_component_write(component,
1753 playback_power_down_list[i].reg,
1754 playback_power_down_list[i].value);
1755 }
1756
1757 } else if (type == RK312x_CODEC_ALL) {
1758 rk312x_reset(component);
1759 }
1760
1761 return 0;
1762 }
1763
rk312x_codec_capture_work(struct work_struct * work)1764 static void rk312x_codec_capture_work(struct work_struct *work)
1765 {
1766 DBG("%s : rk312x_codec_work_capture_type = %d\n", __func__,
1767 rk312x_codec_work_capture_type);
1768
1769 switch (rk312x_codec_work_capture_type) {
1770 case RK312x_CODEC_WORK_POWER_DOWN:
1771 rk312x_codec_power_down(RK312x_CODEC_CAPTURE);
1772 break;
1773 case RK312x_CODEC_WORK_POWER_UP:
1774 rk312x_codec_power_up(RK312x_CODEC_CAPTURE);
1775 snd_soc_component_write(rk312x_priv->component,
1776 0x10c, 0x20 | rk312x_priv->capture_volume);
1777 snd_soc_component_write(rk312x_priv->component,
1778 0x14c, 0x20 | rk312x_priv->capture_volume);
1779 break;
1780 default:
1781 break;
1782 }
1783
1784 rk312x_codec_work_capture_type = RK312x_CODEC_WORK_NULL;
1785 }
1786
rk312x_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1787 static int rk312x_startup(struct snd_pcm_substream *substream,
1788 struct snd_soc_dai *dai)
1789 {
1790 struct rk312x_codec_priv *rk312x = rk312x_priv;
1791 bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
1792 bool is_codec_playback_running;
1793 bool is_codec_capture_running;
1794
1795 if (rk312x_priv->rk312x_for_mid) {
1796 return 0;
1797 }
1798 if (!rk312x) {
1799 DBG("%s : rk312x is NULL\n", __func__);
1800 return -EINVAL;
1801 }
1802 is_codec_playback_running = rk312x->playback_active > 0;
1803 is_codec_capture_running = rk312x->capture_active > 0;
1804
1805 if (playback)
1806 rk312x->playback_active++;
1807 else
1808 rk312x->capture_active++;
1809
1810 if (playback) {
1811 if (rk312x->playback_active > 0)
1812 if (!is_codec_playback_running) {
1813 rk312x_codec_power_up(RK312x_CODEC_PLAYBACK);
1814 snd_soc_component_write(rk312x_priv->component,
1815 0xb4, rk312x_priv->spk_volume);
1816 snd_soc_component_write(rk312x_priv->component,
1817 0xb8, rk312x_priv->spk_volume);
1818 }
1819 } else {
1820 if (rk312x->capture_active > 0 && !is_codec_capture_running) {
1821 if (rk312x_codec_work_capture_type != RK312x_CODEC_WORK_POWER_UP) {
1822 //cancel_delayed_work_sync(&capture_delayed_work);
1823 if (rk312x_codec_work_capture_type == RK312x_CODEC_WORK_NULL)
1824 rk312x_codec_power_up(RK312x_CODEC_CAPTURE);
1825 else
1826 rk312x_codec_work_capture_type = RK312x_CODEC_WORK_NULL;
1827 }
1828 }
1829 }
1830
1831 return 0;
1832 }
1833
rk312x_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1834 static void rk312x_shutdown(struct snd_pcm_substream *substream,
1835 struct snd_soc_dai *dai)
1836 {
1837 struct rk312x_codec_priv *rk312x = rk312x_priv;
1838 bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
1839 bool is_codec_playback_running;
1840 bool is_codec_capture_running;
1841
1842 if (rk312x_priv->rk312x_for_mid) {
1843 return;
1844 }
1845
1846 if (!rk312x) {
1847 DBG("%s : rk312x is NULL\n", __func__);
1848 return;
1849 }
1850 is_codec_playback_running = rk312x->playback_active > 0;
1851 is_codec_capture_running = rk312x->capture_active > 0;
1852
1853 if (playback)
1854 rk312x->playback_active--;
1855 else
1856 rk312x->capture_active--;
1857
1858 if (playback) {
1859 if (rk312x->playback_active <= 0) {
1860 if (is_codec_playback_running)
1861 rk312x_codec_power_down(
1862 RK312x_CODEC_PLAYBACK);
1863 else
1864 DBG(" Warning:playback closed! return !\n");
1865 }
1866 } else {
1867 if (rk312x->capture_active <= 0) {
1868 if ((rk312x_codec_work_capture_type !=
1869 RK312x_CODEC_WORK_POWER_DOWN) &&
1870 is_codec_capture_running) {
1871 cancel_delayed_work_sync(&capture_delayed_work);
1872 /*
1873 * If rk312x_codec_work_capture_type is NULL
1874 * means codec already power down,
1875 * so power up codec.
1876 * If rk312x_codec_work_capture_type is
1877 * RK312x_CODEC_WORK_POWER_UP it means
1878 * codec haven't be powered up, so we don't
1879 * need to power down codec.
1880 * If is playback call power down,
1881 * power down immediatly, because audioflinger
1882 * already has delay 3s.
1883 */
1884 if (rk312x_codec_work_capture_type ==
1885 RK312x_CODEC_WORK_NULL) {
1886 rk312x_codec_work_capture_type =
1887 RK312x_CODEC_WORK_POWER_DOWN;
1888 queue_delayed_work(rk312x_codec_workq,
1889 &capture_delayed_work,
1890 msecs_to_jiffies(3000));
1891 } else {
1892 rk312x_codec_work_capture_type =
1893 RK312x_CODEC_WORK_NULL;
1894 }
1895 }
1896 }
1897 }
1898 }
1899
1900 #define RK312x_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1901 SNDRV_PCM_RATE_16000 | \
1902 SNDRV_PCM_RATE_32000 | \
1903 SNDRV_PCM_RATE_44100 | \
1904 SNDRV_PCM_RATE_48000 | \
1905 SNDRV_PCM_RATE_96000 | \
1906 SNDRV_PCM_RATE_192000)
1907
1908 #define RK312x_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1909 SNDRV_PCM_RATE_16000 | \
1910 SNDRV_PCM_RATE_32000 | \
1911 SNDRV_PCM_RATE_44100 | \
1912 SNDRV_PCM_RATE_48000 | \
1913 SNDRV_PCM_RATE_96000)
1914
1915 #define RK312x_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1916 SNDRV_PCM_FMTBIT_S20_3LE |\
1917 SNDRV_PCM_FMTBIT_S24_LE |\
1918 SNDRV_PCM_FMTBIT_S32_LE)
1919
1920 static struct snd_soc_dai_ops rk312x_dai_ops = {
1921 .hw_params = rk312x_hw_params,
1922 .set_fmt = rk312x_set_dai_fmt,
1923 .set_sysclk = rk312x_set_dai_sysclk,
1924 .mute_stream = rk312x_digital_mute,
1925 .startup = rk312x_startup,
1926 .shutdown = rk312x_shutdown,
1927 .no_capture_mute = 1,
1928 };
1929
1930 static struct snd_soc_dai_driver rk312x_dai[] = {
1931 {
1932 .name = "rk312x-hifi",
1933 .id = RK312x_HIFI,
1934 .playback = {
1935 .stream_name = "HiFi Playback",
1936 .channels_min = 2,
1937 .channels_max = 2,
1938 .rates = RK312x_PLAYBACK_RATES,
1939 .formats = RK312x_FORMATS,
1940 },
1941 .capture = {
1942 .stream_name = "HiFi Capture",
1943 .channels_min = 2,
1944 .channels_max = 2,
1945 .rates = RK312x_CAPTURE_RATES,
1946 .formats = RK312x_FORMATS,
1947 },
1948 .ops = &rk312x_dai_ops,
1949 },
1950 {
1951 .name = "rk312x-voice",
1952 .id = RK312x_VOICE,
1953 .playback = {
1954 .stream_name = "Voice Playback",
1955 .channels_min = 1,
1956 .channels_max = 2,
1957 .rates = RK312x_PLAYBACK_RATES,
1958 .formats = RK312x_FORMATS,
1959 },
1960 .capture = {
1961 .stream_name = "Voice Capture",
1962 .channels_min = 1,
1963 .channels_max = 2,
1964 .rates = RK312x_CAPTURE_RATES,
1965 .formats = RK312x_FORMATS,
1966 },
1967 .ops = &rk312x_dai_ops,
1968 },
1969
1970 };
1971
rk312x_suspend(struct snd_soc_component * component)1972 static int rk312x_suspend(struct snd_soc_component *component)
1973 {
1974 unsigned int val=0;
1975 DBG("%s\n", __func__);
1976 if (rk312x_priv->codec_hp_det) {
1977 /* disable hp det interrupt */
1978 regmap_read(rk312x_priv->grf, GRF_ACODEC_CON, &val);
1979 regmap_write(rk312x_priv->grf, GRF_ACODEC_CON, 0x1f0013);
1980 regmap_read(rk312x_priv->grf, GRF_ACODEC_CON, &val);
1981 cancel_delayed_work_sync(&rk312x_priv->hpdet_work);
1982
1983 }
1984 if (rk312x_priv->rk312x_for_mid) {
1985 cancel_delayed_work_sync(&capture_delayed_work);
1986
1987 if (rk312x_codec_work_capture_type != RK312x_CODEC_WORK_NULL)
1988 rk312x_codec_work_capture_type = RK312x_CODEC_WORK_NULL;
1989
1990 rk312x_codec_power_down(RK312x_CODEC_PLAYBACK);
1991 rk312x_codec_power_down(RK312x_CODEC_ALL);
1992 snd_soc_component_write(component, RK312x_SELECT_CURRENT, 0x1e);
1993 snd_soc_component_write(component, RK312x_SELECT_CURRENT, 0x3e);
1994 } else {
1995 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
1996 }
1997 return 0;
1998 }
1999
gpio_show(struct kobject * kobj,struct kobj_attribute * attr,char * buf)2000 static ssize_t gpio_show(struct kobject *kobj, struct kobj_attribute *attr,
2001 char *buf)
2002 {
2003 return 0;
2004 }
2005
gpio_store(struct kobject * kobj,struct kobj_attribute * attr,const char * buf,size_t n)2006 static ssize_t gpio_store(struct kobject *kobj, struct kobj_attribute *attr,
2007 const char *buf, size_t n)
2008 {
2009 const char *buftmp = buf;
2010 char cmd;
2011 int ret;
2012 struct rk312x_codec_priv *rk312x =
2013 snd_soc_component_get_drvdata(rk312x_priv->component);
2014
2015 ret = sscanf(buftmp, "%c ", &cmd);
2016 if (ret == 0)
2017 return ret;
2018 switch (cmd) {
2019 case 'd':
2020 if (rk312x->spk_ctl_gpio) {
2021 gpiod_set_value(rk312x->spk_ctl_gpio, 0);
2022 DBG(KERN_INFO"%s : spk gpio disable\n",__func__);
2023 }
2024
2025 if (rk312x->hp_ctl_gpio) {
2026 gpiod_set_value(rk312x->hp_ctl_gpio, 0);
2027 DBG(KERN_INFO"%s : disable hp gpio \n",__func__);
2028 }
2029 break;
2030 case 'e':
2031 if (rk312x->spk_ctl_gpio) {
2032 gpiod_set_value(rk312x->spk_ctl_gpio, 1);
2033 DBG(KERN_INFO"%s : spk gpio enable\n",__func__);
2034 }
2035
2036 if (rk312x->hp_ctl_gpio) {
2037 gpiod_set_value(rk312x->hp_ctl_gpio, 1);
2038 DBG("%s : enable hp gpio \n",__func__);
2039 }
2040 break;
2041 default:
2042 DBG(KERN_ERR"--rk312x codec %s-- unknown cmd\n", __func__);
2043 break;
2044 }
2045 return n;
2046 }
2047 static struct kobject *gpio_kobj;
2048 struct gpio_attribute {
2049
2050 struct attribute attr;
2051
2052 ssize_t (*show)(struct kobject *kobj, struct kobj_attribute *attr,
2053 char *buf);
2054 ssize_t (*store)(struct kobject *kobj, struct kobj_attribute *attr,
2055 const char *buf, size_t n);
2056 };
2057
2058 static struct gpio_attribute gpio_attrs[] = {
2059 /* node_name permision show_func store_func */
2060 __ATTR(spk-ctl, S_IRUGO | S_IWUSR, gpio_show, gpio_store),
2061 };
2062
rk312x_resume(struct snd_soc_component * component)2063 static int rk312x_resume(struct snd_soc_component *component)
2064 {
2065 unsigned int val = 0;
2066
2067 if (rk312x_priv->codec_hp_det) {
2068 /* enable hp det interrupt */
2069 snd_soc_component_write(component, RK312x_DAC_CTL, 0x08);
2070 val = snd_soc_component_read(component, RK312x_DAC_CTL);
2071 printk("0xa0 -- 0x%x\n", val);
2072 regmap_read(rk312x_priv->grf, GRF_ACODEC_CON, &val);
2073 regmap_write(rk312x_priv->grf, GRF_ACODEC_CON, 0x1f001f);
2074 regmap_read(rk312x_priv->grf, GRF_ACODEC_CON, &val);
2075 printk("GRF_ACODEC_CON is 0x%x\n", val);
2076 schedule_delayed_work(&rk312x_priv->hpdet_work, msecs_to_jiffies(20));
2077 }
2078 if (!rk312x_priv->rk312x_for_mid)
2079 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
2080
2081 return 0;
2082 }
2083
codec_hp_det_isr(int irq,void * data)2084 static irqreturn_t codec_hp_det_isr(int irq, void *data)
2085 {
2086 unsigned int val = 0;
2087 regmap_read(rk312x_priv->grf, GRF_ACODEC_CON, &val);
2088 DBG("%s GRF_ACODEC_CON -- 0x%x\n", __func__, val);
2089 if (val & 0x1) {
2090 DBG("%s hp det rising\n", __func__);
2091 regmap_write(rk312x_priv->grf, GRF_ACODEC_CON, val | 0x10001);
2092 } else if (val & 0x2) {
2093 DBG("%s hp det falling\n", __func__);
2094 regmap_write(rk312x_priv->grf, GRF_ACODEC_CON, val | 0x20002);
2095 }
2096 cancel_delayed_work(&rk312x_priv->hpdet_work);
2097 schedule_delayed_work(&rk312x_priv->hpdet_work, msecs_to_jiffies(20));
2098 return IRQ_HANDLED;
2099 }
hpdet_work_func(struct work_struct * work)2100 static void hpdet_work_func(struct work_struct *work)
2101 {
2102 unsigned int val = 0;
2103
2104 regmap_read(rk312x_priv->grf, GRF_SOC_STATUS0, &val);
2105 DBG("%s GRF_SOC_STATUS0 -- 0x%x\n", __func__, val);
2106 if (val & 0x80000000) {
2107 DBG("%s hp det high\n", __func__);
2108 DBG("%s no headset\n", __func__);
2109 extcon_set_state_sync(rk312x_priv->edev,
2110 EXTCON_JACK_HEADPHONE, false);
2111 } else {
2112 DBG("%s hp det low\n", __func__);
2113 DBG("%s headset inserted\n", __func__);
2114 extcon_set_state_sync(rk312x_priv->edev,
2115 EXTCON_JACK_HEADPHONE, true);
2116 }
2117 return;
2118 }
2119
rk312x_delay_workq(struct work_struct * work)2120 static void rk312x_delay_workq(struct work_struct *work)
2121 {
2122
2123 int ret;
2124 unsigned int val;
2125 struct rk312x_codec_priv *rk312x_codec;
2126 struct snd_soc_component *component;
2127
2128 printk("%s\n", __func__);
2129 if (!rk312x_priv || !rk312x_priv->component) {
2130 DBG("%s : rk312x_priv or rk312x_priv->component is NULL\n",
2131 __func__);
2132 return;
2133 }
2134 rk312x_codec = snd_soc_component_get_drvdata(rk312x_priv->component);
2135 component = rk312x_codec->component;
2136 rk312x_reset(component);
2137 if (!rk312x_priv->rk312x_for_mid) {
2138 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
2139 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
2140 }
2141 #ifdef WITH_CAP
2142 snd_soc_component_write(component, RK312x_SELECT_CURRENT, 0x1e);
2143 snd_soc_component_write(component, RK312x_SELECT_CURRENT, 0x3e);
2144 #endif
2145
2146 if (rk312x_codec->codec_hp_det) {
2147 /*init codec_hp_det interrupt only for rk3128 */
2148 ret = devm_request_irq(rk312x_priv->dev, rk312x_priv->irq, codec_hp_det_isr,
2149 IRQF_TRIGGER_RISING, "codec_hp_det", NULL);
2150 if (ret < 0)
2151 DBG(" codec_hp_det request_irq failed %d\n", ret);
2152
2153 regmap_read(rk312x_priv->grf, GRF_ACODEC_CON, &val);
2154 regmap_write(rk312x_priv->grf, GRF_ACODEC_CON, 0x1f001f);
2155 regmap_read(rk312x_priv->grf, GRF_ACODEC_CON, &val);
2156 DBG("GRF_ACODEC_CON 3334is 0x%x\n", val);
2157 /* enable rk 3128 codec_hp_det */
2158 snd_soc_component_write(component, RK312x_DAC_CTL, 0x08);
2159 val = snd_soc_component_read(component, RK312x_DAC_CTL);
2160 DBG("0xa0 -- 0x%x\n", val);
2161 /* codec hp det once */
2162 schedule_delayed_work(&rk312x_priv->hpdet_work, msecs_to_jiffies(100));
2163 }
2164
2165
2166 }
rk312x_probe(struct snd_soc_component * component)2167 static int rk312x_probe(struct snd_soc_component *component)
2168 {
2169 struct rk312x_codec_priv *rk312x_codec =
2170 snd_soc_component_get_drvdata(component);
2171 unsigned int val;
2172 int ret;
2173 int i = 0;
2174
2175 rk312x_codec->component = component;
2176 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
2177 clk_prepare_enable(rk312x_codec->pclk);
2178
2179 rk312x_codec->playback_active = 0;
2180 rk312x_codec->capture_active = 0;
2181
2182 rk312x_codec_workq = create_freezable_workqueue("rk312x-codec");
2183
2184 if (rk312x_codec_workq == NULL) {
2185 DBG("%s : rk312x_codec_workq is NULL!\n", __func__);
2186 ret = -ENOMEM;
2187 goto err__;
2188 }
2189
2190 val = snd_soc_component_read(component, RK312x_RESET);
2191
2192 if (val != rk312x_reg_defaults[RK312x_RESET]) {
2193 DBG("%s : codec register 0: %x is not a 0x00000003\n",
2194 __func__, val);
2195 ret = -ENODEV;
2196 goto err__;
2197 }
2198
2199 snd_soc_add_component_controls(component, rk312x_snd_path_controls,
2200 ARRAY_SIZE(rk312x_snd_path_controls));
2201 INIT_DELAYED_WORK(&rk312x_priv->init_delayed_work, rk312x_delay_workq);
2202 INIT_DELAYED_WORK(&rk312x_priv->mute_delayed_work, rk312x_codec_unpop);
2203 INIT_DELAYED_WORK(&rk312x_priv->hpdet_work, hpdet_work_func);
2204
2205 schedule_delayed_work(&rk312x_priv->init_delayed_work, msecs_to_jiffies(3000));
2206 if (rk312x_codec->gpio_debug) {
2207 gpio_kobj = kobject_create_and_add("codec-spk-ctl", NULL);
2208
2209 if (!gpio_kobj)
2210 return -ENOMEM;
2211 for (i = 0; i < ARRAY_SIZE(gpio_attrs); i++) {
2212 ret = sysfs_create_file(gpio_kobj, &gpio_attrs[i].attr);
2213 if (ret != 0) {
2214 DBG(KERN_ERR"create codec-spk-ctl sysfs %d error\n", i);
2215 /* return ret; */
2216 }
2217 }
2218 }
2219 return 0;
2220
2221 err__:
2222 dbg_codec(2, "%s err ret=%d\n", __func__, ret);
2223 return ret;
2224 }
2225
2226 /* power down chip */
rk312x_remove(struct snd_soc_component * component)2227 static void rk312x_remove(struct snd_soc_component *component)
2228 {
2229
2230 DBG("%s\n", __func__);
2231 if (!rk312x_priv) {
2232 DBG("%s : rk312x_priv is NULL\n", __func__);
2233 return;
2234 }
2235
2236 if (rk312x_priv->spk_ctl_gpio)
2237 gpiod_set_value(rk312x_priv->spk_ctl_gpio, 0);
2238
2239 if (rk312x_priv->hp_ctl_gpio)
2240 gpiod_set_value(rk312x_priv->hp_ctl_gpio, 0);
2241
2242 mdelay(10);
2243
2244 if (rk312x_priv->rk312x_for_mid) {
2245 cancel_delayed_work_sync(&capture_delayed_work);
2246
2247 if (rk312x_codec_work_capture_type != RK312x_CODEC_WORK_NULL)
2248 rk312x_codec_work_capture_type = RK312x_CODEC_WORK_NULL;
2249 }
2250 snd_soc_component_write(component, RK312x_RESET, 0xfc);
2251 mdelay(10);
2252 snd_soc_component_write(component, RK312x_RESET, 0x3);
2253 mdelay(10);
2254 }
2255
2256
2257 static struct snd_soc_component_driver soc_codec_dev_rk312x = {
2258 .probe = rk312x_probe,
2259 .remove = rk312x_remove,
2260 .suspend = rk312x_suspend,
2261 .resume = rk312x_resume,
2262 .set_bias_level = rk312x_set_bias_level,
2263 };
2264
2265 static const struct regmap_config rk312x_codec_regmap_config = {
2266 .reg_bits = 32,
2267 .reg_stride = 4,
2268 .val_bits = 32,
2269 .max_register = RK312x_PGAR_AGC_CTL5,
2270 .writeable_reg = rk312x_codec_register,
2271 .readable_reg = rk312x_codec_register,
2272 .volatile_reg = rk312x_volatile_register,
2273 };
2274
2275 #define GRF_SOC_CON0 0x00140
2276 #define GRF_ACODEC_SEL (BIT(10) | BIT(16 + 10))
2277
rk312x_platform_probe(struct platform_device * pdev)2278 static int rk312x_platform_probe(struct platform_device *pdev)
2279 {
2280 struct device_node *rk312x_np = pdev->dev.of_node;
2281 struct rk312x_codec_priv *rk312x;
2282 struct resource *res;
2283 int ret;
2284
2285 rk312x = devm_kzalloc(&pdev->dev, sizeof(*rk312x), GFP_KERNEL);
2286 if (!rk312x) {
2287 dbg_codec(2, "%s : rk312x priv kzalloc failed!\n",
2288 __func__);
2289 return -ENOMEM;
2290 }
2291 rk312x_priv = rk312x;
2292 platform_set_drvdata(pdev, rk312x);
2293 rk312x->dev = &pdev->dev;
2294
2295 #if 0
2296 rk312x->spk_hp_switch_gpio = of_get_named_gpio_flags(rk312x_np,
2297 "spk_hp_switch_gpio", 0, &rk312x->spk_io);
2298 rk312x->spk_io = !rk312x->spk_io;
2299 if (!gpio_is_valid(rk312x->spk_hp_switch_gpio)) {
2300 dbg_codec(2, "invalid spk hp switch_gpio : %d\n",
2301 rk312x->spk_hp_switch_gpio);
2302 rk312x->spk_hp_switch_gpio = INVALID_GPIO;
2303 /* ret = -ENOENT; */
2304 /* goto err__; */
2305 }
2306 DBG("%s : spk_hp_switch_gpio %d spk active_level %d \n", __func__,
2307 rk312x->spk_hp_switch_gpio, rk312x->spk_io);
2308
2309 if(rk312x->spk_hp_switch_gpio != INVALID_GPIO) {
2310 ret = devm_gpio_request(&pdev->dev, rk312x->spk_hp_switch_gpio, "spk_hp_switch");
2311 if (ret < 0) {
2312 dbg_codec(2, "rk312x_platform_probe spk_hp_switch_gpio fail\n");
2313 /* goto err__; */
2314 rk312x->spk_hp_switch_gpio = INVALID_GPIO;
2315 }
2316 }
2317 #endif
2318 rk312x->edev = devm_extcon_dev_allocate(&pdev->dev, headset_extcon_cable);
2319 if (IS_ERR(rk312x->edev)) {
2320 dev_err(&pdev->dev, "failed to allocate extcon device\n");
2321 return -ENOMEM;
2322 }
2323
2324 ret = devm_extcon_dev_register(&pdev->dev, rk312x->edev);
2325 if (ret < 0) {
2326 dev_err(&pdev->dev, "failed to register extcon device\n");
2327 return ret;
2328 }
2329
2330 rk312x->hp_ctl_gpio = devm_gpiod_get_optional(&pdev->dev, "hp-ctl",
2331 GPIOD_OUT_LOW);
2332 if (!IS_ERR_OR_NULL(rk312x->hp_ctl_gpio)) {
2333 DBG("%s : hp-ctl-gpio %d\n", __func__,
2334 desc_to_gpio(rk312x->hp_ctl_gpio));
2335 }
2336
2337 rk312x->spk_ctl_gpio = devm_gpiod_get_optional(&pdev->dev, "spk-ctl",
2338 GPIOD_OUT_LOW);
2339 if (!IS_ERR_OR_NULL(rk312x->spk_ctl_gpio)) {
2340 DBG(KERN_INFO "%s : spk-ctl-gpio %d\n", __func__,
2341 desc_to_gpio(rk312x->spk_ctl_gpio));
2342 }
2343
2344 ret = of_property_read_u32(rk312x_np, "spk-mute-delay",
2345 &rk312x->spk_mute_delay);
2346 if (ret < 0) {
2347 DBG(KERN_ERR "%s() Can not read property spk-mute-delay\n",
2348 __func__);
2349 rk312x->spk_mute_delay = 0;
2350 }
2351
2352 ret = of_property_read_u32(rk312x_np, "hp-mute-delay",
2353 &rk312x->hp_mute_delay);
2354 if (ret < 0) {
2355 DBG(KERN_ERR"%s() Can not read property hp-mute-delay\n",
2356 __func__);
2357 rk312x->hp_mute_delay = 0;
2358 }
2359 DBG("spk mute delay %dms --- hp mute delay %dms\n",rk312x->spk_mute_delay,rk312x->hp_mute_delay);
2360
2361 ret = of_property_read_u32(rk312x_np, "rk312x_for_mid",
2362 &rk312x->rk312x_for_mid);
2363 if (ret < 0) {
2364 DBG(KERN_ERR"%s() Can not read property rk312x_for_mid, default for mid\n",
2365 __func__);
2366 rk312x->rk312x_for_mid = 1;
2367 }
2368 ret = of_property_read_u32(rk312x_np, "is_rk3128",
2369 &rk312x->is_rk3128);
2370 if (ret < 0) {
2371 DBG(KERN_ERR"%s() Can not read property is_rk3128, default rk3126\n",
2372 __func__);
2373 rk312x->is_rk3128 = 0;
2374 }
2375 ret = of_property_read_u32(rk312x_np, "spk_volume",
2376 &rk312x->spk_volume);
2377 if (ret < 0) {
2378 DBG(KERN_ERR"%s() Can not read property spk_volume, default 25\n",
2379 __func__);
2380 rk312x->spk_volume = 25;
2381 }
2382 ret = of_property_read_u32(rk312x_np, "hp_volume",
2383 &rk312x->hp_volume);
2384 if (ret < 0) {
2385 DBG(KERN_ERR"%s() Can not read property hp_volume, default 25\n",
2386 __func__);
2387 rk312x->hp_volume = 25;
2388 }
2389 ret = of_property_read_u32(rk312x_np, "capture_volume",
2390 &rk312x->capture_volume);
2391 if (ret < 0) {
2392 DBG(KERN_ERR"%s() Can not read property capture_volume, default 26\n",
2393 __func__);
2394 rk312x->capture_volume = 26;
2395 }
2396 ret = of_property_read_u32(rk312x_np, "gpio_debug", &rk312x->gpio_debug);
2397 if (ret < 0) {
2398 DBG(KERN_ERR"%s() Can not read property gpio_debug\n", __func__);
2399 rk312x->gpio_debug = 0;
2400 }
2401 ret = of_property_read_u32(rk312x_np, "codec_hp_det", &rk312x->codec_hp_det);
2402
2403 if (ret < 0) {
2404 DBG(KERN_ERR"%s() Can not read property gpio_debug\n", __func__);
2405 rk312x->codec_hp_det = 0;
2406 }
2407
2408 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2409 rk312x->regbase = devm_ioremap_resource(&pdev->dev, res);
2410 if (IS_ERR(rk312x->regbase))
2411 return PTR_ERR(rk312x->regbase);
2412 rk312x->regmap = devm_regmap_init_mmio(&pdev->dev, rk312x->regbase,
2413 &rk312x_codec_regmap_config);
2414 if (IS_ERR(rk312x->regmap))
2415 return PTR_ERR(rk312x->regmap);
2416
2417 rk312x->grf = syscon_regmap_lookup_by_phandle(rk312x_np, "rockchip,grf");
2418 if (IS_ERR(rk312x->grf)) {
2419 dev_err(&pdev->dev, "needs 'rockchip,grf' property\n");
2420 return PTR_ERR(rk312x->grf);
2421 }
2422 ret = regmap_write(rk312x->grf, GRF_SOC_CON0, GRF_ACODEC_SEL);
2423 if (ret) {
2424 dev_err(&pdev->dev, "Could not write to GRF: %d\n", ret);
2425 return ret;
2426 }
2427
2428 if (rk312x->codec_hp_det)
2429 rk312x->irq = platform_get_irq(pdev, 0);
2430
2431 rk312x->pclk = devm_clk_get(&pdev->dev, "g_pclk_acodec");
2432 if (IS_ERR(rk312x->pclk)) {
2433 dev_err(&pdev->dev, "Unable to get acodec pclk\n");
2434 ret = -ENXIO;
2435 goto err__;
2436 }
2437 rk312x->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
2438 if (IS_ERR(rk312x->mclk)) {
2439 dev_err(&pdev->dev, "Unable to get mclk\n");
2440 ret = -ENXIO;
2441 goto err__;
2442 }
2443
2444 clk_prepare_enable(rk312x->mclk);
2445 clk_set_rate(rk312x->mclk, 11289600);
2446
2447 return devm_snd_soc_register_component(&pdev->dev, &soc_codec_dev_rk312x,
2448 rk312x_dai, ARRAY_SIZE(rk312x_dai));
2449
2450 err__:
2451 platform_set_drvdata(pdev, NULL);
2452 rk312x_priv = NULL;
2453 return ret;
2454 }
2455
rk312x_platform_remove(struct platform_device * pdev)2456 static int rk312x_platform_remove(struct platform_device *pdev)
2457 {
2458 DBG("%s\n", __func__);
2459 rk312x_priv = NULL;
2460 return 0;
2461 }
2462
rk312x_platform_shutdown(struct platform_device * pdev)2463 void rk312x_platform_shutdown(struct platform_device *pdev)
2464 {
2465 unsigned int val = 0;
2466 DBG("%s\n", __func__);
2467 if (!rk312x_priv || !rk312x_priv->component) {
2468 DBG("%s : rk312x_priv or rk312x_priv->component is NULL\n",
2469 __func__);
2470 return;
2471 }
2472 if (rk312x_priv->codec_hp_det) {
2473 /* disable hp det interrupt */
2474 regmap_read(rk312x_priv->grf, GRF_ACODEC_CON, &val);
2475 regmap_write(rk312x_priv->grf, GRF_ACODEC_CON, 0x1f0013);
2476 regmap_read(rk312x_priv->grf, GRF_ACODEC_CON, &val);
2477 DBG("disable codec_hp_det GRF_ACODEC_CON is 0x%x\n", val);
2478 cancel_delayed_work_sync(&rk312x_priv->hpdet_work);
2479 }
2480
2481 if (rk312x_priv->spk_ctl_gpio)
2482 gpiod_set_value(rk312x_priv->spk_ctl_gpio, 0);
2483
2484 if (rk312x_priv->hp_ctl_gpio)
2485 gpiod_set_value(rk312x_priv->hp_ctl_gpio, 0);
2486
2487 mdelay(10);
2488
2489 if (rk312x_priv->rk312x_for_mid) {
2490 cancel_delayed_work_sync(&capture_delayed_work);
2491 if (rk312x_codec_work_capture_type !=
2492 RK312x_CODEC_WORK_NULL)
2493 rk312x_codec_work_capture_type =
2494 RK312x_CODEC_WORK_NULL;
2495 }
2496
2497 regmap_write(rk312x_priv->regmap, RK312x_RESET, 0xfc);
2498 mdelay(10);
2499 regmap_write(rk312x_priv->regmap, RK312x_RESET, 0x03);
2500
2501 }
2502
2503 #ifdef CONFIG_OF
2504 static const struct of_device_id rk312x_codec_of_match[] = {
2505 { .compatible = "rockchip,rk3128-codec" },
2506 {},
2507 };
2508 MODULE_DEVICE_TABLE(of, rk312x_codec_of_match);
2509 #endif
2510
2511 static struct platform_driver rk312x_codec_driver = {
2512 .driver = {
2513 .name = "rk312x-codec",
2514 .of_match_table = of_match_ptr(rk312x_codec_of_match),
2515 },
2516 .probe = rk312x_platform_probe,
2517 .remove = rk312x_platform_remove,
2518 .shutdown = rk312x_platform_shutdown,
2519 };
2520 module_platform_driver(rk312x_codec_driver);
2521
2522 /* Module information */
2523 MODULE_AUTHOR("rockchip");
2524 MODULE_DESCRIPTION("ROCKCHIP i2s ASoC Interface");
2525 MODULE_LICENSE("GPL");
2526