1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Driver of Inno codec for rk3036 by Rockchip Inc.
4 *
5 * Author: Rockchip Inc.
6 * Author: Zheng ShunQian<zhengsq@rock-chips.com>
7 */
8
9 #include <sound/soc.h>
10 #include <sound/tlv.h>
11 #include <sound/soc-dapm.h>
12 #include <sound/soc-dai.h>
13 #include <sound/pcm.h>
14 #include <sound/pcm_params.h>
15
16 #include <linux/platform_device.h>
17 #include <linux/of.h>
18 #include <linux/of_gpio.h>
19 #include <linux/clk.h>
20 #include <linux/regmap.h>
21 #include <linux/device.h>
22 #include <linux/mfd/syscon.h>
23 #include <linux/module.h>
24 #include <linux/io.h>
25
26 #include "inno_rk3036.h"
27
28 struct rk3036_codec_priv {
29 void __iomem *base;
30 struct clk *pclk;
31 struct regmap *regmap;
32 struct device *dev;
33 struct gpio_desc *pa_ctl;
34 };
35
36 static const DECLARE_TLV_DB_MINMAX(rk3036_codec_hp_tlv, -39, 0);
37
rk3036_codec_antipop_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)38 static int rk3036_codec_antipop_event(struct snd_soc_dapm_widget *w,
39 struct snd_kcontrol *kcontrol, int event)
40 {
41 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
42 int val, ret, regmsk;
43
44 regmsk = INNO_R09_HP_ANTIPOP_MSK << w->shift;
45 switch (event) {
46 case SND_SOC_DAPM_PRE_PMU:
47 val = INNO_R09_HP_ANTIPOP_ON << w->shift;
48 break;
49 case SND_SOC_DAPM_POST_PMD:
50 val = INNO_R09_HP_ANTIPOP_OFF << w->shift;
51 break;
52 default:
53 return 0;
54 }
55
56 ret = snd_soc_component_update_bits(component, INNO_R09,
57 regmsk, val);
58 if (ret < 0)
59 return ret;
60
61 /* Need to wait POP Sound VCM is stable */
62 msleep(50);
63
64 return 0;
65 }
66
67 static const struct snd_kcontrol_new rk3036_codec_dapm_controls[] = {
68 SOC_DOUBLE_R_RANGE_TLV("Headphone Volume", INNO_R07, INNO_R08,
69 INNO_HP_GAIN_SHIFT, INNO_HP_GAIN_N39DB,
70 INNO_HP_GAIN_0DB, 0, rk3036_codec_hp_tlv),
71 SOC_DOUBLE("Zero Cross Switch", INNO_R06, INNO_R06_VOUTL_CZ_SHIFT,
72 INNO_R06_VOUTR_CZ_SHIFT, 1, 0),
73 SOC_DOUBLE("Headphone Switch", INNO_R09, INNO_R09_HPL_MUTE_SHIFT,
74 INNO_R09_HPR_MUTE_SHIFT, 1, 0),
75 };
76
77 static const struct snd_soc_dapm_widget rk3036_codec_dapm_widgets[] = {
78 /* Using S3(Step3) as the starting step by datasheet */
79 SND_SOC_DAPM_SUPPLY_S("DAC PWR", 0, INNO_R06,
80 INNO_R06_DAC_EN_SHIFT, 0, NULL,
81 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
82 SND_SOC_DAPM_SUPPLY_S("DACL VREF", 1, INNO_R04,
83 INNO_R04_DACL_VREF_SHIFT, 0, NULL,
84 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
85 SND_SOC_DAPM_SUPPLY_S("DACR VREF", 1, INNO_R04,
86 INNO_R04_DACR_VREF_SHIFT, 0, NULL,
87 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
88 SND_SOC_DAPM_SUPPLY_S("DACL ANTI-POP", 2, SND_SOC_NOPM,
89 INNO_R09_HPL_ANITPOP_SHIFT, 0, rk3036_codec_antipop_event,
90 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
91 SND_SOC_DAPM_SUPPLY_S("DACR ANTI-POP", 2, SND_SOC_NOPM,
92 INNO_R09_HPR_ANITPOP_SHIFT, 0, rk3036_codec_antipop_event,
93 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
94 SND_SOC_DAPM_SUPPLY_S("HPL OUT EN", 3, INNO_R05,
95 INNO_R05_HPL_EN_SHIFT, 0, NULL,
96 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
97 SND_SOC_DAPM_SUPPLY_S("HPR OUT EN", 3, INNO_R05,
98 INNO_R05_HPR_EN_SHIFT, 0, NULL,
99 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
100 SND_SOC_DAPM_SUPPLY_S("HPL OUT WORK", 4, INNO_R05,
101 INNO_R05_HPL_WORK_SHIFT, 0, NULL,
102 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
103 SND_SOC_DAPM_SUPPLY_S("HPR OUT WORK", 4, INNO_R05,
104 INNO_R05_HPR_WORK_SHIFT, 0, NULL,
105 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
106 SND_SOC_DAPM_SUPPLY_S("DACL HiLo VREF", 5, INNO_R06,
107 INNO_R06_DACL_HILO_VREF_SHIFT, 0, NULL,
108 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
109 SND_SOC_DAPM_SUPPLY_S("DACR HiLo VREF", 5, INNO_R06,
110 INNO_R06_DACR_HILO_VREF_SHIFT, 0, NULL,
111 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
112 SND_SOC_DAPM_SUPPLY_S("DACL CLK", 6, INNO_R04,
113 INNO_R04_DACL_CLK_SHIFT, 0, NULL,
114 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
115 SND_SOC_DAPM_SUPPLY_S("DACR CLK", 6, INNO_R04,
116 INNO_R04_DACR_CLK_SHIFT, 0, NULL,
117 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
118 SND_SOC_DAPM_SUPPLY_S("DACL WORK", 7, INNO_R04,
119 INNO_R04_DACL_SW_SHIFT, 0, NULL,
120 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
121 SND_SOC_DAPM_SUPPLY_S("DACR WORK", 7, INNO_R04,
122 INNO_R04_DACR_SW_SHIFT, 0, NULL,
123 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
124
125 SND_SOC_DAPM_DAC_E("DACL", "Left Playback", INNO_R09,
126 INNO_R09_DACL_SWITCH_SHIFT, 0, NULL,
127 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
128 SND_SOC_DAPM_DAC_E("DACR", "Right Playback", INNO_R09,
129 INNO_R09_DACR_SWITCH_SHIFT, 0, NULL,
130 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
131
132 SND_SOC_DAPM_AIF_IN("DAI-IN", "Playback", 0, SND_SOC_NOPM, 0, 0),
133
134 SND_SOC_DAPM_OUTPUT("HPL"),
135 SND_SOC_DAPM_OUTPUT("HPR"),
136 };
137
138 static const struct snd_soc_dapm_route rk3036_codec_dapm_routes[] = {
139 {"DACL VREF", NULL, "DAC PWR"},
140 {"DACR VREF", NULL, "DAC PWR"},
141 {"DACL ANTI-POP", NULL, "DAC PWR"},
142 {"DACR ANTI-POP", NULL, "DAC PWR"},
143 {"HPL OUT EN", NULL, "DAC PWR"},
144 {"HPR OUT EN", NULL, "DAC PWR"},
145 {"HPL OUT WORK", NULL, "DAC PWR"},
146 {"HPR OUT WORK", NULL, "DAC PWR"},
147 {"DACL HiLo VREF", NULL, "DAC PWR"},
148 {"DACR HiLo VREF", NULL, "DAC PWR"},
149 {"DACL CLK", NULL, "DAC PWR"},
150 {"DACR CLK", NULL, "DAC PWR"},
151 {"DACL WORK", NULL, "DAC PWR"},
152 {"DACR WORK", NULL, "DAC PWR"},
153
154 {"DACL", NULL, "DACL VREF"},
155 {"DACL", NULL, "DACL ANTI-POP"},
156 {"DACL", NULL, "HPL OUT EN"},
157 {"DACL", NULL, "HPL OUT WORK"},
158 {"DACL", NULL, "DACL HiLo VREF"},
159 {"DACL", NULL, "DACL CLK"},
160 {"DACL", NULL, "DACL WORK"},
161 {"DACR", NULL, "DACR VREF"},
162 {"DACR", NULL, "DACR ANTI-POP"},
163 {"DACR", NULL, "HPR OUT EN"},
164 {"DACR", NULL, "HPR OUT WORK"},
165 {"DACR", NULL, "DACR HiLo VREF"},
166 {"DACR", NULL, "DACR CLK"},
167 {"DACR", NULL, "DACR WORK"},
168
169 {"DACL", NULL, "DAI-IN"},
170 {"DACR", NULL, "DAI-IN"},
171
172 {"HPL", NULL, "DACL"},
173 {"HPR", NULL, "DACR"},
174 };
175
rk3036_codec_dai_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)176 static int rk3036_codec_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
177 {
178 struct snd_soc_component *component = dai->component;
179 unsigned int reg01_val = 0, reg02_val = 0, reg03_val = 0;
180
181 dev_dbg(component->dev, "rk3036_codec dai set fmt : %08x\n", fmt);
182
183 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
184 case SND_SOC_DAIFMT_CBS_CFS:
185 reg01_val |= INNO_R01_PINDIR_IN_SLAVE |
186 INNO_R01_I2SMODE_SLAVE;
187 break;
188 case SND_SOC_DAIFMT_CBM_CFM:
189 reg01_val |= INNO_R01_PINDIR_OUT_MASTER |
190 INNO_R01_I2SMODE_MASTER;
191 break;
192 default:
193 dev_err(component->dev, "invalid fmt\n");
194 return -EINVAL;
195 }
196
197 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
198 case SND_SOC_DAIFMT_DSP_A:
199 reg02_val |= INNO_R02_DACM_PCM;
200 break;
201 case SND_SOC_DAIFMT_I2S:
202 reg02_val |= INNO_R02_DACM_I2S;
203 break;
204 case SND_SOC_DAIFMT_RIGHT_J:
205 reg02_val |= INNO_R02_DACM_RJM;
206 break;
207 case SND_SOC_DAIFMT_LEFT_J:
208 reg02_val |= INNO_R02_DACM_LJM;
209 break;
210 default:
211 dev_err(component->dev, "set dai format failed\n");
212 return -EINVAL;
213 }
214
215 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
216 case SND_SOC_DAIFMT_NB_NF:
217 reg02_val |= INNO_R02_LRCP_NORMAL;
218 reg03_val |= INNO_R03_BCP_NORMAL;
219 break;
220 case SND_SOC_DAIFMT_IB_IF:
221 reg02_val |= INNO_R02_LRCP_REVERSAL;
222 reg03_val |= INNO_R03_BCP_REVERSAL;
223 break;
224 case SND_SOC_DAIFMT_IB_NF:
225 reg02_val |= INNO_R02_LRCP_REVERSAL;
226 reg03_val |= INNO_R03_BCP_NORMAL;
227 break;
228 case SND_SOC_DAIFMT_NB_IF:
229 reg02_val |= INNO_R02_LRCP_NORMAL;
230 reg03_val |= INNO_R03_BCP_REVERSAL;
231 break;
232 default:
233 dev_err(component->dev, "set dai format failed\n");
234 return -EINVAL;
235 }
236
237 snd_soc_component_update_bits(component, INNO_R01, INNO_R01_I2SMODE_MSK |
238 INNO_R01_PINDIR_MSK, reg01_val);
239 snd_soc_component_update_bits(component, INNO_R02, INNO_R02_LRCP_MSK |
240 INNO_R02_DACM_MSK, reg02_val);
241 snd_soc_component_update_bits(component, INNO_R03, INNO_R03_BCP_MSK, reg03_val);
242
243 return 0;
244 }
245
rk3036_codec_dai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * hw_params,struct snd_soc_dai * dai)246 static int rk3036_codec_dai_hw_params(struct snd_pcm_substream *substream,
247 struct snd_pcm_hw_params *hw_params,
248 struct snd_soc_dai *dai)
249 {
250 struct snd_soc_component *component = dai->component;
251 unsigned int reg02_val = 0, reg03_val = 0;
252
253 switch (params_format(hw_params)) {
254 case SNDRV_PCM_FORMAT_S16_LE:
255 reg02_val |= INNO_R02_VWL_16BIT;
256 break;
257 case SNDRV_PCM_FORMAT_S20_3LE:
258 reg02_val |= INNO_R02_VWL_20BIT;
259 break;
260 case SNDRV_PCM_FORMAT_S24_LE:
261 reg02_val |= INNO_R02_VWL_24BIT;
262 break;
263 case SNDRV_PCM_FORMAT_S32_LE:
264 reg02_val |= INNO_R02_VWL_32BIT;
265 break;
266 default:
267 return -EINVAL;
268 }
269
270 reg02_val |= INNO_R02_LRCP_NORMAL;
271 reg03_val |= INNO_R03_FWL_32BIT | INNO_R03_DACR_WORK;
272
273 snd_soc_component_update_bits(component, INNO_R02, INNO_R02_LRCP_MSK |
274 INNO_R02_VWL_MSK, reg02_val);
275 snd_soc_component_update_bits(component, INNO_R03, INNO_R03_DACR_MSK |
276 INNO_R03_FWL_MSK, reg03_val);
277 return 0;
278 }
279
rk3308_mute_stream(struct snd_soc_dai * dai,int mute,int stream)280 static int rk3308_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
281 {
282 struct snd_soc_component *component = dai->component;
283 struct rk3036_codec_priv *priv = snd_soc_component_get_drvdata(component);
284
285 if (stream == SNDRV_PCM_STREAM_CAPTURE)
286 return 0;
287
288 if (priv->pa_ctl)
289 gpiod_direction_output(priv->pa_ctl, !mute);
290
291 return 0;
292 }
293
294 #define RK3036_CODEC_RATES (SNDRV_PCM_RATE_8000 | \
295 SNDRV_PCM_RATE_16000 | \
296 SNDRV_PCM_RATE_32000 | \
297 SNDRV_PCM_RATE_44100 | \
298 SNDRV_PCM_RATE_48000 | \
299 SNDRV_PCM_RATE_96000)
300
301 #define RK3036_CODEC_FMTS (SNDRV_PCM_FMTBIT_S16_LE | \
302 SNDRV_PCM_FMTBIT_S20_3LE | \
303 SNDRV_PCM_FMTBIT_S24_LE | \
304 SNDRV_PCM_FMTBIT_S32_LE)
305
306 static const struct snd_soc_dai_ops rk3036_codec_dai_ops = {
307 .set_fmt = rk3036_codec_dai_set_fmt,
308 .hw_params = rk3036_codec_dai_hw_params,
309 .mute_stream = rk3308_mute_stream,
310 };
311
312 static struct snd_soc_dai_driver rk3036_codec_dai_driver[] = {
313 {
314 .name = "rk3036-codec-dai",
315 .playback = {
316 .stream_name = "Playback",
317 .channels_min = 1,
318 .channels_max = 2,
319 .rates = RK3036_CODEC_RATES,
320 .formats = RK3036_CODEC_FMTS,
321 },
322 .ops = &rk3036_codec_dai_ops,
323 .symmetric_rates = 1,
324 },
325 };
326
rk3036_codec_reset(struct snd_soc_component * component)327 static void rk3036_codec_reset(struct snd_soc_component *component)
328 {
329 snd_soc_component_write(component, INNO_R00,
330 INNO_R00_CSR_RESET | INNO_R00_CDCR_RESET);
331 snd_soc_component_write(component, INNO_R00,
332 INNO_R00_CSR_WORK | INNO_R00_CDCR_WORK);
333 }
334
rk3036_codec_probe(struct snd_soc_component * component)335 static int rk3036_codec_probe(struct snd_soc_component *component)
336 {
337 rk3036_codec_reset(component);
338 return 0;
339 }
340
rk3036_codec_remove(struct snd_soc_component * component)341 static void rk3036_codec_remove(struct snd_soc_component *component)
342 {
343 rk3036_codec_reset(component);
344 }
345
rk3036_codec_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)346 static int rk3036_codec_set_bias_level(struct snd_soc_component *component,
347 enum snd_soc_bias_level level)
348 {
349 switch (level) {
350 case SND_SOC_BIAS_PREPARE:
351 /* start precharge and waiting finish. */
352 snd_soc_component_write(component, INNO_R06, INNO_R06_DAC_PRECHARGE);
353 msleep(20);
354
355 break;
356
357 case SND_SOC_BIAS_STANDBY:
358 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
359 /* set a big current for capacitor charging. */
360 snd_soc_component_write(component, INNO_R10, INNO_R10_MAX_CUR);
361 }
362 /* start discharge. */
363 snd_soc_component_write(component, INNO_R06, INNO_R06_DAC_DISCHARGE);
364
365 break;
366 default:
367 break;
368 }
369
370 return 0;
371 }
372
373 static const struct snd_soc_component_driver rk3036_codec_driver = {
374 .probe = rk3036_codec_probe,
375 .remove = rk3036_codec_remove,
376 .set_bias_level = rk3036_codec_set_bias_level,
377 .controls = rk3036_codec_dapm_controls,
378 .num_controls = ARRAY_SIZE(rk3036_codec_dapm_controls),
379 .dapm_routes = rk3036_codec_dapm_routes,
380 .num_dapm_routes = ARRAY_SIZE(rk3036_codec_dapm_routes),
381 .dapm_widgets = rk3036_codec_dapm_widgets,
382 .num_dapm_widgets = ARRAY_SIZE(rk3036_codec_dapm_widgets),
383 .idle_bias_on = 1,
384 .use_pmdown_time = 1,
385 .endianness = 1,
386 .non_legacy_dai_naming = 1,
387 };
388
389 static const struct regmap_config rk3036_codec_regmap_config = {
390 .reg_bits = 32,
391 .reg_stride = 4,
392 .val_bits = 32,
393 };
394
395 #define GRF_SOC_CON0 0x00140
396 #define GRF_ACODEC_SEL (BIT(10) | BIT(16 + 10))
397
rk3036_codec_platform_probe(struct platform_device * pdev)398 static int rk3036_codec_platform_probe(struct platform_device *pdev)
399 {
400 struct rk3036_codec_priv *priv;
401 struct device_node *of_node = pdev->dev.of_node;
402 void __iomem *base;
403 struct regmap *grf;
404 int ret;
405
406 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
407 if (!priv)
408 return -ENOMEM;
409
410 base = devm_platform_ioremap_resource(pdev, 0);
411 if (IS_ERR(base))
412 return PTR_ERR(base);
413
414 priv->base = base;
415 priv->regmap = devm_regmap_init_mmio(&pdev->dev, priv->base,
416 &rk3036_codec_regmap_config);
417 if (IS_ERR(priv->regmap)) {
418 dev_err(&pdev->dev, "init regmap failed\n");
419 return PTR_ERR(priv->regmap);
420 }
421
422 grf = syscon_regmap_lookup_by_phandle(of_node, "rockchip,grf");
423 if (IS_ERR(grf)) {
424 dev_err(&pdev->dev, "needs 'rockchip,grf' property\n");
425 return PTR_ERR(grf);
426 }
427 ret = regmap_write(grf, GRF_SOC_CON0, GRF_ACODEC_SEL);
428 if (ret) {
429 dev_err(&pdev->dev, "Could not write to GRF: %d\n", ret);
430 return ret;
431 }
432
433 priv->pa_ctl = devm_gpiod_get_optional(&pdev->dev, "pa-ctl",
434 GPIOD_OUT_LOW);
435 if (!priv->pa_ctl) {
436 dev_info(&pdev->dev, "Don't need pa-ctl gpio\n");
437 } else if (IS_ERR(priv->pa_ctl)) {
438 dev_err(&pdev->dev, "Unable to claim gpio pa-ctl\n");
439 return PTR_ERR(priv->pa_ctl);
440 }
441
442 priv->pclk = devm_clk_get(&pdev->dev, "acodec_pclk");
443 if (IS_ERR(priv->pclk))
444 return PTR_ERR(priv->pclk);
445
446 ret = clk_prepare_enable(priv->pclk);
447 if (ret < 0) {
448 dev_err(&pdev->dev, "failed to enable clk\n");
449 return ret;
450 }
451
452 priv->dev = &pdev->dev;
453 dev_set_drvdata(&pdev->dev, priv);
454
455 ret = devm_snd_soc_register_component(&pdev->dev, &rk3036_codec_driver,
456 rk3036_codec_dai_driver,
457 ARRAY_SIZE(rk3036_codec_dai_driver));
458 if (ret) {
459 clk_disable_unprepare(priv->pclk);
460 dev_set_drvdata(&pdev->dev, NULL);
461 }
462
463 return ret;
464 }
465
rk3036_codec_platform_remove(struct platform_device * pdev)466 static int rk3036_codec_platform_remove(struct platform_device *pdev)
467 {
468 struct rk3036_codec_priv *priv = dev_get_drvdata(&pdev->dev);
469
470 clk_disable_unprepare(priv->pclk);
471
472 return 0;
473 }
474
475 static const struct of_device_id rk3036_codec_of_match[] = {
476 { .compatible = "rockchip,rk3036-codec", },
477 {}
478 };
479 MODULE_DEVICE_TABLE(of, rk3036_codec_of_match);
480
481 static struct platform_driver rk3036_codec_platform_driver = {
482 .driver = {
483 .name = "rk3036-codec-platform",
484 .of_match_table = of_match_ptr(rk3036_codec_of_match),
485 },
486 .probe = rk3036_codec_platform_probe,
487 .remove = rk3036_codec_platform_remove,
488 };
489
490 module_platform_driver(rk3036_codec_platform_driver);
491
492 MODULE_AUTHOR("Rockchip Inc.");
493 MODULE_DESCRIPTION("Rockchip rk3036 codec driver");
494 MODULE_LICENSE("GPL");
495