1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // es8396.c -- ES8396 ALSA SoC Audio Codec
4 //
5 // Copyright (C) 2014 Everest Semiconductor Co., Ltd
6 //
7 // Authors: David Yang(yangxiaohua@everest-semi.com)
8
9 #include <linux/module.h>
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/pm.h>
14 #include <linux/i2c.h>
15 #include <linux/slab.h>
16 #include <linux/regmap.h>
17 #include <linux/stddef.h>
18 #include <sound/core.h>
19 #include <sound/pcm.h>
20 #include <sound/pcm_params.h>
21 #include <sound/tlv.h>
22 #include <sound/soc.h>
23 #include <sound/initval.h>
24 #include <linux/gpio.h>
25 #include <linux/of_gpio.h>
26 #include <linux/mutex.h>
27 #include <linux/clk.h>
28 #include "es8396.h"
29
30 static int es8396_set_bias_level(struct snd_soc_component *component,
31 enum snd_soc_bias_level level);
32
33 /*
34 * ES8396 register cache
35 */
36 static struct reg_default es8396_reg_defaults[] = {
37 {0x00, 0x00},
38 {0x01, 0x00},
39 {0x02, 0x80},
40 {0x03, 0x00},
41 {0x04, 0x00},
42 {0x05, 0x00},
43 {0x06, 0x00},
44 {0x07, 0x00},
45 {0x08, 0x50},
46 {0x09, 0x04},
47 {0x0a, 0x00},
48 {0x0b, 0x20},
49 {0x0c, 0x20},
50 {0x0d, 0x00},
51 {0x0e, 0x00},
52 {0x0f, 0x00},
53
54 {0x10, 0x00},
55 {0x11, 0x00},
56 {0x12, 0x00},
57 {0x13, 0x00},
58 {0x14, 0x00},
59 {0x15, 0x00},
60 {0x16, 0x00},
61 {0x17, 0x00},
62 {0x18, 0x00},
63 {0x19, 0x00},
64 {0x1a, 0x00},
65 {0x1b, 0x00},
66 {0x1c, 0x00},
67 {0x1d, 0x00},
68 {0x1e, 0x00},
69 {0x1f, 0x00},
70
71 {0x20, 0x00},
72 {0x21, 0x00},
73 {0x22, 0x00},
74 {0x23, 0x00},
75 {0x24, 0x00},
76 {0x25, 0x00},
77 {0x26, 0x11},
78 {0x27, 0x00},
79 {0x28, 0x00},
80 {0x29, 0x04},
81 {0x2a, 0x00},
82 {0x2b, 0x33},
83 {0x2c, 0x00},
84 {0x2d, 0x04},
85 {0x2e, 0x00},
86 {0x2f, 0x11},
87
88 {0x30, 0x00},
89 {0x31, 0x04},
90 {0x32, 0x00},
91 {0x33, 0x11},
92 {0x34, 0x00},
93 {0x35, 0x04},
94 {0x36, 0x00},
95 {0x37, 0x11},
96 {0x38, 0x00},
97 {0x39, 0x04},
98 {0x3a, 0x44},
99 {0x3b, 0x00},
100 {0x3c, 0x20},
101 {0x3d, 0x00},
102 {0x3e, 0x00},
103 {0x3f, 0x00},
104
105 {0x40, 0x08},
106 {0x41, 0x88},
107 {0x42, 0x20},
108 {0x43, 0x82},
109 {0x44, 0x03},
110 {0x45, 0xa0},
111 {0x46, 0x00},
112 {0x47, 0x00},
113 {0x48, 0x01},
114 {0x49, 0x01},
115 {0x4a, 0x80},
116 {0x4b, 0x80},
117 {0x4c, 0x80},
118 {0x4d, 0x80},
119 {0x4e, 0x84},
120 {0x4f, 0x84},
121
122 {0x50, 0x84},
123 {0x51, 0x84},
124 {0x52, 0xc0},
125 {0x53, 0x80},
126 {0x54, 0x00},
127 {0x55, 0x00},
128 {0x56, 0xc0},
129 {0x57, 0xc0},
130 {0x58, 0x0b},
131 {0x59, 0x32},
132 {0x5a, 0x00},
133 {0x5b, 0x1f},
134 {0x5c, 0xc0},
135 {0x5d, 0x00},
136 {0x5e, 0xfc},
137 {0x5f, 0x02},
138
139 {0x60, 0x00},
140 {0x61, 0x00},
141 {0x62, 0x00},
142 {0x63, 0x00},
143 {0x64, 0x00},
144 {0x65, 0x00},
145 {0x66, 0x80},
146 {0x67, 0x00},
147 {0x68, 0x00},
148 {0x69, 0x00},
149 {0x6a, 0xc0},
150 {0x6b, 0xc0},
151 {0x6c, 0x00},
152 {0x6d, 0x00},
153 {0x6e, 0xc8},
154 {0x6f, 0x00},
155
156 {0x70, 0xd3},
157 {0x71, 0x90},
158 {0x72, 0x00},
159 {0x73, 0x00},
160 {0x74, 0x88},
161 {0x75, 0xc1},
162 {0x76, 0x00},
163 {0x77, 0x00},
164 {0x7a, 0x00},
165 {0x7b, 0x00},
166 };
167
168 static u8 es8396_equalizer_lpf_bt_incall[] = {
169 0x6D, 0x27, 0x64, 0x09, 0x4C, 0xA3, 0x53, 0x07, 0x6D, 0x27, 0x64, 0x09,
170 0x8D, 0xE5, 0x23, 0x00, 0x2A, 0xA3, 0x4A, 0x22,
171 0x6D, 0x27, 0x64, 0x09, 0x4C, 0xA3, 0x53, 0x07, 0x6D, 0x27, 0x64, 0x09,
172 0x8D, 0xE5, 0x23, 0x00, 0x2A, 0xA3, 0x4A, 0x22,
173 0x6D, 0x27, 0x64, 0x09, 0x4C, 0xA3, 0x53, 0x07, 0x6D, 0x27, 0x64, 0x09,
174 0x8D, 0xE5, 0x23, 0x00, 0x2A, 0xA3, 0x4A, 0x22,
175 };
176
177 struct sp_config {
178 u8 spc, mmcc, spfs;
179 u32 srate;
180 u8 lrcdiv;
181 u8 sclkdiv;
182 };
183
184 /* codec private data */
185 struct es8396_private {
186 struct snd_soc_component *component;
187 struct sp_config config[3];
188 struct regmap *regmap;
189 u8 sysclk[3];
190 u32 mclk[3];
191 struct clk *mclk_clock;
192
193 /* platform dependent DVDD voltage configuration */
194 u8 dvdd_pwr_vol;
195
196 /* platform dependent CLASS D Mono mode configuration */
197 bool spkmono;
198 /* platform dependent earpiece mode configuration */
199 bool earpiece;
200 /* platform dependent monon/p differential mode configuration */
201 bool monoin_differential;
202 /* platform dependent lout/rout differential mode configuration */
203 bool lno_differential;
204
205 /* platform dependent analog ldo level configuration */
206 u8 ana_ldo_lvl;
207 /* platform dependent speaker ldo level configuration */
208 u8 spk_ldo_lvl;
209 /* platform dependent mic bias voltage configuration */
210 u8 mic_bias_lvl;
211 u8 dmic_amic;
212
213 bool jackdet_enable;
214
215 u8 gpio_int_pol;
216
217 int shutdwn_delay;
218 int pon_delay;
219 struct gpio_desc *spk_ctl_gpio;
220 struct gpio_desc *lineout_ctl_gpio;
221
222 bool calibrate;
223 u8 output_device_selected;
224 u8 aif1_select;
225 u8 aif2_select;
226 /*
227 * Add a delay work-quenue, to debug DC calibration
228 */
229 struct mutex adc_depop_mlock;
230 struct delayed_work adc_depop_work;
231
232 /* for playback pop noise */
233 struct mutex pcm_depop_mlock;
234 struct delayed_work pcm_pop_work;
235 /* for playback pop noise */
236 struct mutex pcm_shutdown_depop_mlock;
237 struct delayed_work pcm_shutdown_depop_work;
238
239 /* for voice pop noise */
240 struct mutex voice_depop_mlock;
241 struct delayed_work voice_pop_work;
242 /* for voice pop noise */
243 struct mutex voice_shutdown_depop_mlock;
244 struct delayed_work voice_shutdown_depop_work;
245
246 /* for hp calibration */
247 struct mutex init_cali_mlock;
248 struct delayed_work init_cali_work;
249 int pcm_pop_work_retry;
250 };
251
es8396_valid_micbias(u8 micbias)252 static bool es8396_valid_micbias(u8 micbias)
253 {
254 switch (micbias) {
255 case MICBIAS_3V:
256 case MICBIAS_2_8V:
257 case MICBIAS_2_5V:
258 case MICBIAS_2_3V:
259 case MICBIAS_2V:
260 case MICBIAS_1_5V:
261 return true;
262 default:
263 break;
264 }
265 return false;
266 }
267
es8396_valid_analdo(u8 ldolvl)268 static bool es8396_valid_analdo(u8 ldolvl)
269 {
270 switch (ldolvl) {
271 case ANA_LDO_3V:
272 case ANA_LDO_2_9V:
273 case ANA_LDO_2_8V:
274 case ANA_LDO_2_7V:
275 case ANA_LDO_2_4V:
276 case ANA_LDO_2_3V:
277 case ANA_LDO_2_2V:
278 case ANA_LDO_2_1V:
279 return true;
280 default:
281 break;
282 }
283 return false;
284 }
285
es8396_valid_spkldo(u8 ldolvl)286 static bool es8396_valid_spkldo(u8 ldolvl)
287 {
288 switch (ldolvl) {
289 case SPK_LDO_3_3V:
290 case SPK_LDO_3_2V:
291 case SPK_LDO_3V:
292 case SPK_LDO_2_9V:
293 case SPK_LDO_2_8V:
294 case SPK_LDO_2_6V:
295 case SPK_LDO_2_5V:
296 case SPK_LDO_2_4V:
297 return true;
298 default:
299 break;
300 }
301 return false;
302 }
303
pcm_shutdown_depop_events(struct work_struct * work)304 static void pcm_shutdown_depop_events(struct work_struct *work)
305 {
306 struct es8396_private *es8396 = container_of(work, struct es8396_private,
307 pcm_shutdown_depop_work.work);
308 struct snd_soc_component *component = es8396->component;
309
310 mutex_lock(&es8396->pcm_shutdown_depop_mlock);
311 snd_soc_component_update_bits(component, ES8396_SDP1_IN_FMT_REG1F,
312 0x40, 0x40);
313 es8396->aif1_select &= 0xfe;
314 mutex_unlock(&es8396->pcm_shutdown_depop_mlock);
315 }
316
voice_shutdown_depop_events(struct work_struct * work)317 static void voice_shutdown_depop_events(struct work_struct *work)
318 {
319 struct es8396_private *es8396 = container_of(work, struct es8396_private,
320 voice_shutdown_depop_work.work);
321 struct snd_soc_component *component = es8396->component;
322
323 mutex_lock(&es8396->voice_shutdown_depop_mlock);
324 snd_soc_component_update_bits(component, ES8396_SDP2_IN_FMT_REG22,
325 0x7F, 0x53);
326 es8396->aif2_select &= 0xfe;
327 if (es8396->aif1_select != 0) {
328 snd_soc_component_write(component, 0x1A, 0x00);
329 snd_soc_component_write(component, 0x67, 0x00);
330 snd_soc_component_write(component, 0x69, 0x00);
331 snd_soc_component_write(component, 0x66, 0x00);
332 }
333 mutex_unlock(&es8396->voice_shutdown_depop_mlock);
334 }
335
init_cali_work_events(struct work_struct * work)336 static void init_cali_work_events(struct work_struct *work)
337 {
338 struct es8396_private *es8396 = container_of(work, struct es8396_private,
339 init_cali_work.work);
340 struct snd_soc_component *component = es8396->component;
341
342 mutex_lock(&es8396->init_cali_mlock);
343 pr_debug("init_cali_work_events\n");
344 if (es8396->pcm_pop_work_retry > 0) {
345 es8396->pcm_pop_work_retry--;
346 pr_debug("Enter into %s %d\n", __func__, __LINE__);
347 snd_soc_component_write(component, ES8396_DAC_OFFSET_CALI_REG6F, 0x83);
348 if (es8396->pcm_pop_work_retry) {
349 schedule_delayed_work(&es8396->init_cali_work,
350 msecs_to_jiffies(100));
351 }
352 }
353 snd_soc_component_write(component, ES8396_ADC_ANALOG_CTRL_REG5E, 0x3C);
354
355 /* use line out */
356 msleep(100);
357 snd_soc_component_write(component, 0x4E, 0x80);
358 snd_soc_component_write(component, 0x4F, 0x81);
359 snd_soc_component_write(component, 0x4A, 0x60);
360 snd_soc_component_write(component, 0x4B, 0x60);
361
362 mutex_unlock(&es8396->init_cali_mlock);
363 }
364
voice_pop_work_events(struct work_struct * work)365 static void voice_pop_work_events(struct work_struct *work)
366 {
367 struct es8396_private *es8396 = container_of(work, struct es8396_private,
368 voice_pop_work.work);
369 struct snd_soc_component *component = es8396->component;
370 int i;
371
372 mutex_lock(&es8396->voice_depop_mlock);
373 pr_debug("voice_pop_work_events\n");
374 /*
375 * set the clock source to pll out
376 * set divider for voice playback
377 * set Equalizer
378 * set DAC source from equalizer
379 */
380 snd_soc_component_update_bits(component, ES8396_SDP2_IN_FMT_REG22,
381 0x3F, 0x13);
382 snd_soc_component_update_bits(component, ES8396_SDP2_OUT_FMT_REG23,
383 0x7F, 0x33);
384 /* use line out */
385 snd_soc_component_write(component, 0x4E, 0x80);
386 snd_soc_component_write(component, 0x4F, 0x81);
387 snd_soc_component_write(component, 0x4A, 0x60);
388 snd_soc_component_write(component, 0x4B, 0x60);
389 snd_soc_component_write(component, 0x1A, 0x40); /* Enable HPOUT */
390
391 /* unmute dac */
392 snd_soc_component_write(component, 0x66, 0x00);
393
394 for (i = 0; i < 120; i = i + 2) {
395 snd_soc_component_write(component, 0x6A, 120 - i);
396 snd_soc_component_write(component, 0x6B, 120 - i);
397 usleep_range(100, 200);
398 }
399
400 mutex_unlock(&es8396->voice_depop_mlock);
401 }
402
pcm_pop_work_events(struct work_struct * work)403 static void pcm_pop_work_events(struct work_struct *work)
404 {
405 struct es8396_private *es8396 = container_of(work, struct es8396_private,
406 pcm_pop_work.work);
407 struct snd_soc_component *component = es8396->component;
408 int i;
409
410 mutex_lock(&es8396->pcm_depop_mlock);
411 pr_debug("pcm_pop_work_events\n");
412
413 snd_soc_component_write(component, ES8396_SYS_VMID_REF_REG71, 0xFC);
414
415 /* use line out */
416 snd_soc_component_write(component, 0x4E, 0x80);
417 snd_soc_component_write(component, 0x4F, 0x81);
418 snd_soc_component_write(component, 0x4A, 0x60);
419 snd_soc_component_write(component, 0x4B, 0x60);
420 snd_soc_component_update_bits(component, ES8396_DAC_CSM_REG66, 0x03, 0x00);
421 snd_soc_component_update_bits(component, ES8396_SDP1_IN_FMT_REG1F, 0x40, 0x00);
422 for (i = 0; i < 120; i = i + 2) {
423 snd_soc_component_write(component, 0x6A, 120 - i);
424 snd_soc_component_write(component, 0x6B, 120 - i);
425 usleep_range(100, 200);
426 }
427 mutex_unlock(&es8396->pcm_depop_mlock);
428 }
429
430 /*********************************************************************
431 * to power on/off class d with min pop noise
432 *********************************************************************/
classd_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)433 static int classd_event(struct snd_soc_dapm_widget *w,
434 struct snd_kcontrol *kcontrol, int event)
435 {
436 unsigned int regv1, regv2, lvl;
437 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
438 struct es8396_private *es8396 = snd_soc_component_get_drvdata(component);
439
440 switch (event) {
441 case SND_SOC_DAPM_PRE_PMU: /* prepare power up */
442 /* power up class d */
443 pr_debug("SND_SOC_DAPM_PRE_PMU = 0x%x\n", event);
444 /* read the clock configure */
445 regv1 = snd_soc_component_read(component, ES8396_CLK_CTRL_REG08);
446 regv1 &= 0xcf;
447 /* enable class d clock */
448 snd_soc_component_write(component, ES8396_CLK_CTRL_REG08, regv1);
449 /* dac csm startup, dac digital still on */
450 snd_soc_component_update_bits(component, ES8396_DAC_CSM_REG66, 0xFE, 0x00);
451 /* dac analog power on */
452 snd_soc_component_update_bits(component, ES8396_DAC_REF_PWR_CTRL_REG6E,
453 0xff, 0x34);
454
455 regv2 = snd_soc_component_read(component, ES8396_SPK_CTRL_1_REG3C);
456 /* set speaker ldo level */
457 if (es8396_valid_spkldo(es8396->spk_ldo_lvl) == false) {
458 pr_err("speaker LDO Level error.\n");
459 return -EINVAL;
460 } else {
461 regv1 = regv2 & 0xD8;
462 lvl = es8396->spk_ldo_lvl;
463 lvl &= 0x07;
464 regv1 |= lvl;
465 regv1 |= 0x10;
466 }
467 if (es8396->spkmono == 1) { /* speaker in mono mode */
468 regv1 = regv1 | 0x40;
469 } else {
470 regv1 = regv1 & 0xbf;
471 }
472 snd_soc_component_write(component, ES8396_SPK_CTRL_1_REG3C, regv1);
473
474 snd_soc_component_write(component, ES8396_SPK_CTRL_2_REG3D, 0x10);
475
476 regv1 = snd_soc_component_read(component, ES8396_SPK_MIXER_REG26);
477 /* clear pdnspkl_biasgen, clear pdnspkr_biasgen */
478 regv1 &= 0xee;
479 snd_soc_component_write(component, ES8396_SPK_MIXER_REG26, regv1);
480 snd_soc_component_write(component, ES8396_SPK_MIXER_VOL_REG28, 0x33);
481
482 snd_soc_component_write(component, ES8396_SPK_CTRL_SRC_REG3A, 0xA9);
483 /* L&R DAC Vol=-6db */
484 snd_soc_component_write(component, ES8396_DAC_LDAC_VOL_REG6A, 0x00);
485 snd_soc_component_write(component, ES8396_DAC_RDAC_VOL_REG6B, 0x00);
486
487 regv1 = snd_soc_component_read(component, ES8396_HP_MIXER_BOOST_REG2B);
488 regv1 &= 0xcc;
489 snd_soc_component_write(component, ES8396_HP_MIXER_BOOST_REG2B, regv1);
490
491 regv1 = snd_soc_component_read(component, ES8396_CPHP_CTRL_3_REG44);
492 regv1 &= 0xcc;
493 snd_soc_component_write(component, ES8396_CPHP_CTRL_3_REG44, regv1);
494
495 regv1 = snd_soc_component_read(component, ES8396_CPHP_CTRL_1_REG42);
496 regv1 &= 0xdf;
497 snd_soc_component_write(component, ES8396_CPHP_CTRL_1_REG42, regv1);
498
499 regv1 = snd_soc_component_read(component, ES8396_CPHP_CTRL_2_REG43);
500 regv1 &= 0x7f;
501 snd_soc_component_write(component, ES8396_CPHP_CTRL_2_REG43, regv1);
502 es8396->output_device_selected = 0;
503 break;
504 case SND_SOC_DAPM_POST_PMU: /* after power up */
505 pr_debug("SND_SOC_DAPM_POST_PMU = 0x%x\n", event);
506 schedule_delayed_work(&es8396->pcm_pop_work,
507 msecs_to_jiffies(50));
508 break;
509 case SND_SOC_DAPM_PRE_PMD: /* prepare power down */
510 pr_debug("SND_SOC_DAPM_PRE_PMD = 0x%x\n", event);
511 /* read the clock configure */
512 regv1 = snd_soc_component_read(component, ES8396_CLK_CTRL_REG08);
513 regv1 |= 0x10;
514 /* stop class d clock */
515 snd_soc_component_write(component, ES8396_CLK_CTRL_REG08, regv1);
516 /* dac csm startup, dac digital still on */
517 /* snd_soc_component_update_bits(w->component, ES8396_DAC_CSM_REG66,
518 0x01, 0x01); */
519 regv1 = snd_soc_component_read(component, ES8396_SPK_EN_VOL_REG3B);
520 regv1 &= 0x77;
521 /* clear enspk_l,enspk_r */
522 snd_soc_component_write(component, ES8396_SPK_EN_VOL_REG3B, regv1);
523
524 regv1 = snd_soc_component_read(component, ES8396_SPK_CTRL_SRC_REG3A);
525 regv1 |= 0x44; /* set pdnspkl_biasgen, set pdnspkr_biasgen */
526 snd_soc_component_write(component, ES8396_SPK_CTRL_SRC_REG3A, regv1);
527 regv1 = snd_soc_component_read(component, ES8396_SPK_MIXER_REG26);
528 /* clear pdnspkl_biasgen, clear pdnspkr_biasgen */
529 regv1 |= 0x11;
530 snd_soc_component_write(component, ES8396_SPK_MIXER_REG26, regv1);
531 snd_soc_component_update_bits(component, ES8396_SPK_CTRL_1_REG3C, 0x20,
532 0x20);
533 break;
534 case SND_SOC_DAPM_POST_PMD: /* after power down */
535 pr_debug("SND_SOC_DAPM_POST_PMD = 0x%x\n", event);
536 break;
537 default:
538 break;
539 }
540 return 0;
541 }
542
micbias_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)543 static int micbias_event(struct snd_soc_dapm_widget *w,
544 struct snd_kcontrol *kcontrol, int event)
545 {
546 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
547 struct es8396_private *es8396 = snd_soc_component_get_drvdata(component);
548 unsigned int regv;
549
550 switch (event) {
551 case SND_SOC_DAPM_PRE_PMU:
552 if (es8396_valid_micbias(es8396->mic_bias_lvl) == false) {
553 pr_err("MIC BIAS Level error.\n");
554 return -EINVAL;
555 } else {
556 regv = es8396->mic_bias_lvl;
557 regv &= 0x07;
558 regv = (regv << 4) | 0x08;
559 /* enable micbias1 */
560 snd_soc_component_write(component, ES8396_SYS_MICBIAS_CTRL_REG74,
561 regv);
562 }
563 regv = snd_soc_component_read(component, ES8396_ALRCK_GPIO_SEL_REG15);
564 if (es8396->dmic_amic == MIC_DMIC) {
565 regv &= 0xf0; /* enable DMIC CLK */
566 regv |= 0x0A;
567 } else {
568 regv &= 0xf0; /* disable DMIC CLK */
569 }
570 snd_soc_component_write(component, ES8396_ALRCK_GPIO_SEL_REG15, regv);
571 break;
572 case SND_SOC_DAPM_POST_PMD:
573 regv = snd_soc_component_read(component, ES8396_ALRCK_GPIO_SEL_REG15);
574 regv &= 0xf0; /* disable DMIC CLK */
575 snd_soc_component_write(component, ES8396_ALRCK_GPIO_SEL_REG15, regv);
576 break;
577 default:
578 break;
579 }
580
581 return 0;
582 }
583
adc_depop_work_events(struct work_struct * work)584 static void adc_depop_work_events(struct work_struct *work)
585 {
586 struct es8396_private *es8396 = container_of(work, struct es8396_private,
587 adc_depop_work.work);
588 struct snd_soc_component *component = es8396->component;
589
590 pr_debug("adc_depop_work_events\n");
591 mutex_lock(&es8396->adc_depop_mlock);
592 snd_soc_component_update_bits(component, ES8396_SDP1_OUT_FMT_REG20, 0x40, 0x00);
593 mutex_unlock(&es8396->adc_depop_mlock);
594 }
595
adc_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)596 static int adc_event(struct snd_soc_dapm_widget *w,
597 struct snd_kcontrol *kcontrol, int event)
598 {
599 unsigned int regv;
600 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
601 struct es8396_private *es8396 = snd_soc_component_get_drvdata(component);
602
603 pr_debug("Enter into %s %d\n", __func__, __LINE__);
604 switch (event) {
605 case SND_SOC_DAPM_PRE_PMU:
606 pr_debug("Enter into SND_SOC_DAPM_PRE_PMU %s %d\n", __func__,
607 __LINE__);
608 snd_soc_component_update_bits(component, ES8396_SDP1_OUT_FMT_REG20, 0x40,
609 0x40);
610 /* set adc alc */
611 snd_soc_component_write(component, ES8396_ADC_ALC_CTRL_1_REG58, 0xC6);
612 snd_soc_component_write(component, ES8396_ADC_ALC_CTRL_2_REG59, 0x12);
613 snd_soc_component_write(component, ES8396_ADC_ALC_CTRL_4_REG5B, 0x04);
614 snd_soc_component_write(component, ES8396_ADC_ALC_CTRL_5_REG5C, 0xC8);
615 snd_soc_component_write(component, ES8396_ADC_ALC_CTRL_6_REG5D, 0x11);
616 snd_soc_component_write(component, ES8396_ADC_ANALOG_CTRL_REG5E, 0x0);
617 /* Enable MIC BOOST */
618 snd_soc_component_write(component, ES8396_SYS_MIC_IBIAS_EN_REG75, 0x02);
619
620 /* axMixer Gain boost */
621 regv = snd_soc_component_read(component, ES8396_AX_MIXER_BOOST_REG2F);
622 regv |= 0x88;
623 snd_soc_component_write(component, ES8396_AX_MIXER_BOOST_REG2F, regv);
624 /* axmixer vol = +12db */
625 snd_soc_component_write(component, ES8396_AX_MIXER_VOL_REG30, 0xaa);
626 /* axmixer high driver capacility */
627 snd_soc_component_write(component, ES8396_AX_MIXER_REF_LP_REG31, 0x02);
628
629 /* MNMixer Gain boost */
630 regv = snd_soc_component_read(component, ES8396_MN_MIXER_BOOST_REG37);
631 regv |= 0x88;
632 snd_soc_component_write(component, ES8396_MN_MIXER_BOOST_REG37, regv);
633 /* mnmixer vol = +12db */
634 snd_soc_component_write(component, ES8396_MN_MIXER_VOL_REG38, 0x44);
635 /* mnmixer high driver capacility */
636 snd_soc_component_write(component, ES8396_MN_MIXER_REF_LP_REG39, 0x02);
637
638 msleep(200);
639 /* ADC STM and Digital Startup, ADC DS Mode */
640 snd_soc_component_write(component, ES8396_ADC_CSM_REG53, 0x00);
641 /* force adc stm to normal */
642 snd_soc_component_write(component, ES8396_ADC_FORCE_REG77, 0x40);
643 snd_soc_component_write(component, ES8396_ADC_FORCE_REG77, 0x0);
644 /* ADC Volume =0db */
645 snd_soc_component_write(component, ES8396_ADC_LADC_VOL_REG56, 0x0);
646 snd_soc_component_write(component, ES8396_ADC_RADC_VOL_REG57, 0x0);
647 snd_soc_component_write(component, ES8396_ADC_CLK_DIV_REG09, 0x04);
648
649 schedule_delayed_work(&es8396->adc_depop_work,
650 msecs_to_jiffies(150));
651 break;
652 case SND_SOC_DAPM_PRE_PMD:
653 pr_debug("Enter into SND_SOC_DAPM_PRE_PMD %s %d\n", __func__,
654 __LINE__);
655 snd_soc_component_write(component, ES8396_ADC_CSM_REG53, 0x20);
656 snd_soc_component_write(component, ES8396_ADC_CLK_DIV_REG09, 0x04);
657 break;
658 default:
659 break;
660 }
661
662 return 0;
663 }
664
665 /*********************************************************************
666 * to power on/off headphone with min pop noise
667 ********************************************************************/
hpamp_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)668 static int hpamp_event(struct snd_soc_dapm_widget *w,
669 struct snd_kcontrol *kcontrol, int event)
670 {
671 unsigned int regv;
672 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
673 struct es8396_private *es8396 = snd_soc_component_get_drvdata(component);
674
675 pr_debug("Enter into %s %d\n", __func__, __LINE__);
676 switch (event) {
677 case SND_SOC_DAPM_PRE_PMU:
678 pr_debug("Enter into %s %d, event = SND_SOC_DAPM_PRE_PMU\n",
679 __func__, __LINE__);
680 es8396->output_device_selected = 1;
681 break;
682 case SND_SOC_DAPM_POST_PMU:
683 pr_debug("Enter into %s %d, event = SND_SOC_DAPM_POST_PMU\n",
684 __func__, __LINE__);
685 schedule_delayed_work(&es8396->pcm_pop_work,
686 msecs_to_jiffies(50));
687 break;
688 case SND_SOC_DAPM_PRE_PMD:
689 pr_debug("Enter into %s %d, event = SND_SOC_DAPM_PRE_PMD\n",
690 __func__, __LINE__);
691 /* dac analog power down */
692 snd_soc_component_update_bits(component, ES8396_DAC_CSM_REG66, 0x42, 0x00);
693 break;
694 case SND_SOC_DAPM_POST_PMD:
695 pr_debug("Enter into %s %d, event = SND_SOC_DAPM_POST_PMD\n",
696 __func__, __LINE__);
697 /* dac analog power down */
698 snd_soc_component_update_bits(component, ES8396_DAC_CSM_REG66, 0x40, 0x40);
699 /* dac analog power down */
700 snd_soc_component_update_bits(component, ES8396_DAC_REF_PWR_CTRL_REG6E,
701 0xC0, 0xC0);
702 /* read the clock configure */
703 regv = snd_soc_component_read(component, ES8396_CLK_CTRL_REG08);
704 regv |= 0x20;
705 /* stop charge pump clock */
706 snd_soc_component_write(component, ES8396_CLK_CTRL_REG08, regv);
707
708 regv = snd_soc_component_read(component, ES8396_HP_MIXER_BOOST_REG2B);
709 regv |= 0x11;
710 snd_soc_component_write(component, ES8396_HP_MIXER_BOOST_REG2B, regv);
711 break;
712 default:
713 break;
714 }
715
716 return 0;
717 }
718
719 /*
720 * ES8396 Controls
721 */
722 static const DECLARE_TLV_DB_RANGE(mixvol_tlv,
723 0, 4, TLV_DB_SCALE_ITEM(-1200, 150, 0),
724 8, 11, TLV_DB_SCALE_ITEM(-600, 150, 0));
725 static const DECLARE_TLV_DB_RANGE(boost_tlv,
726 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
727 1, 3, TLV_DB_SCALE_ITEM(2000, 0, 0));
728
729 /* -34.5db min scale, 1.5db steps, no mute */
730 static const DECLARE_TLV_DB_SCALE(vol_tlv, -600, 150, 0);
731 /* -34.5db min scale, 1.5db steps, no mute */
732 static const DECLARE_TLV_DB_SCALE(spk_vol_tlv, 0, 150, 0);
733 /* -46.5db min scale, 1.5db steps, no mute */
734 static const DECLARE_TLV_DB_SCALE(hp_tlv, -4800, 1200, 0);
735 /* -16.5db min scale, 1.5db steps, no mute */
736 static const DECLARE_TLV_DB_SCALE(adc_rec_tlv, -9600, 50, 0);
737
738 static const DECLARE_TLV_DB_SCALE(lineout_tlv, -1200, 1200, 0);
739
740 /* 0db min scale, 6 db steps, no mute */
741 static const DECLARE_TLV_DB_SCALE(dig_tlv, 0, 600, 0);
742 /* 0db min scalem 0.75db steps, no mute */
743 static const DECLARE_TLV_DB_SCALE(vdac_tlv, -9600, 50, 0);
744
745 static const char *const alc_func_txt[] = { "Off", "LOn", "ROn", "StereoOn" };
746
747 static const struct soc_enum alc_func =
748 SOC_ENUM_SINGLE(ES8396_ADC_ALC_CTRL_1_REG58, 6, 4, alc_func_txt);
749
750 /*
751 *define the line in,mic in, phone in ,and aif1-2 in volume/switch
752 */
753 static const struct snd_kcontrol_new es8396_snd_controls[] = {
754 SOC_DOUBLE_R_TLV("DAC Playback Volume",
755 ES8396_DAC_LDAC_VOL_REG6A, ES8396_DAC_RDAC_VOL_REG6B,
756 0, 127, 1, vdac_tlv),
757 SOC_DOUBLE_TLV("MNIN MIXER Volume",
758 ES8396_MN_MIXER_VOL_REG38, 4, 0, 3, 1, mixvol_tlv),
759
760 SOC_DOUBLE_TLV("LIN MIXER Volume",
761 ES8396_LN_MIXER_VOL_REG34, 4, 0, 4, 0, mixvol_tlv),
762
763 SOC_DOUBLE_TLV("AXIN MIXER Volume",
764 ES8396_AX_MIXER_VOL_REG30, 4, 0, 4, 0, mixvol_tlv),
765 SOC_DOUBLE_TLV("Mic Boost Volume",
766 ES8396_ADC_MICBOOST_REG60, 4, 0, 3, 0, boost_tlv),
767
768 SOC_DOUBLE_R_TLV("ADC Capture Volume",
769 ES8396_ADC_LADC_VOL_REG56, ES8396_ADC_RADC_VOL_REG57,
770 0, 127, 1, adc_rec_tlv),
771
772 SOC_SINGLE_TLV("Speakerl Playback Volume",
773 ES8396_SPK_EN_VOL_REG3B, 4, 7, 0, spk_vol_tlv),
774 SOC_SINGLE_TLV("Speakerr Playback Volume",
775 ES8396_SPK_EN_VOL_REG3B, 0, 7, 0, spk_vol_tlv),
776
777 SOC_SINGLE_TLV("Headphonel Playback Volume",
778 ES8396_CPHP_ICAL_VOL_REG41, 4, 3, 1, hp_tlv),
779 SOC_SINGLE_TLV("Headphoner Playback Volume",
780 ES8396_CPHP_ICAL_VOL_REG41, 0, 3, 1, hp_tlv),
781 /*
782 * lineout playback volume
783 */
784 SOC_SINGLE_TLV("Lineoutp Playback Volume",
785 ES8396_LNOUT_LO1_GAIN_CTRL_REG4E, 5, 1, 1, lineout_tlv),
786 SOC_SINGLE_TLV("Lineoutn Playback Volume",
787 ES8396_LNOUT_RO1_GAIN_CTRL_REG4F, 5, 1, 1, lineout_tlv),
788 /*
789 * monoout playback volume
790 */
791 SOC_SINGLE_TLV("Monooutp Playback Volume",
792 ES8396_MONOHP_P_BOOST_MUTE_REG48, 3, 1, 1, lineout_tlv),
793 SOC_SINGLE_TLV("Monooutn Playback Volume",
794 ES8396_MONOHP_N_BOOST_MUTE_REG49, 3, 1, 1, lineout_tlv),
795 SOC_ENUM("ALC Capture Function", alc_func),
796 };
797
798 /*
799 * DAPM Controls
800 */
801 static const struct snd_kcontrol_new es8396_dac_controls =
802 SOC_DAPM_SINGLE("Switch", ES8396_DAC_CSM_REG66, 3, 1, 1);
803
804 static const struct snd_kcontrol_new hp_amp_ctl =
805 SOC_DAPM_SINGLE("Switch", ES8396_CP_CLK_DIV_REG0B, 1, 1, 1);
806
807 static const struct snd_kcontrol_new es8396_hpl_mixer_controls[] = {
808 SOC_DAPM_SINGLE("LNMUX2HPMIX_L Switch", ES8396_HP_MIXER_REG2A, 6, 1, 0),
809 SOC_DAPM_SINGLE("AXMUX2HPMIX_L Switch", ES8396_HP_MIXER_REG2A, 5, 1, 0),
810 SOC_DAPM_SINGLE("DACL2HPMIX Switch", ES8396_HP_MIXER_REF_LP_REG2D,
811 5, 1, 0),
812 };
813
814 static const struct snd_kcontrol_new es8396_hpr_mixer_controls[] = {
815 SOC_DAPM_SINGLE("LNMUX2HPMIX_R Switch", ES8396_HP_MIXER_REG2A, 2, 1, 0),
816 SOC_DAPM_SINGLE("AXMUX2HPMIX_R Switch", ES8396_HP_MIXER_REG2A, 1, 1, 0),
817 SOC_DAPM_SINGLE("DACR2HPMIX Switch", ES8396_HP_MIXER_REF_LP_REG2D,
818 4, 1, 0),
819 };
820
821 /*
822 * Only used mono out p mixer for differential output
823 */
824 static const struct snd_kcontrol_new es8396_mono_p_mixer_controls[] = {
825 SOC_DAPM_SINGLE("LHPMIX2MNMIXP Switch", ES8396_MONOHP_P_MIXER_REG47, 7,
826 1, 0),
827 SOC_DAPM_SINGLE("RHPMIX2MNOMIXP Switch", ES8396_MONOHP_P_MIXER_REG47, 6,
828 1, 0),
829 SOC_DAPM_SINGLE("RMNMIX2MNOMIXP Switch", ES8396_MONOHP_P_MIXER_REG47, 5,
830 1, 0),
831 SOC_DAPM_SINGLE("RAXMIX2MNOMIXP Switch",
832 ES8396_MONOHP_P_MIXER_REG47, 4, 1, 0),
833 SOC_DAPM_SINGLE("LLNMIX2MNOMIXP Switch",
834 ES8396_MONOHP_P_MIXER_REG47, 3, 1, 0),
835 };
836
837 static const struct snd_kcontrol_new es8396_mono_n_mixer_controls[] = {
838 SOC_DAPM_SINGLE("LMNMIX2MNMIXN Switch", ES8396_MONOHP_N_MIXER_REG46, 7,
839 1, 0),
840 SOC_DAPM_SINGLE("RHPMIX2MNOMIXN Switch", ES8396_MONOHP_N_MIXER_REG46, 6,
841 1, 0),
842 SOC_DAPM_SINGLE("MOPINV2MNOMIXN Switch", ES8396_MONOHP_N_MIXER_REG46, 5,
843 1, 0),
844 SOC_DAPM_SINGLE("LLNMIX2MNOMIXN Switch",
845 ES8396_MONOHP_N_MIXER_REG46, 4, 1, 0),
846 SOC_DAPM_SINGLE("LAXMIX2MNOMIXN Switch",
847 ES8396_MONOHP_N_MIXER_REG46, 3, 1, 0),
848 };
849
850 /*
851 * define the stereo class d speaker mixer
852 */
853 static const struct snd_kcontrol_new es8396_speaker_lmixer_controls[] = {
854 SOC_DAPM_SINGLE("LLNMUX2SPKMIX Switch", ES8396_SPK_MIXER_REG26, 6, 1,
855 0),
856 SOC_DAPM_SINGLE("LAXMUX2SPKMIX Switch", ES8396_SPK_MIXER_REG26, 5, 1,
857 0),
858 SOC_DAPM_SINGLE("LDAC2SPKMIX Switch", ES8396_SPK_MIXER_REG26, 7, 1, 0),
859 };
860
861 static const struct snd_kcontrol_new es8396_speaker_rmixer_controls[] = {
862 SOC_DAPM_SINGLE("RLNMUX2SPKMIX Switch", ES8396_SPK_MIXER_REG26, 2, 1,
863 0),
864 SOC_DAPM_SINGLE("RAXMUX2SPKMIX Switch", ES8396_SPK_MIXER_REG26, 1, 1,
865 0),
866 SOC_DAPM_SINGLE("RDAC2SPKMIX Switch", ES8396_SPK_MIXER_REG26, 3, 1, 0),
867 };
868
869 /*
870 * Only used line out1 p mixer for differential output
871 */
872 static const struct snd_kcontrol_new es8396_lout1_mixer_controls[] = {
873 SOC_DAPM_SINGLE("LDAC2LO1MIXP Switch", SND_SOC_NOPM,
874 5, 1, 0),
875 SOC_DAPM_SINGLE("LAXMIX2LO1MIXP Switch",
876 ES8396_LNOUT_LO1EN_LO1MIX_REG4A, 4, 1, 0),
877 SOC_DAPM_SINGLE("LLNMIX2LO1MIXP Switch",
878 ES8396_LNOUT_LO1EN_LO1MIX_REG4A, 3, 1, 0),
879 SOC_DAPM_SINGLE("LMNMIX2LO1MIXP Switch",
880 ES8396_LNOUT_LO1EN_LO1MIX_REG4A, 2, 1, 0),
881 SOC_DAPM_SINGLE("RO1INV2LO1MIXP Switch",
882 ES8396_LNOUT_LO1EN_LO1MIX_REG4A, 1, 1, 0),
883 };
884
885 static const struct snd_kcontrol_new es8396_rout1_mixer_controls[] = {
886 SOC_DAPM_SINGLE("RDAC2RO1MIXN Switch", SND_SOC_NOPM,
887 5, 1, 0),
888 SOC_DAPM_SINGLE("RAXMIX2RO1MIXN Switch",
889 ES8396_LNOUT_RO1EN_RO1MIX_REG4B, 4, 1, 0),
890 SOC_DAPM_SINGLE("RLNMIX2RO1MIXN Switch",
891 ES8396_LNOUT_RO1EN_RO1MIX_REG4B, 3, 1, 0),
892 SOC_DAPM_SINGLE("RMNMIX2RO1MIXN Switch",
893 ES8396_LNOUT_RO1EN_RO1MIX_REG4B, 2, 1, 0),
894 SOC_DAPM_SINGLE("LO1INV2RO1MIXN Switch",
895 ES8396_LNOUT_RO1EN_RO1MIX_REG4B, 1, 1, 0),
896 };
897
898 /*
899 *left LNMIX mixer
900 */
901 static const struct snd_kcontrol_new es8396_lnmix_l_mixer_controls[] = {
902 SOC_DAPM_SINGLE("AINL2LLNMIX Switch", ES8396_LN_MIXER_REG32, 7, 1, 0),
903 SOC_DAPM_SINGLE("LLNMUX2LLNMIX Switch", ES8396_LN_MIXER_REG32, 6, 1, 0),
904 SOC_DAPM_SINGLE("MIC1P2LLNMIX Switch", ES8396_LN_MIXER_REG32, 5, 1, 0),
905 SOC_DAPM_SINGLE("PMICDSE2LLNMIX Switch", ES8396_LN_MIXER_REG32, 4, 1, 0),
906 };
907
908 /*
909 *right LNMIX mixer
910 */
911 static const struct snd_kcontrol_new es8396_lnmix_r_mixer_controls[] = {
912 SOC_DAPM_SINGLE("AINR2RLNMIX Switch", ES8396_LN_MIXER_REG32, 3, 1, 0),
913 SOC_DAPM_SINGLE("RLNMUX2RLNMIX Switch", ES8396_LN_MIXER_REG32, 2, 1, 0),
914 SOC_DAPM_SINGLE("MIC1N2LLNMIX Switch", ES8396_LN_MIXER_REG32, 1, 1, 0),
915 SOC_DAPM_SINGLE("NMICDSE2RLNMIX Switch", ES8396_LN_MIXER_REG32, 0, 1, 0),
916 };
917
918 /*
919 *left AXMIX mixer
920 */
921 static const struct snd_kcontrol_new es8396_axmix_l_mixer_controls[] = {
922 SOC_DAPM_SINGLE("LAXMUX2LAXMIX Switch", ES8396_AX_MIXER_REG2E, 7, 1, 0),
923 SOC_DAPM_SINGLE("MONOP2LAXMIX Switch", ES8396_AX_MIXER_REG2E, 6, 1, 0),
924 SOC_DAPM_SINGLE("MIC2P2LAXMIX Switch", ES8396_AX_MIXER_REG2E, 5, 1, 0),
925 SOC_DAPM_SINGLE("PMICDSE2LAXMIX Switch", ES8396_AX_MIXER_REG2E, 4, 1, 0),
926 };
927
928 /*
929 *right AXMIX mixer
930 */
931 static const struct snd_kcontrol_new es8396_axmix_r_mixer_controls[] = {
932 SOC_DAPM_SINGLE("RAXMUX2RAXMIX Switch", ES8396_AX_MIXER_REG2E, 3, 1, 0),
933 SOC_DAPM_SINGLE("MONON2RAXMIX Switch", ES8396_AX_MIXER_REG2E, 2, 1, 0),
934 SOC_DAPM_SINGLE("MIC2N2RAXMIX Switch", ES8396_AX_MIXER_REG2E, 1, 1, 0),
935 SOC_DAPM_SINGLE("NMICDSE2RAXMIX Switch", ES8396_AX_MIXER_REG2E, 0, 1, 0),
936 };
937
938 /*
939 *left MNMIX mixer
940 */
941 static const struct snd_kcontrol_new es8396_mnmix_l_mixer_controls[] = {
942 SOC_DAPM_SINGLE("LDAC2LMNMIX Switch", ES8396_MN_MIXER_REG36, 7, 1, 0),
943 SOC_DAPM_SINGLE("MONOP2LMNMIX Switch", ES8396_MN_MIXER_REG36, 6, 1, 0),
944 SOC_DAPM_SINGLE("AINL2LMNMIX Switch", ES8396_MN_MIXER_REG36, 5, 1, 0),
945 };
946
947 /*
948 *right MNMIX mixer
949 */
950 static const struct snd_kcontrol_new es8396_mnmix_r_mixer_controls[] = {
951 SOC_DAPM_SINGLE("RDAC2RMNMIX Switch", ES8396_MN_MIXER_REG36, 3, 1, 0),
952 SOC_DAPM_SINGLE("MONON2RMNMIX Switch", ES8396_MN_MIXER_REG36, 2, 1, 0),
953 SOC_DAPM_SINGLE("AINR2RMNMIX Switch", ES8396_MN_MIXER_REG36, 1, 1, 0),
954 };
955
956 /*
957 * Left Record Mixer
958 */
959 static const struct snd_kcontrol_new es8396_capture_l_mixer_controls[] = {
960 SOC_DAPM_SINGLE("RLNMIX2LPGA Switch", ES8396_ADC_LPGA_MIXER_REG62, 7, 1, 0),
961 SOC_DAPM_SINGLE("RAXMIX2LPGA Switch", ES8396_ADC_LPGA_MIXER_REG62, 6, 1, 0),
962 SOC_DAPM_SINGLE("RMNMIX2LPGA Switch", ES8396_ADC_LPGA_MIXER_REG62, 5, 1, 0),
963 SOC_DAPM_SINGLE("LMNMIX2LPGA Switch", ES8396_ADC_LPGA_MIXER_REG62, 4, 1, 0),
964 SOC_DAPM_SINGLE("LLNMIX2LPGA Switch", ES8396_ADC_LPGA_MIXER_REG62, 3, 1, 0),
965
966 };
967
968 /*
969 * Right Record Mixer
970 */
971 static const struct snd_kcontrol_new es8396_capture_r_mixer_controls[] = {
972 SOC_DAPM_SINGLE("RLNMIX2RPGA Switch", ES8396_ADC_RPGA_MIXER_REG63, 7, 1, 0),
973 SOC_DAPM_SINGLE("RAXMIX2RPGA Switch", ES8396_ADC_RPGA_MIXER_REG63, 6, 1, 0),
974 SOC_DAPM_SINGLE("RMNMIX2RPGA Switch", ES8396_ADC_RPGA_MIXER_REG63, 5, 1, 0),
975 SOC_DAPM_SINGLE("LMNMIX2RPGA Switch", ES8396_ADC_RPGA_MIXER_REG63, 4, 1, 0),
976 SOC_DAPM_SINGLE("LAXMIX2RPGA Switch", ES8396_ADC_RPGA_MIXER_REG63, 3, 1, 0),
977 };
978
979 static const struct snd_kcontrol_new es8396_adc_controls =
980 SOC_DAPM_SINGLE("Switch", ES8396_ADC_CSM_REG53, 6, 1, 1);
981
982 /*
983 * MIC INPUT MUX
984 */
985 static const struct snd_kcontrol_new es8396_micin_mux_controls =
986 SOC_DAPM_SINGLE("Switch", ES8396_SYS_MIC_IBIAS_EN_REG75, 1, 1, 0);
987
988 /*
989 * left LN MUX
990 */
991 static const char *const es8396_left_lnmux_txt[] = {
992 "NO IN",
993 "RPGAP",
994 "LPGAP",
995 "MONOP",
996 "AINL"
997 };
998
999 static const unsigned int es8396_left_lnmux_values[] = {
1000 0, 1, 2, 4, 8
1001 };
1002
1003 static const struct soc_enum es8396_left_lnmux_enum =
1004 SOC_VALUE_ENUM_SINGLE(ES8396_ADC_LN_MUX_REG64, 0, 15,
1005 ARRAY_SIZE(es8396_left_lnmux_txt),
1006 es8396_left_lnmux_txt,
1007 es8396_left_lnmux_values);
1008 static const struct snd_kcontrol_new es8396_left_lnmux_controls =
1009 SOC_DAPM_ENUM("Route", es8396_left_lnmux_enum);
1010
1011 /*
1012 * Right LN MUX
1013 */
1014 static const char *const es8396_right_lnmux_txt[] = {
1015 "NO IN",
1016 "RPGAP",
1017 "LPGAP",
1018 "MONON",
1019 "AINR"
1020 };
1021
1022 static const struct soc_enum es8396_right_lnmux_enum =
1023 SOC_VALUE_ENUM_SINGLE(ES8396_ADC_LN_MUX_REG64, 4, 15,
1024 ARRAY_SIZE(es8396_right_lnmux_txt),
1025 es8396_right_lnmux_txt,
1026 es8396_left_lnmux_values);
1027 static const struct snd_kcontrol_new es8396_right_lnmux_controls =
1028 SOC_DAPM_ENUM("Route", es8396_right_lnmux_enum);
1029
1030 /*
1031 * left AX MUX
1032 */
1033 static const struct soc_enum es8396_left_axmux_enum =
1034 SOC_VALUE_ENUM_SINGLE(ES8396_ADC_AX_MUX_REG65, 0, 15,
1035 ARRAY_SIZE(es8396_left_lnmux_txt),
1036 es8396_left_lnmux_txt,
1037 es8396_left_lnmux_values);
1038 static const struct snd_kcontrol_new es8396_left_axmux_controls =
1039 SOC_DAPM_ENUM("Route", es8396_left_axmux_enum);
1040
1041 /*
1042 * Right AX MUX
1043 */
1044 static const struct soc_enum es8396_right_axmux_enum =
1045 SOC_VALUE_ENUM_SINGLE(ES8396_ADC_AX_MUX_REG65, 4, 15,
1046 ARRAY_SIZE(es8396_right_lnmux_txt),
1047 es8396_right_lnmux_txt,
1048 es8396_left_lnmux_values);
1049 static const struct snd_kcontrol_new es8396_right_axmux_controls =
1050 SOC_DAPM_ENUM("Route", es8396_right_axmux_enum);
1051
1052 /*
1053 * Left SPKOUT MUX
1054 */
1055 static const char *const es8396_left_spkout_mux_txt[] = {
1056 "NO Out",
1057 "SPKR Route",
1058 "SPKL Route"
1059 };
1060
1061 static const unsigned int es8396_left_spkout_mux_values[] = {
1062 0, 1, 2
1063 };
1064
1065 static const struct soc_enum es8396_left_spkout_mux_enum =
1066 SOC_VALUE_ENUM_SINGLE(ES8396_SPK_CTRL_SRC_REG3A, 4, 3,
1067 ARRAY_SIZE(es8396_left_spkout_mux_txt),
1068 es8396_left_spkout_mux_txt,
1069 es8396_left_spkout_mux_values);
1070 static const struct snd_kcontrol_new es8396_left_spkout_mux_controls =
1071 SOC_DAPM_ENUM("Route", es8396_left_spkout_mux_enum);
1072
1073 /*
1074 * Right SPKOUT MUX
1075 */
1076 static const struct soc_enum es8396_right_spkout_mux_enum =
1077 SOC_VALUE_ENUM_SINGLE(ES8396_SPK_CTRL_SRC_REG3A, 0, 3,
1078 ARRAY_SIZE(es8396_left_spkout_mux_txt),
1079 es8396_left_spkout_mux_txt,
1080 es8396_left_spkout_mux_values);
1081 static const struct snd_kcontrol_new es8396_right_spkout_mux_controls =
1082 SOC_DAPM_ENUM("Route", es8396_right_spkout_mux_enum);
1083
1084 /*
1085 * SPKLDO POWER SWITCH
1086 */
1087 static const struct snd_kcontrol_new es8396_spkldo_pwrswitch_controls =
1088 SOC_DAPM_SINGLE("Switch", ES8396_DAMP_CLK_DIV_REG0C, 1, 1, 1);
1089
1090 /*
1091 * Dmic MUX
1092 */
1093 static const char *const es8396_dmic_mux_txt[] = {
1094 /* 0 can be used for stereo amic */
1095 "dmic disable,use adc",
1096 "ldata use ladc,rdata use ldmic at low clk",
1097 "ldata use ladc,rdata use rdmic at low clk",
1098 "ldata use ladc,rdata use rdmic at high clk",
1099 "ldata use ldmic at high clk,rdata use radc",
1100 "ldata use ldmic at high clk,rdata use ldmic at low clk",
1101 /* can be used for stereo dmic */
1102 "ldata use ldmic at high clk,rdata use rdmic at low clk",
1103 "ldata use ldmic at high clk,rdata use rdmic at high clk",
1104 "ldata use rdmic at high clk,rdata use radc",
1105 /* can be used for stereo dmic */
1106 "ldata use rdmic at high clk,rdata use ldmic at low clk",
1107 "ldata use rdmic at high clk,rdata use rdmic at low clk",
1108 "ldata use rdmic at high clk,rdata use rdmic at high clk",
1109 "ldata use ldmic at low clk,rdata use radc",
1110 "ldata use ldmic at low clk,rdata use ldmic at low clk",
1111 "ldata use ldmic at low clk,rdata use rdmic at low clk",
1112 /* can be used for stereo dmic */
1113 "ldata use ldmic at low clk,rdata use rdmic at high clk",
1114 };
1115
1116 static const unsigned int es8396_dmic_mux_values[] = {
1117 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
1118 };
1119
1120 static const struct soc_enum es8396_dmic_mux_enum =
1121 SOC_VALUE_ENUM_SINGLE(ES8396_ADC_DMIC_RAMPRATE_REG54, 4, 15,
1122 ARRAY_SIZE(es8396_dmic_mux_txt),
1123 es8396_dmic_mux_txt,
1124 es8396_dmic_mux_values);
1125 static const struct snd_kcontrol_new es8396_dmic_mux_controls =
1126 SOC_DAPM_ENUM("Route", es8396_dmic_mux_enum);
1127
1128 /*
1129 * Digital mixer1 left
1130 */
1131 static const char *const es8396_left_digital_mixer_txt[] = {
1132 "left SDP1 in",
1133 "left SDP2 in",
1134 "left SDP3 in",
1135 "left ADC out",
1136 "right SDP1 in",
1137 "right SDP2 in",
1138 "right SDP3 in",
1139 "right ADC out"
1140 };
1141
1142 static const unsigned int es8396_left_digital_mixer_values[] = {
1143 0, 1, 2, 3, 4, 5, 6, 7
1144 };
1145
1146 static const struct soc_enum es8396_left_digital_mixer_enum =
1147 SOC_VALUE_ENUM_SINGLE(ES8396_DMIX_SRC_1_REG18, 4, 15,
1148 ARRAY_SIZE(es8396_left_digital_mixer_txt),
1149 es8396_left_digital_mixer_txt,
1150 es8396_left_digital_mixer_values);
1151 static const struct snd_kcontrol_new es8396_left_digital_mixer_controls =
1152 SOC_DAPM_ENUM("Route", es8396_left_digital_mixer_enum);
1153
1154 /*
1155 * Digital mixer1 right
1156 */
1157 static const char *const es8396_right_digital_mixer_txt[] = {
1158 "right SDP1 in",
1159 "right SDP2 in",
1160 "right SDP3 in",
1161 "right ADC out",
1162 "left SDP1 in",
1163 "left SDP2 in",
1164 "left SDP3 in",
1165 "left ADC out"
1166 };
1167
1168 static const struct soc_enum es8396_right_digital_mixer_enum =
1169 SOC_VALUE_ENUM_SINGLE(ES8396_DMIX_SRC_1_REG18, 0, 15,
1170 ARRAY_SIZE(es8396_right_digital_mixer_txt),
1171 es8396_right_digital_mixer_txt,
1172 es8396_left_digital_mixer_values);
1173 static const struct snd_kcontrol_new es8396_right_digital_mixer_controls =
1174 SOC_DAPM_ENUM("Route", es8396_right_digital_mixer_enum);
1175
1176 /*
1177 * Digital mixer2 left
1178 */
1179 static const struct soc_enum es8396_left_digital2_mixer_enum =
1180 SOC_VALUE_ENUM_SINGLE(ES8396_DMIX_SRC_2_REG19, 4, 15,
1181 ARRAY_SIZE(es8396_left_digital_mixer_txt),
1182 es8396_left_digital_mixer_txt,
1183 es8396_left_digital_mixer_values);
1184 static const struct snd_kcontrol_new es8396_left_digital2_mixer_controls =
1185 SOC_DAPM_ENUM("Route", es8396_left_digital2_mixer_enum);
1186
1187 /*
1188 * Digital mixer2 right
1189 */
1190 static const struct soc_enum es8396_right_digital2_mixer_enum =
1191 SOC_VALUE_ENUM_SINGLE(ES8396_DMIX_SRC_2_REG19, 0, 15,
1192 ARRAY_SIZE(es8396_right_digital_mixer_txt),
1193 es8396_right_digital_mixer_txt,
1194 es8396_left_digital_mixer_values);
1195 static const struct snd_kcontrol_new es8396_right_digital2_mixer_controls =
1196 SOC_DAPM_ENUM("Route", es8396_right_digital2_mixer_enum);
1197
1198 /*
1199 * equalizer clk mux
1200 */
1201 static const char *const es8396_eq_clk_mux_txt[] = {
1202 "from dac mclk",
1203 "from adc mclk",
1204 "from clk1",
1205 "from clk2"
1206 };
1207
1208 static const unsigned int es8396_eq_clk_mux_values[] = {
1209 0, 1, 2, 3
1210 };
1211
1212 static const struct soc_enum es8396_eq_clk_mux_enum =
1213 SOC_VALUE_ENUM_SINGLE(ES8396_EQ_CLK_OSR_SEL_REG1C, 4, 3,
1214 ARRAY_SIZE(es8396_eq_clk_mux_txt),
1215 es8396_eq_clk_mux_txt,
1216 es8396_eq_clk_mux_values);
1217 static const struct snd_kcontrol_new es8396_eq_clk_mux_controls =
1218 SOC_DAPM_ENUM("Route", es8396_eq_clk_mux_enum);
1219
1220 /*
1221 * equalizer osr mux
1222 */
1223 static const char *const es8396_eq_osr_mux_txt[] = {
1224 "1FS OSR",
1225 "2FS OSR",
1226 "3FS OSR",
1227 "4FS OSR",
1228 "5FS OSR",
1229 "6FS OSR"
1230 };
1231
1232 static const unsigned int es8396_eq_osr_mux_values[] = {
1233 0, 1, 2, 3, 4, 5
1234 };
1235
1236 static const struct soc_enum es8396_eq_osr_mux_enum =
1237 SOC_VALUE_ENUM_SINGLE(ES8396_EQ_CLK_OSR_SEL_REG1C, 0, 7,
1238 ARRAY_SIZE(es8396_eq_osr_mux_txt),
1239 es8396_eq_osr_mux_txt,
1240 es8396_eq_osr_mux_values);
1241 static const struct snd_kcontrol_new es8396_eq_osr_mux_controls =
1242 SOC_DAPM_ENUM("Route", es8396_eq_osr_mux_enum);
1243
1244 /*
1245 * DAC source mux
1246 */
1247 static const char *const es8396_dac_src_mux_txt[] = {
1248 "SDP1 in",
1249 "SDP2 in",
1250 "SDP3 in",
1251 "ADC out",
1252 "EQ stereo",
1253 "EQ left",
1254 "EQ right",
1255 };
1256
1257 static const unsigned int es8396_dac_src_mux_values[] = {
1258 0, 1, 2, 3, 4, 5, 6
1259 };
1260
1261 static const struct soc_enum es8396_dac_src_mux_enum =
1262 SOC_VALUE_ENUM_SINGLE(ES8396_DAC_SRC_SDP1O_SRC_REG1A, 4, 7,
1263 ARRAY_SIZE(es8396_dac_src_mux_txt),
1264 es8396_dac_src_mux_txt,
1265 es8396_dac_src_mux_values);
1266 static const struct snd_kcontrol_new es8396_dac_src_mux_controls =
1267 SOC_DAPM_ENUM("Route", es8396_dac_src_mux_enum);
1268
1269 /*
1270 * I2S1 out mux
1271 */
1272 static const char *const es8396_i2s1_out_mux_txt[] = {
1273 "ADC out",
1274 "SDP1 in",
1275 "SDP2 in",
1276 "SDP3 in",
1277 "EQ stereo",
1278 "EQ left",
1279 "EQ right",
1280 };
1281
1282 static const unsigned int es8396_i2s1_out_mux_values[] = {
1283 0, 1, 2, 3, 4, 5, 6
1284 };
1285
1286 static const struct soc_enum es8396_i2s1_out_mux_enum =
1287 SOC_VALUE_ENUM_SINGLE(ES8396_DAC_SRC_SDP1O_SRC_REG1A, 0, 7,
1288 ARRAY_SIZE(es8396_i2s1_out_mux_txt),
1289 es8396_i2s1_out_mux_txt,
1290 es8396_i2s1_out_mux_values);
1291 static const struct snd_kcontrol_new es8396_i2s1_out_mux_controls =
1292 SOC_DAPM_ENUM("Route", es8396_i2s1_out_mux_enum);
1293
1294 /*
1295 * I2S2 out mux
1296 */
1297 static const struct soc_enum es8396_i2s2_out_mux_enum =
1298 SOC_VALUE_ENUM_SINGLE(ES8396_SDP2O_SDP3O_SRC_REG1B, 4, 7,
1299 ARRAY_SIZE(es8396_i2s1_out_mux_txt),
1300 es8396_i2s1_out_mux_txt,
1301 es8396_i2s1_out_mux_values);
1302 static const struct snd_kcontrol_new es8396_i2s2_out_mux_controls =
1303 SOC_DAPM_ENUM("Route", es8396_i2s2_out_mux_enum);
1304
1305 /*
1306 * I2S3 out mux
1307 */
1308 static const struct soc_enum es8396_i2s3_out_mux_enum =
1309 SOC_VALUE_ENUM_SINGLE(ES8396_SDP2O_SDP3O_SRC_REG1B, 0, 7,
1310 ARRAY_SIZE(es8396_i2s1_out_mux_txt),
1311 es8396_i2s1_out_mux_txt,
1312 es8396_i2s1_out_mux_values);
1313 static const struct snd_kcontrol_new es8396_i2s3_out_mux_controls =
1314 SOC_DAPM_ENUM("Route", es8396_i2s3_out_mux_enum);
1315
1316 static const struct snd_soc_dapm_widget es8396_dapm_widgets[] = {
1317 SND_SOC_DAPM_INPUT("DMIC"),
1318 SND_SOC_DAPM_INPUT("LINP"),
1319 SND_SOC_DAPM_INPUT("RINN"),
1320 SND_SOC_DAPM_INPUT("MONOINP"),
1321 SND_SOC_DAPM_INPUT("MONOINN"),
1322 SND_SOC_DAPM_INPUT("AINL"),
1323 SND_SOC_DAPM_INPUT("AINR"),
1324 SND_SOC_DAPM_INPUT("MIC"),
1325 SND_SOC_DAPM_SUPPLY("MIC Bias", SND_SOC_NOPM, 0, 0,
1326 micbias_event,
1327 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1328 /*
1329 * AIF OUT AND MUX
1330 */
1331 SND_SOC_DAPM_AIF_OUT("VOICESDPOL", "SDP1 Capture", 0,
1332 ES8396_SDP1_OUT_FMT_REG20, 6, 1),
1333 SND_SOC_DAPM_AIF_OUT("VOICESDPOR", "SDP1 Capture", 0,
1334 ES8396_SDP1_OUT_FMT_REG20, 6, 1),
1335 SND_SOC_DAPM_MUX("VOICESDPO Mux", SND_SOC_NOPM, 0, 0, &es8396_i2s1_out_mux_controls),
1336 SND_SOC_DAPM_AIF_OUT("MASTERSDPOL", "SDP2 Capture", 0,
1337 ES8396_SDP2_OUT_FMT_REG23, 6, 1),
1338 SND_SOC_DAPM_AIF_OUT("MASTERSDPOR", "SDP2 Capture", 0,
1339 ES8396_SDP2_OUT_FMT_REG23, 6, 1),
1340 SND_SOC_DAPM_MUX("MASTERSDPO Mux", SND_SOC_NOPM, 0, 0,
1341 &es8396_i2s2_out_mux_controls),
1342
1343 SND_SOC_DAPM_AIF_OUT("AUXSDPOL", "SDP3 Capture", 0,
1344 ES8396_SDP3_OUT_FMT_REG25, 6, 1),
1345 SND_SOC_DAPM_AIF_OUT("AUXSDPOR", "SDP3 Capture", 0,
1346 ES8396_SDP3_OUT_FMT_REG25, 6, 1),
1347 SND_SOC_DAPM_MUX("AUXSDPO Mux", SND_SOC_NOPM, 0, 0,
1348 &es8396_i2s3_out_mux_controls),
1349
1350 SND_SOC_DAPM_MIXER("VOICEOUT AIF Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
1351 SND_SOC_DAPM_MIXER("MASTEROUT AIF Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
1352 SND_SOC_DAPM_MIXER("AUXOUT AIF Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
1353
1354 /* capature */
1355
1356 /*
1357 *left and right mixer
1358 */
1359 SND_SOC_DAPM_MIXER_NAMED_CTL("PGA Left Mix", SND_SOC_NOPM, 0, 0,
1360 &es8396_capture_l_mixer_controls[0],
1361 ARRAY_SIZE
1362 (es8396_capture_l_mixer_controls)),
1363 SND_SOC_DAPM_MIXER_NAMED_CTL("PGA Right Mix", SND_SOC_NOPM, 0, 0,
1364 &es8396_capture_r_mixer_controls[0],
1365 ARRAY_SIZE
1366 (es8396_capture_r_mixer_controls)),
1367
1368 SND_SOC_DAPM_PGA("LPGA P", ES8396_ADC_ANALOG_CTRL_REG5E, 4, 1, NULL, 0),
1369 SND_SOC_DAPM_PGA("RPGA P", ES8396_ADC_ANALOG_CTRL_REG5E, 5, 1, NULL, 0),
1370
1371 SND_SOC_DAPM_ADC("ADC Left", NULL, ES8396_ADC_ANALOG_CTRL_REG5E, 2, 1),
1372 SND_SOC_DAPM_ADC("ADC Right", NULL, ES8396_ADC_ANALOG_CTRL_REG5E, 3, 1),
1373 SND_SOC_DAPM_SWITCH_E("ADC_1", SND_SOC_NOPM, 0, 0,
1374 &es8396_adc_controls, adc_event,
1375 SND_SOC_DAPM_PRE_PMD),
1376
1377 /*
1378 * Analog MIC Muxes
1379 */
1380 SND_SOC_DAPM_SWITCH("AMIC Mux", ES8396_SYS_MIC_IBIAS_EN_REG75, 0, 1,
1381 &es8396_micin_mux_controls),
1382 SND_SOC_DAPM_PGA("MIC BOOST", SND_SOC_NOPM, 0, 0, NULL, 0),
1383
1384 /* LN,AX Muxes */
1385 /*
1386 * LN MUX
1387 */
1388 SND_SOC_DAPM_MUX("LLN Mux", SND_SOC_NOPM, 0, 0,
1389 &es8396_left_lnmux_controls),
1390 SND_SOC_DAPM_MUX("RLN Mux", SND_SOC_NOPM, 0, 0,
1391 &es8396_right_lnmux_controls),
1392 /*
1393 * AX MUX
1394 */
1395 SND_SOC_DAPM_MUX("LAX Mux", SND_SOC_NOPM, 0, 0,
1396 &es8396_left_axmux_controls),
1397 SND_SOC_DAPM_MUX("RAX Mux", SND_SOC_NOPM, 0, 0,
1398 &es8396_right_axmux_controls),
1399 /*
1400 * AIF IN
1401 */
1402 SND_SOC_DAPM_AIF_IN("VOICESDPIL", "SDP1 Playback", 0,
1403 ES8396_SDP1_IN_FMT_REG1F, 6, 1),
1404 SND_SOC_DAPM_AIF_IN("VOICESDPIR", "SDP1 Playback", 0,
1405 ES8396_SDP1_IN_FMT_REG1F, 6, 1),
1406 SND_SOC_DAPM_AIF_IN("MASTERSDPIL", "SDP2 Playback", 0,
1407 SND_SOC_NOPM, 6, 1),
1408 SND_SOC_DAPM_AIF_IN("MASTERSDPIR", "SDP2 Playback", 0,
1409 SND_SOC_NOPM, 6, 1),
1410 SND_SOC_DAPM_AIF_IN("AUXSDPIL", "SDP3 Playback", 0,
1411 ES8396_SDP3_IN_FMT_REG24, 6, 1),
1412 SND_SOC_DAPM_AIF_IN("AUXSDPIR", "SDP3 Playback", 0,
1413 ES8396_SDP3_IN_FMT_REG24, 6, 1),
1414 SND_SOC_DAPM_MIXER("VOICEIN AIF Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
1415 SND_SOC_DAPM_MIXER("MASTERIN AIF Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
1416 SND_SOC_DAPM_MIXER("AUXIN AIF Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
1417 /*
1418 * Digital mixer1,2
1419 */
1420 SND_SOC_DAPM_MUX("LDMIX1 Mux", SND_SOC_NOPM, 0, 0,
1421 &es8396_left_digital_mixer_controls),
1422 SND_SOC_DAPM_MUX("RDMIX1 Mux", SND_SOC_NOPM, 0, 0,
1423 &es8396_right_digital_mixer_controls),
1424 SND_SOC_DAPM_MUX("LDMIX2 Mux", SND_SOC_NOPM, 0, 0,
1425 &es8396_left_digital2_mixer_controls),
1426 SND_SOC_DAPM_MUX("RDMIX2 Mux", SND_SOC_NOPM, 0, 0,
1427 &es8396_right_digital2_mixer_controls),
1428
1429 SND_SOC_DAPM_MIXER("Digital Left Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
1430 SND_SOC_DAPM_MIXER("Digital Right Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
1431 SND_SOC_DAPM_MIXER("Equalizer", SND_SOC_NOPM, 0, 0, NULL, 0),
1432
1433 SND_SOC_DAPM_MUX("DACSRC Mux", SND_SOC_NOPM, 0, 0,
1434 &es8396_dac_src_mux_controls),
1435 /*
1436 * DAC
1437 */
1438 SND_SOC_DAPM_SWITCH("DAC_1", SND_SOC_NOPM, 0, 0,
1439 &es8396_dac_controls),
1440
1441 SND_SOC_DAPM_DAC("Left DAC", NULL, SND_SOC_NOPM, 0, 0),
1442 SND_SOC_DAPM_DAC("Right DAC", NULL, SND_SOC_NOPM, 0, 0),
1443
1444 /*
1445 * mixerMono
1446 */
1447 SND_SOC_DAPM_MIXER("LMONIN Mix", ES8396_MN_MIXER_BOOST_REG37, 4, 1,
1448 &es8396_mnmix_l_mixer_controls[0],
1449 ARRAY_SIZE(es8396_mnmix_l_mixer_controls)),
1450 SND_SOC_DAPM_PGA("LMONINMIX PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
1451 SND_SOC_DAPM_MIXER("RMONIN Mix", ES8396_MN_MIXER_BOOST_REG37, 0, 1,
1452 &es8396_mnmix_r_mixer_controls[0],
1453 ARRAY_SIZE(es8396_mnmix_r_mixer_controls)),
1454 SND_SOC_DAPM_PGA("RMONINMIX PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
1455 /*
1456 * mixerLN
1457 */
1458 SND_SOC_DAPM_MIXER("LLNIN Mix", ES8396_LN_MIXER_BOOST_REG33, 4, 1,
1459 &es8396_lnmix_l_mixer_controls[0],
1460 ARRAY_SIZE(es8396_lnmix_l_mixer_controls)),
1461 SND_SOC_DAPM_PGA("LLNINMIX PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
1462 SND_SOC_DAPM_MIXER("RLNIN Mix", ES8396_LN_MIXER_BOOST_REG33, 0, 1,
1463 &es8396_lnmix_r_mixer_controls[0],
1464 ARRAY_SIZE(es8396_lnmix_r_mixer_controls)),
1465 SND_SOC_DAPM_PGA("RLNINMIX PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
1466 /*
1467 * mixerAX
1468 */
1469 SND_SOC_DAPM_MIXER("LAXIN Mix", ES8396_AX_MIXER_BOOST_REG2F, 4, 1,
1470 &es8396_axmix_l_mixer_controls[0],
1471 ARRAY_SIZE(es8396_axmix_l_mixer_controls)),
1472 SND_SOC_DAPM_PGA("LAXINMIX PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
1473 SND_SOC_DAPM_MIXER("RAXIN Mix", ES8396_AX_MIXER_BOOST_REG2F, 0, 1,
1474 &es8396_axmix_r_mixer_controls[0],
1475 ARRAY_SIZE(es8396_axmix_r_mixer_controls)),
1476 SND_SOC_DAPM_PGA("RAXINMIX PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
1477 /*
1478 * mixerLNOUT
1479 */
1480 SND_SOC_DAPM_MIXER("LOUT1 Mix", SND_SOC_NOPM, 0, 0,
1481 &es8396_lout1_mixer_controls[0],
1482 ARRAY_SIZE(es8396_lout1_mixer_controls)),
1483 SND_SOC_DAPM_PGA("LNOUTMIX1 PGA", SND_SOC_NOPM, 6, 0,
1484 NULL, 0),
1485 SND_SOC_DAPM_MIXER("ROUT1 Mix", SND_SOC_NOPM, 0, 0,
1486 &es8396_rout1_mixer_controls[0],
1487 ARRAY_SIZE(es8396_rout1_mixer_controls)),
1488 SND_SOC_DAPM_PGA("RNOUTMIX1 PGA", SND_SOC_NOPM, 6, 0,
1489 NULL, 0),
1490
1491 /*
1492 * mixerMNOUT
1493 */
1494 SND_SOC_DAPM_MIXER("MNOUTP Mix", SND_SOC_NOPM, 0, 0,
1495 &es8396_mono_p_mixer_controls[0],
1496 ARRAY_SIZE(es8396_mono_p_mixer_controls)),
1497 SND_SOC_DAPM_PGA("MNOUTP PGA", ES8396_MONOHP_P_BOOST_MUTE_REG48, 7, 0,
1498 NULL, 0),
1499 SND_SOC_DAPM_MIXER("MNOUTN Mix", SND_SOC_NOPM, 0, 0,
1500 &es8396_mono_n_mixer_controls[0],
1501 ARRAY_SIZE(es8396_mono_n_mixer_controls)),
1502 SND_SOC_DAPM_PGA("MNOUTN PGA", ES8396_MONOHP_N_BOOST_MUTE_REG49, 7, 0,
1503 NULL, 0),
1504
1505 /*
1506 * mixerHP
1507 */
1508 /*
1509 * SND_SOC_DAPM_MIXER("HPL Mix", ES8396_HP_MIXER_BOOST_REG2B, 4, 1,
1510 */
1511 SND_SOC_DAPM_MIXER("HPL Mix", SND_SOC_NOPM, 6, 0,
1512 &es8396_hpl_mixer_controls[0],
1513 ARRAY_SIZE(es8396_hpl_mixer_controls)),
1514 /*
1515 * SND_SOC_DAPM_MIXER("HPR Mix", ES8396_HP_MIXER_BOOST_REG2B, 0, 1,
1516 */
1517 SND_SOC_DAPM_MIXER("HPR Mix", SND_SOC_NOPM, 2, 0,
1518 &es8396_hpr_mixer_controls[0],
1519 ARRAY_SIZE(es8396_hpr_mixer_controls)),
1520 SND_SOC_DAPM_SWITCH_E("HP Amp", SND_SOC_NOPM, 0, 0,
1521 &hp_amp_ctl, hpamp_event,
1522 SND_SOC_DAPM_PRE_PMU),
1523 /*
1524 * mixerSPK
1525 */
1526 SND_SOC_DAPM_MIXER("SPKL Mix", SND_SOC_NOPM, 0, 0,
1527 &es8396_speaker_lmixer_controls[0],
1528 ARRAY_SIZE(es8396_speaker_lmixer_controls)),
1529 SND_SOC_DAPM_MIXER("SPKR Mix", SND_SOC_NOPM, 0, 0,
1530 &es8396_speaker_rmixer_controls[0],
1531 ARRAY_SIZE(es8396_speaker_rmixer_controls)),
1532 SND_SOC_DAPM_SWITCH_E("SPK Amp", SND_SOC_NOPM, 0, 0,
1533 &es8396_spkldo_pwrswitch_controls, classd_event,
1534 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1535
1536 SND_SOC_DAPM_OUTPUT("MONOOUTP"),
1537 SND_SOC_DAPM_OUTPUT("MONOOUTN"),
1538 SND_SOC_DAPM_OUTPUT("HPL"),
1539 SND_SOC_DAPM_OUTPUT("HPR"),
1540 SND_SOC_DAPM_OUTPUT("SPKOUTL"),
1541 SND_SOC_DAPM_OUTPUT("SPKOUTR"),
1542 SND_SOC_DAPM_OUTPUT("LOUTP"),
1543 SND_SOC_DAPM_OUTPUT("ROUTN"),
1544 };
1545
1546 static const struct snd_soc_dapm_route es8396_dapm_routes[] = {
1547 /* lln mux */
1548 {"LLN Mux", "RPGAP", "RPGA P"},
1549 {"LLN Mux", "LPGAP", "LPGA P"},
1550 {"LLN Mux", "MONOP", "MONOINP"},
1551 {"LLN Mux", "AINL", "AINL"},
1552
1553 /* rln mux */
1554 {"RLN Mux", "RPGAP", "RPGA P"},
1555 {"RLN Mux", "LPGAP", "LPGA P"},
1556 {"RLN Mux", "MONON", "MONOINN"},
1557 {"RLN Mux", "AINR", "AINR"},
1558
1559 /* lax mux */
1560 {"LAX Mux", "RPGAP", "RPGA P"},
1561 {"LAX Mux", "LPGAP", "LPGA P"},
1562 {"LAX Mux", "MONOP", "MONOINP"},
1563 {"LAX Mux", "AINL", "AINL"},
1564
1565 /* rax mux */
1566 {"RAX Mux", "RPGAP", "RPGA P"},
1567 {"RAX Mux", "LPGAP", "LPGA P"},
1568 {"RAX Mux", "MONON", "MONOINN"},
1569 {"RAX Mux", "AINR", "AINR"},
1570
1571 /* Left, right PGA */
1572 {"LPGA P", NULL, "PGA Left Mix"},
1573 {"RPGA P", NULL, "PGA Right Mix"},
1574
1575 {"PGA Left Mix", "RLNMIX2LPGA Switch", "RLNINMIX PGA"},
1576 {"PGA Left Mix", "RAXMIX2LPGA Switch", "RAXINMIX PGA"},
1577 {"PGA Left Mix", "RMNMIX2LPGA Switch", "RMONINMIX PGA"},
1578 {"PGA Left Mix", "LMNMIX2LPGA Switch", "LMONINMIX PGA"},
1579 {"PGA Left Mix", "LLNMIX2LPGA Switch", "LLNINMIX PGA"},
1580
1581 {"PGA Right Mix", "RLNMIX2RPGA Switch", "RLNINMIX PGA"},
1582 {"PGA Right Mix", "RAXMIX2RPGA Switch", "RAXINMIX PGA"},
1583 {"PGA Right Mix", "RMNMIX2RPGA Switch", "RMONINMIX PGA"},
1584 {"PGA Right Mix", "LMNMIX2RPGA Switch", "LMONINMIX PGA"},
1585 {"PGA Right Mix", "LAXMIX2RPGA Switch", "LAXINMIX PGA"},
1586
1587 /* lnmix */
1588 {"RLNINMIX PGA", NULL, "RLNIN Mix"},
1589 {"LLNINMIX PGA", NULL, "LLNIN Mix"},
1590
1591 {"LLNIN Mix", "AINL2LLNMIX Switch", "AINL"},
1592 {"LLNIN Mix", "LLNMUX2LLNMIX Switch", "LLN Mux"},
1593 {"LLNIN Mix", "MIC1P2LLNMIX Switch", "MIC"},
1594 {"LLNIN Mix", "PMICDSE2LLNMIX Switch", "MIC BOOST"},
1595
1596 {"RLNIN Mix", "AINR2RLNMIX Switch", "AINR"},
1597 {"RLNIN Mix", "RLNMUX2RLNMIX Switch", "RLN Mux"},
1598 {"RLNIN Mix", "MIC1N2LLNMIX Switch", "MIC"},
1599 {"RLNIN Mix", "NMICDSE2RLNMIX Switch", "MIC BOOST"},
1600
1601 /* AXmix */
1602 {"RAXINMIX PGA", NULL, "RAXIN Mix"},
1603 {"LAXINMIX PGA", NULL, "LAXIN Mix"},
1604
1605 {"LAXIN Mix", "LAXMUX2LAXMIX Switch", "LAX Mux"},
1606 {"LAXIN Mix", "MONOP2LAXMIX Switch", "MONOINP"},
1607 {"LAXIN Mix", "MIC2P2LAXMIX Switch", "MIC"},
1608 {"LAXIN Mix", "PMICDSE2LAXMIX Switch", "MIC BOOST"},
1609
1610 {"RAXIN Mix", "RAXMUX2RAXMIX Switch", "RAX Mux"},
1611 {"RAXIN Mix", "MONON2RAXMIX Switch", "MONOINN"},
1612 {"RAXIN Mix", "MIC2N2RAXMIX Switch", "MIC"},
1613 {"RAXIN Mix", "NMICDSE2RAXMIX Switch", "MIC BOOST"},
1614
1615 /* MNmix */
1616 {"RMONINMIX PGA", NULL, "RMONIN Mix"},
1617 {"LMONINMIX PGA", NULL, "LMONIN Mix"},
1618
1619 {"LMONIN Mix", "LDAC2LMNMIX Switch", "Left DAC"},
1620 {"LMONIN Mix", "MONOP2LMNMIX Switch", "MONOINP"},
1621 {"LMONIN Mix", "AINL2LMNMIX Switch", "AINL"},
1622
1623 {"RMONIN Mix", "RDAC2RMNMIX Switch", "Right DAC"},
1624 {"RMONIN Mix", "MONON2RMNMIX Switch", "MONOINN"},
1625 {"RMONIN Mix", "AINR2RMNMIX Switch", "AINR"},
1626
1627 /* Analog mic mux */
1628 {"MIC BOOST", NULL, "AMIC Mux"},
1629
1630 {"AMIC Mux", "Switch", "MIC"},
1631 {"MIC", NULL, "MIC Bias"},
1632 /* capature */
1633 {"ADC Left", NULL, "LPGA P"},
1634 {"ADC Right", NULL, "RPGA P"},
1635
1636 {"ADC_1", "Switch", "ADC Left"},
1637 {"ADC_1", "Switch", "ADC Right"},
1638
1639 /* digital mixer */
1640 {"Equalizer", NULL, "Digital Left Mixer"},
1641 {"Equalizer", NULL, "Digital Right Mixer"},
1642
1643 {"Digital Left Mixer", NULL, "LDMIX1 Mux"},
1644 {"Digital Left Mixer", NULL, "LDMIX2 Mux"},
1645
1646 {"Digital Right Mixer", NULL, "RDMIX1 Mux"},
1647 {"Digital Right Mixer", NULL, "RDMIX2 Mux"},
1648
1649 {"LDMIX1 Mux", "left SDP1 in", "VOICESDPIL"},
1650 {"LDMIX1 Mux", "left SDP2 in", "MASTERSDPIL"},
1651 {"LDMIX1 Mux", "left SDP3 in", "AUXSDPIL"},
1652 {"LDMIX1 Mux", "left ADC out", "ADC_1"},
1653 {"LDMIX1 Mux", "right SDP1 in", "VOICESDPIR"},
1654 {"LDMIX1 Mux", "right SDP2 in", "MASTERSDPIR"},
1655 {"LDMIX1 Mux", "right SDP3 in", "AUXSDPIR"},
1656 {"LDMIX1 Mux", "right ADC out", "ADC_1"},
1657
1658 {"RDMIX1 Mux", "left SDP1 in", "VOICESDPIL"},
1659 {"RDMIX1 Mux", "left SDP2 in", "MASTERSDPIL"},
1660 {"RDMIX1 Mux", "left SDP3 in", "AUXSDPIL"},
1661 {"RDMIX1 Mux", "left ADC out", "ADC_1"},
1662 {"RDMIX1 Mux", "right SDP1 in", "VOICESDPIR"},
1663 {"RDMIX1 Mux", "right SDP2 in", "MASTERSDPIR"},
1664 {"RDMIX1 Mux", "right SDP3 in", "AUXSDPIR"},
1665 {"RDMIX1 Mux", "right ADC out", "ADC_1"},
1666
1667 {"LDMIX2 Mux", "left SDP1 in", "VOICESDPIL"},
1668 {"LDMIX2 Mux", "left SDP2 in", "MASTERSDPIL"},
1669 {"LDMIX2 Mux", "left SDP3 in", "AUXSDPIL"},
1670 {"LDMIX2 Mux", "left ADC out", "ADC_1"},
1671 {"LDMIX2 Mux", "right SDP1 in", "VOICESDPIR"},
1672 {"LDMIX2 Mux", "right SDP2 in", "MASTERSDPIR"},
1673 {"LDMIX2 Mux", "right SDP3 in", "AUXSDPIR"},
1674 {"LDMIX2 Mux", "right ADC out", "ADC_1"},
1675
1676 {"RDMIX2 Mux", "left SDP1 in", "VOICESDPIL"},
1677 {"RDMIX2 Mux", "left SDP2 in", "MASTERSDPIL"},
1678 {"RDMIX2 Mux", "left SDP3 in", "AUXSDPIL"},
1679 {"RDMIX2 Mux", "left ADC out", "ADC_1"},
1680 {"RDMIX2 Mux", "right SDP1 in", "VOICESDPIR"},
1681 {"RDMIX2 Mux", "right SDP2 in", "MASTERSDPIR"},
1682 {"RDMIX2 Mux", "right SDP3 in", "AUXSDPIR"},
1683 {"RDMIX2 Mux", "right ADC out", "ADC_1"},
1684
1685 /* VOICE/SDP1 AIF IN mixer */
1686 {"VOICEIN AIF Mixer", NULL, "VOICESDPIL"},
1687 {"VOICEIN AIF Mixer", NULL, "VOICESDPIR"},
1688 /* master/SDP2 AIF IN mixer */
1689 {"MASTERIN AIF Mixer", NULL, "MASTERSDPIL"},
1690 {"MASTERIN AIF Mixer", NULL, "MASTERSDPIR"},
1691 /* aux/SDP3 AIF IN mixer */
1692 {"AUXIN AIF Mixer", NULL, "AUXSDPIL"},
1693 {"AUXIN AIF Mixer", NULL, "AUXSDPIR"},
1694 /* VOICE/SDP1 AIF OUT */
1695 {"VOICESDPOL", NULL, "VOICESDPO Mux"},
1696 {"VOICESDPOR", NULL, "VOICESDPO Mux"},
1697
1698 {"VOICESDPO Mux", "ADC out", "ADC_1"},
1699 {"VOICESDPO Mux", "SDP1 in", "VOICEIN AIF Mixer"},
1700 {"VOICESDPO Mux", "SDP2 in", "MASTERIN AIF Mixer"},
1701 {"VOICESDPO Mux", "SDP3 in", "AUXIN AIF Mixer"},
1702 {"VOICESDPO Mux", "EQ stereo", "Equalizer"},
1703 {"VOICESDPO Mux", "EQ left", "Digital Left Mixer"},
1704 {"VOICESDPO Mux", "EQ right", "Digital Right Mixer"},
1705
1706 /* master/SDP2 AIF OUT */
1707 {"MASTERSDPOL", NULL, "MASTERSDPO Mux"},
1708 {"MASTERSDPOR", NULL, "MASTERSDPO Mux"},
1709
1710 {"MASTERSDPO Mux", "ADC out", "ADC_1"},
1711 {"MASTERSDPO Mux", "SDP1 in", "VOICEIN AIF Mixer"},
1712 {"MASTERSDPO Mux", "SDP2 in", "MASTERIN AIF Mixer"},
1713 {"MASTERSDPO Mux", "SDP3 in", "AUXIN AIF Mixer"},
1714 {"MASTERSDPO Mux", "EQ stereo", "Equalizer"},
1715 {"MASTERSDPO Mux", "EQ left", "Digital Left Mixer"},
1716 {"MASTERSDPO Mux", "EQ right", "Digital Right Mixer"},
1717
1718 /* AUX/SDP3 AIF OUT */
1719 {"AUXSDPOL", NULL, "AUXSDPO Mux"},
1720 {"AUXSDPOR", NULL, "AUXSDPO Mux"},
1721
1722 {"AUXSDPO Mux", "ADC out", "ADC_1"},
1723 {"AUXSDPO Mux", "SDP1 in", "VOICEIN AIF Mixer"},
1724 {"AUXSDPO Mux", "SDP2 in", "MASTERIN AIF Mixer"},
1725 {"AUXSDPO Mux", "SDP3 in", "AUXIN AIF Mixer"},
1726 {"AUXSDPO Mux", "EQ stereo", "Equalizer"},
1727 {"AUXSDPO Mux", "EQ left", "Digital Left Mixer"},
1728 {"AUXSDPO Mux", "EQ right", "Digital Right Mixer"},
1729
1730 /* DAC */
1731 {"Left DAC", NULL, "DAC_1"},
1732 {"Right DAC", NULL, "DAC_1"},
1733
1734 {"DAC_1", "Switch", "DACSRC Mux"},
1735
1736 {"DACSRC Mux", "SDP1 in", "VOICEIN AIF Mixer"},
1737 {"DACSRC Mux", "SDP2 in", "MASTERIN AIF Mixer"},
1738 {"DACSRC Mux", "SDP3 in", "AUXIN AIF Mixer"},
1739 {"DACSRC Mux", "ADC out", "ADC_1"},
1740 {"DACSRC Mux", "EQ stereo", "Equalizer"},
1741 {"DACSRC Mux", "EQ left", "Digital Left Mixer"},
1742 {"DACSRC Mux", "EQ right", "Digital Right Mixer"},
1743
1744 /* SPEAKER Paths */
1745 {"SPKOUTL", NULL, "SPK Amp"},
1746 {"SPKOUTR", NULL, "SPK Amp"},
1747
1748 {"SPK Amp", "Switch", "SPKL Mix"},
1749 {"SPK Amp", "Switch", "SPKR Mix"},
1750 /*
1751 * {"SPK Amp", "Switch", "SPKL Mux"},
1752 * {"SPK Amp", "Switch", "SPKR Mux"},
1753 *
1754 * {"SPKL Mux", "SPKR Route", "SPKR Mix"},
1755 * {"SPKL Mux", "SPKL Route", "SPKL Mix"},
1756 *
1757 * {"SPKR Mux", "SPKR Route", "SPKR Mix"},
1758 * {"SPKR Mux", "SPKL Route", "SPKL Mix"},
1759 */
1760 {"SPKL Mix", "LLNMUX2SPKMIX Switch", "LLN Mux"},
1761 {"SPKL Mix", "LAXMUX2SPKMIX Switch", "LAX Mux"},
1762 {"SPKL Mix", "LDAC2SPKMIX Switch", "Left DAC"},
1763
1764 {"SPKR Mix", "RLNMUX2SPKMIX Switch", "RLN Mux"},
1765 {"SPKR Mix", "RAXMUX2SPKMIX Switch", "RAX Mux"},
1766 {"SPKR Mix", "RDAC2SPKMIX Switch", "Right DAC"},
1767
1768 /* HEADPHONE Paths */
1769 {"HPL", NULL, "HP Amp"},
1770 {"HPR", NULL, "HP Amp"},
1771
1772 {"HP Amp", "Switch", "HPL Mix"},
1773 {"HP Amp", "Switch", "HPR Mix"},
1774
1775 {"HPL Mix", "LNMUX2HPMIX_L Switch", "LLN Mux"},
1776 {"HPL Mix", "AXMUX2HPMIX_L Switch", "LAX Mux"},
1777 {"HPL Mix", "DACL2HPMIX Switch", "Left DAC"},
1778
1779 {"HPR Mix", "LNMUX2HPMIX_R Switch", "RLN Mux"},
1780 {"HPR Mix", "AXMUX2HPMIX_R Switch", "RAX Mux"},
1781 {"HPR Mix", "DACR2HPMIX Switch", "Right DAC"},
1782
1783 /* EARPIECE Paths */
1784 {"MONOOUTP", NULL, "MNOUTP PGA"},
1785 {"MONOOUTN", NULL, "MNOUTN PGA"},
1786
1787 {"MNOUTP PGA", NULL, "MNOUTP Mix"},
1788 {"MNOUTN PGA", NULL, "MNOUTN Mix"},
1789
1790 {"MNOUTP Mix", "LHPMIX2MNMIXP Switch", "HPL Mix"},
1791 {"MNOUTP Mix", "RHPMIX2MNOMIXP Switch", "HPR Mix"},
1792 {"MNOUTP Mix", "RMNMIX2MNOMIXP Switch", "RMONINMIX PGA"},
1793 {"MNOUTP Mix", "RAXMIX2MNOMIXP Switch", "RAXINMIX PGA"},
1794 {"MNOUTP Mix", "LLNMIX2MNOMIXP Switch", "LLNINMIX PGA"},
1795
1796 {"MNOUTN Mix", "LMNMIX2MNMIXN Switch", "LMONINMIX PGA"},
1797 {"MNOUTN Mix", "RHPMIX2MNOMIXN Switch", "HPR Mix"},
1798 {"MNOUTN Mix", "MOPINV2MNOMIXN Switch", "MNOUTP Mix"},
1799 {"MNOUTN Mix", "LLNMIX2MNOMIXN Switch", "LLNINMIX PGA"},
1800 {"MNOUTN Mix", "LAXMIX2MNOMIXN Switch", "LAXINMIX PGA"},
1801
1802 /* LNOUT Paths */
1803 {"LOUTP", NULL, "LNOUTMIX1 PGA"},
1804 {"ROUTN", NULL, "RNOUTMIX1 PGA"},
1805
1806 {"LNOUTMIX1 PGA", NULL, "LOUT1 Mix"},
1807 {"RNOUTMIX1 PGA", NULL, "ROUT1 Mix"},
1808
1809 {"LOUT1 Mix", "LDAC2LO1MIXP Switch", "Left DAC"},
1810 {"LOUT1 Mix", "LAXMIX2LO1MIXP Switch", "LAXINMIX PGA"},
1811 {"LOUT1 Mix", "LLNMIX2LO1MIXP Switch", "LLNINMIX PGA"},
1812 {"LOUT1 Mix", "LMNMIX2LO1MIXP Switch", "LMONINMIX PGA"},
1813 {"LOUT1 Mix", "RO1INV2LO1MIXP Switch", "ROUT1 Mix"},
1814
1815 {"ROUT1 Mix", "RDAC2RO1MIXN Switch", "Right DAC"},
1816 {"ROUT1 Mix", "RAXMIX2RO1MIXN Switch", "RAXINMIX PGA"},
1817 {"ROUT1 Mix", "RLNMIX2RO1MIXN Switch", "RLNINMIX PGA"},
1818 {"ROUT1 Mix", "RMNMIX2RO1MIXN Switch", "RMONINMIX PGA"},
1819 {"ROUT1 Mix", "LO1INV2RO1MIXN Switch", "LOUT1 Mix"},
1820 };
1821
1822 struct _pll_div {
1823 u32 pll_in;
1824 u32 pll_out;
1825 u8 mclkdiv;
1826 u8 plldiv;
1827 u8 n;
1828 u8 k1;
1829 u8 k2;
1830 u8 k3;
1831 };
1832
1833 static const struct _pll_div codec_pll_div[] = {
1834 {7500000, 11289600, 1, 8, 12, 0x01, 0xc6, 0xee},
1835 {7500000, 12288000, 1, 8, 13, 0x04, 0x82, 0x90},
1836
1837 {7600000, 11289600, 1, 8, 11, 0x25, 0x2e, 0x93},
1838 {7600000, 12288000, 1, 8, 12, 0x27, 0x53, 0x49},
1839
1840 {8192000, 11289600, 1, 8, 11, 0x01, 0x0d, 0x41},
1841 {8192000, 12288000, 1, 8, 12, 0x00, 0x00, 0x01},
1842
1843 {8380000, 11289600, 1, 8, 10, 0x20, 0xb7, 0x8d},
1844 {8380000, 12288000, 1, 8, 11, 0x1e, 0xbe, 0xb7},
1845
1846 {9000000, 11289600, 1, 8, 10, 0x01, 0x7b, 0x1c},
1847 {9000000, 12288000, 1, 8, 10, 0x26, 0xd1, 0x4a},
1848
1849 {9600000, 11289600, 1, 8, 9, 0x11, 0x2a, 0x3c},
1850 {9600000, 12288000, 1, 8, 10, 0x0a, 0x18, 0xd8},
1851
1852 {9800000, 11289600, 1, 8, 9, 0x09, 0x16, 0x5c},
1853 {9800000, 12288000, 1, 8, 10, 0x01, 0x4e, 0x18},
1854
1855 {10000000, 11289600, 1, 8, 9, 0x01, 0x55, 0x33},
1856 {10000000, 12288000, 1, 8, 9, 0x22, 0xef, 0x8f},
1857
1858 {11059200, 11289600, 1, 8, 8, 0x07, 0x03, 0x07},
1859 {11059200, 12288000, 1, 8, 8, 0x25, 0x65, 0x7f},
1860
1861 {11289600, 11289600, 1, 8, 8, 0x00, 0x00, 0x01},
1862 {11289600, 12288000, 1, 8, 8, 0x1d, 0xc3, 0xb8},
1863
1864 {11500000, 11289600, 1, 8, 7, 0x23, 0xe9, 0xcd},
1865 {11500000, 12288000, 1, 8, 8, 0x17, 0x0f, 0xee},
1866
1867 {12000000, 11289600, 1, 8, 7, 0x16, 0x25, 0x6c},
1868 {12000000, 12288000, 1, 8, 8, 0x08, 0x13, 0xe0},
1869
1870 {12288000, 11289600, 1, 8, 7, 0x0e, 0xb9, 0x90},
1871 {12288000, 12288000, 1, 8, 8, 0x00, 0x00, 0x01},
1872
1873 {12500000, 11289600, 1, 8, 7, 0x09, 0x7a, 0xff},
1874 {12500000, 12288000, 1, 8, 7, 0x24, 0x5c, 0xe2},
1875
1876 {12800000, 11289600, 1, 8, 7, 0x02, 0x5b, 0x21},
1877 {12800000, 12288000, 1, 8, 7, 0x1c, 0x9b, 0xb9},
1878
1879 {13000000, 11289600, 1, 8, 6, 0x27, 0xdc, 0x2b},
1880 {13000000, 12288000, 1, 8, 7, 0x17, 0xa3, 0x2f},
1881
1882 {13500000, 11289600, 1, 8, 6, 0x1d, 0x08, 0xdc},
1883 {13500000, 12288000, 1, 8, 7, 0x0b, 0xda, 0xcc},
1884
1885 {13560000, 11289600, 1, 8, 6, 0x1b, 0xca, 0x0a},
1886 {13560000, 12288000, 1, 8, 7, 0x0a, 0x7f, 0xc7},
1887
1888 {14000000, 11289600, 1, 8, 6, 0x12, 0xfb, 0x81},
1889 {14000000, 12288000, 1, 8, 7, 0x00, 0xe9, 0xdd},
1890
1891 {15000000, 11289600, 1, 8, 6, 0x00, 0xe3, 0x77},
1892 {15000000, 12288000, 1, 8, 6, 0x17, 0x4a, 0x5f},
1893
1894 {15360000, 11289600, 1, 8, 5, 0x25, 0x05, 0xc2},
1895 {15360000, 12288000, 1, 8, 6, 0x10, 0xd4, 0x12},
1896
1897 {16000000, 11289600, 1, 8, 5, 0x1b, 0x20, 0x9d},
1898 {16000000, 12288000, 1, 8, 6, 0x06, 0x0e, 0xe8},
1899
1900 {16384000, 11289600, 1, 8, 5, 0x15, 0x8f, 0xb8},
1901 {16384000, 12288000, 1, 8, 6, 0x00, 0x00, 0x01},
1902
1903 {16800000, 11289600, 1, 8, 5, 0x0f, 0xd1, 0x96},
1904 {16800000, 12288000, 1, 8, 5, 0x23, 0xd2, 0x0a},
1905
1906 {18432000, 11289600, 2, 8, 9, 0x21, 0xa8, 0x25},
1907 {18432000, 12288000, 2, 8, 10, 0x1c, 0x0c, 0x1f},
1908
1909 {19200000, 11289600, 2, 8, 9, 0x11, 0x2a, 0x3c},
1910 {19200000, 12288000, 2, 8, 10, 0x0a, 0x18, 0xd8},
1911
1912 {19800000, 11289600, 2, 8, 9, 0x05, 0x2b, 0xc0},
1913 {19800000, 12288000, 2, 8, 9, 0x27, 0x1d, 0x01},
1914
1915 {20000000, 11289600, 2, 8, 9, 0x01, 0x55, 0x33},
1916 {20000000, 12288000, 2, 8, 9, 0x22, 0xef, 0x8f},
1917
1918 {22118400, 11289600, 2, 8, 8, 0x07, 0x03, 0x07},
1919 {22118400, 12288000, 2, 8, 8, 0x25, 0x65, 0x7f},
1920
1921 {22579200, 11289600, 2, 8, 8, 0x00, 0x00, 0x01},
1922 {22579200, 12288000, 2, 8, 8, 0x1d, 0xc3, 0xb8},
1923
1924 {24000000, 11289600, 2, 8, 7, 0x16, 0x25, 0x6c},
1925 {24000000, 12288000, 2, 8, 8, 0x08, 0x13, 0xe0},
1926
1927 {24576000, 11289600, 2, 8, 7, 0x0e, 0xb9, 0x90},
1928 {24576000, 12288000, 2, 8, 8, 0x00, 0x00, 0x01},
1929
1930 {25000000, 11289600, 2, 8, 7, 0x09, 0x7a, 0xff},
1931 {25000000, 12288000, 2, 8, 7, 0x24, 0x5c, 0xe2},
1932
1933 {26000000, 11289600, 2, 8, 6, 0x27, 0xdc, 0x2b},
1934 {26000000, 12288000, 2, 8, 7, 0x17, 0xa3, 0x2f},
1935
1936 {27000000, 11289600, 2, 8, 6, 0x1d, 0x08, 0xdc},
1937 {27000000, 12288000, 2, 8, 7, 0x0b, 0xda, 0xcc},
1938
1939 {30000000, 11289600, 2, 8, 6, 0x00, 0xe3, 0x77},
1940 {30000000, 12288000, 2, 8, 6, 0x17, 0x4a, 0x5f},
1941 };
1942
es8396_set_pll(struct snd_soc_dai * dai,int pll_id,int source,unsigned int freq_in,unsigned int freq_out)1943 static int es8396_set_pll(struct snd_soc_dai *dai, int pll_id,
1944 int source, unsigned int freq_in,
1945 unsigned int freq_out)
1946 {
1947 int i;
1948 struct snd_soc_component *component = dai->component;
1949 struct es8396_private *priv = snd_soc_component_get_drvdata(component);
1950 u16 reg;
1951 u8 N, K1, K2, K3, mclk_div, pll_div, tmp;
1952
1953 switch (pll_id) {
1954 case ES8396_PLL:
1955 break;
1956 default:
1957 return -EINVAL;
1958 }
1959 /* Disable PLL, power down and hold in reset state */
1960 snd_soc_component_write(component, ES8396_PLL_CTRL_1_REG02, 0x81);
1961
1962 if (!freq_in || !freq_out)
1963 return 0;
1964
1965 switch (source) {
1966 case ES8396_PLL_NO_SRC_0:
1967 /* Allow no source specification when stopping */
1968 if (freq_out)
1969 return -EINVAL;
1970 reg = snd_soc_component_read(component, ES8396_CLK_SRC_SEL_REG01);
1971 reg &= 0xF0;
1972 if (source == 0)
1973 reg |= 0x01; /* clksrc2= 0, clksrc1 = 1 */
1974 else
1975 reg |= 0x09; /* clksrc2= 1, clksrc1 = 1 */
1976
1977 snd_soc_component_write(component, ES8396_CLK_SRC_SEL_REG01, reg);
1978 reg = snd_soc_component_read(component, ES8396_CLK_CTRL_REG08);
1979 reg |= 0x0F;
1980 snd_soc_component_write(component, ES8396_CLK_CTRL_REG08, reg);
1981 pr_debug("ES8396 PLL No Clock source\n");
1982 break;
1983 case ES8396_PLL_SRC_FRM_MCLK:
1984 reg = snd_soc_component_read(component, ES8396_CLK_SRC_SEL_REG01);
1985 reg &= 0xF3;
1986 reg |= 0x04; /* clksrc2= mclk */
1987 /* use clk2 for pll clk source */
1988 snd_soc_component_write(component, ES8396_CLK_SRC_SEL_REG01, reg);
1989 reg = snd_soc_component_read(component, ES8396_CLK_CTRL_REG08);
1990 reg |= 0x0F;
1991 snd_soc_component_write(component, ES8396_CLK_CTRL_REG08, reg);
1992 pr_debug("ES8396 PLL Clock Source from MCLK pin\n");
1993 break;
1994 case ES8396_PLL_SRC_FRM_BCLK:
1995 reg = snd_soc_component_read(component, ES8396_CLK_SRC_SEL_REG01);
1996 reg &= 0xF3;
1997 reg |= 0x0c; /* clksrc2= bclk, */
1998 /* use clk2 for pll clk source */
1999 snd_soc_component_write(component, ES8396_CLK_SRC_SEL_REG01, reg);
2000 reg = snd_soc_component_read(component, ES8396_CLK_CTRL_REG08);
2001 reg |= 0x0F;
2002 snd_soc_component_write(component, ES8396_CLK_CTRL_REG08, reg);
2003 pr_debug("ES8396 PLL Clock Source from BCLK signal\n");
2004 break;
2005 default:
2006 return -EINVAL;
2007 }
2008 /* get N & K */
2009 tmp = 0;
2010 if (source == ES8396_PLL_SRC_FRM_MCLK ||
2011 source == ES8396_PLL_SRC_FRM_BCLK) {
2012 for (i = 0; i < ARRAY_SIZE(codec_pll_div); i++) {
2013 if (codec_pll_div[i].pll_in == freq_in &&
2014 codec_pll_div[i].pll_out == freq_out) {
2015 /* PLL source from MCLK */
2016 mclk_div = codec_pll_div[i].mclkdiv;
2017 pll_div = codec_pll_div[i].plldiv;
2018 N = codec_pll_div[i].n;
2019 K3 = codec_pll_div[i].k1;
2020 K2 = codec_pll_div[i].k2;
2021 K1 = codec_pll_div[i].k3;
2022 tmp = 1;
2023 break;
2024 }
2025 }
2026
2027 if (tmp == 1) {
2028 pr_debug("MCLK DIV=%d PLL DIV=%d PLL CLOCK SOURCE=%dHz\n",
2029 mclk_div, pll_div, freq_in);
2030 pr_debug("N=%d, K3=%d, K2=%d, K1=%d\n", N, K3, K2, K1);
2031
2032 /* set N & K */
2033 snd_soc_component_write(component, ES8396_PLL_N_REG04, N);
2034 snd_soc_component_write(component, ES8396_PLL_K2_REG05, K3);
2035 snd_soc_component_write(component, ES8396_PLL_K1_REG06, K2);
2036 snd_soc_component_write(component, ES8396_PLL_K0_REG07, K1);
2037 if (mclk_div == 1)
2038 /* mclk div2 = 0 */
2039 snd_soc_component_update_bits(component,
2040 ES8396_CLK_SRC_SEL_REG01,
2041 0x10, 0x00);
2042 else
2043 /* mclk div2 = 1 */
2044 snd_soc_component_update_bits(component,
2045 ES8396_CLK_SRC_SEL_REG01,
2046 0x10, 0x10);
2047
2048 /* pll div 8 */
2049 snd_soc_component_update_bits(component, ES8396_PLL_CTRL_1_REG02,
2050 0x3, 0x01);
2051
2052 /* configure the pll power voltage */
2053 switch (priv->dvdd_pwr_vol) {
2054 case 0x18:
2055 /* dvdd=1.8v */
2056 snd_soc_component_update_bits(component,
2057 ES8396_PLL_CTRL_2_REG03,
2058 0x0c, 0x00);
2059 break;
2060 case 0x25:
2061 /* dvdd=2.5v */
2062 snd_soc_component_update_bits(component,
2063 ES8396_PLL_CTRL_2_REG03,
2064 0x0c, 0x04);
2065 break;
2066 case 0x33:
2067 /* dvdd=3.3v */
2068 snd_soc_component_update_bits(component,
2069 ES8396_PLL_CTRL_2_REG03,
2070 0x0c, 0x08);
2071 break;
2072 default:
2073 /* dvdd=1.8v */
2074 snd_soc_component_update_bits(component,
2075 ES8396_PLL_CTRL_2_REG03,
2076 0x0c, 0x00);
2077 break;
2078 }
2079 /* enable PLL analog power up */
2080 snd_soc_component_update_bits(component, ES8396_PLL_CTRL_1_REG02,
2081 0x80, 0x00);
2082 /* pll digital on */
2083 snd_soc_component_update_bits(component, ES8396_PLL_CTRL_1_REG02,
2084 0x40, 0x40);
2085 priv->mclk[dai->id - 1] = freq_out;
2086 snd_soc_component_write(component, ES8396_PLL_N_REG04, 0x08);
2087 snd_soc_component_write(component, ES8396_PLL_K2_REG05, 0X1D);
2088 snd_soc_component_write(component, ES8396_PLL_K1_REG06, 0XC3);
2089 snd_soc_component_write(component, ES8396_PLL_K0_REG07, 0XB8);
2090 } else {
2091 pr_debug("Can not find the correct clock frequency!!!!!\n");
2092 }
2093 }
2094 return 0;
2095 }
2096
2097 /*
2098 * if PLL not be used, use internal clk1 for mclk,
2099 * otherwise, use internal clk2 for PLL source.
2100 */
es8396_set_dai_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)2101 static int es8396_set_dai_sysclk(struct snd_soc_dai *dai,
2102 int clk_id, unsigned int freq, int dir)
2103 {
2104 struct snd_soc_component *component = dai->component;
2105 struct es8396_private *priv = snd_soc_component_get_drvdata(component);
2106 u8 reg;
2107
2108 switch (dai->id) {
2109 case ES8396_SDP1:
2110 case ES8396_SDP2:
2111 case ES8396_SDP3:
2112 break;
2113 default:
2114 return -EINVAL;
2115 }
2116 switch (clk_id) {
2117 /* the clock source form MCLK pin, don't use PLL */
2118 case ES8396_CLKID_MCLK:
2119 reg = snd_soc_component_read(component, ES8396_CLK_SRC_SEL_REG01);
2120 reg &= 0xFC;
2121 reg |= 0x00; /* clksrc1= mclk */
2122 snd_soc_component_write(component, ES8396_CLK_SRC_SEL_REG01, reg);
2123
2124 /* always use clk1 */
2125 reg = snd_soc_component_read(component, ES8396_CLK_CTRL_REG08);
2126 reg &= 0xf0;
2127 snd_soc_component_write(component, ES8396_CLK_CTRL_REG08, reg);
2128
2129 priv->sysclk[dai->id] = clk_id;
2130 priv->mclk[dai->id] = freq;
2131 if (freq > 19600000) {
2132 /* mclk div2 */
2133 snd_soc_component_update_bits(component, ES8396_CLK_SRC_SEL_REG01,
2134 0x10, 0x10);
2135 }
2136 switch (dai->id) {
2137 case ES8396_SDP1:
2138 /* bclkdiv m1 use clk1 */
2139 snd_soc_component_update_bits(component, ES8396_BCLK_DIV_M1_REG0E,
2140 0x20, 0x00);
2141 /* lrckdiv m3 use clk1 */
2142 snd_soc_component_update_bits(component, ES8396_LRCK_DIV_M3_REG10,
2143 0x20, 0x00);
2144 break;
2145 case ES8396_SDP2:
2146 case ES8396_SDP3:
2147 /* bclkdiv m1 use clk1 */
2148 snd_soc_component_update_bits(component, ES8396_BCLK_DIV_M2_REG0F,
2149 0x20, 0x00);
2150 /* lrckdiv m4 use clk1 */
2151 snd_soc_component_update_bits(component, ES8396_LRCK_DIV_M4_REG11,
2152 0x20, 0x00);
2153 break;
2154 default:
2155 break;
2156 }
2157 pr_debug("ES8396 using MCLK as SYSCLK at %uHz\n", freq);
2158 break;
2159 /* the clock source form internal BCLK signal, don't use PLL */
2160 case ES8396_CLKID_BCLK:
2161 reg = snd_soc_component_read(component, ES8396_CLK_SRC_SEL_REG01);
2162 reg &= 0xFC;
2163 reg |= 0x03; /* clksrc1= bclk */
2164 snd_soc_component_write(component, ES8396_CLK_SRC_SEL_REG01, reg);
2165 /* always use clk1 */
2166 reg = snd_soc_component_read(component, ES8396_CLK_CTRL_REG08);
2167 reg &= 0xf0;
2168 snd_soc_component_write(component, ES8396_CLK_CTRL_REG08, reg);
2169
2170 priv->sysclk[dai->id] = clk_id;
2171 priv->mclk[dai->id] = freq;
2172 if (freq > 19600000) {
2173 /* mclk div2 */
2174 snd_soc_component_update_bits(component, ES8396_CLK_SRC_SEL_REG01,
2175 0x10, 0x10);
2176 }
2177 switch (dai->id) {
2178 case ES8396_SDP1:
2179 /* bclkdiv m1 use clk1 */
2180 snd_soc_component_update_bits(component, ES8396_BCLK_DIV_M1_REG0E,
2181 0x20, 0x00);
2182 /* lrckdiv m3 use clk1 */
2183 snd_soc_component_update_bits(component, ES8396_LRCK_DIV_M3_REG10,
2184 0x20, 0x00);
2185 break;
2186 case ES8396_SDP2:
2187 case ES8396_SDP3:
2188 /* bclkdiv m1 use clk1 */
2189 snd_soc_component_update_bits(component, ES8396_BCLK_DIV_M2_REG0F,
2190 0x20, 0x00);
2191 /* lrckdiv m4 use clk1 */
2192 snd_soc_component_update_bits(component, ES8396_LRCK_DIV_M4_REG11,
2193 0x20, 0x00);
2194 break;
2195 default:
2196 break;
2197 }
2198 pr_debug("ES8396 using BCLK as SYSCLK at %uHz\n", freq);
2199 break;
2200 case ES8396_CLKID_PLLO:
2201 priv->sysclk[dai->id] = ES8396_CLKID_PLLO;
2202 switch (dai->id) {
2203 case ES8396_SDP1:
2204 /* bclkdiv m1 use clk1 */
2205 snd_soc_component_update_bits(component, ES8396_BCLK_DIV_M1_REG0E,
2206 0x20, 0x00);
2207 /* lrckdiv m3 use clk1 */
2208 snd_soc_component_update_bits(component, ES8396_LRCK_DIV_M3_REG10,
2209 0x20, 0x00);
2210 break;
2211 case ES8396_SDP2:
2212 /* bclkdiv m1 use clk2 */
2213 snd_soc_component_update_bits(component, ES8396_BCLK_DIV_M1_REG0E,
2214 0x20, 0x20);
2215 /* lrckdiv m3 use clk2 */
2216 snd_soc_component_update_bits(component, ES8396_LRCK_DIV_M3_REG10,
2217 0x20, 0x20);
2218 break;
2219 case ES8396_SDP3:
2220 /* bclkdiv m1 use clk2 */
2221 snd_soc_component_update_bits(component, ES8396_BCLK_DIV_M2_REG0F,
2222 0x20, 0x20);
2223 /* lrckdiv m4 use clk2 */
2224 snd_soc_component_update_bits(component, ES8396_LRCK_DIV_M4_REG11,
2225 0x20, 0x20);
2226 break;
2227 default:
2228 break;
2229 }
2230 pr_debug("ES8396 using PLL Output as SYSCLK\n");
2231 break;
2232 default:
2233 pr_err("ES8396 System clock error\n");
2234 return -EINVAL;
2235 }
2236 return 0;
2237 }
2238
2239 struct es8396_mclk_div {
2240 u32 mclk;
2241 u32 srate;
2242 u8 lrcdiv;
2243 u8 bclkdiv;
2244 };
2245
2246 static struct es8396_mclk_div es8396_mclk_coeffs[] = {
2247 /* MCLK, Sample Rate, lrckdiv, bclkdiv */
2248 {5644800, 11025, 0x04, 0x08},
2249 {5644800, 22050, 0x02, 0x04},
2250 {5644800, 44100, 0x00, 0x02},
2251
2252 {6000000, 8000, 0x17, 0x0f},
2253 {6000000, 11025, 0x16, 0x08},
2254 {6000000, 12000, 0x15, 0x0a},
2255 {6000000, 16000, 0x14, 0x05},
2256 {6000000, 22050, 0x13, 0x04},
2257 {6000000, 24000, 0x12, 0x05},
2258 {6000000, 44100, 0x11, 0x02},
2259 {6000000, 48000, 0x10, 0x01},
2260
2261 {6144000, 8000, 0x06, 0x0c},
2262 {6144000, 12000, 0x04, 0x08},
2263 {6144000, 16000, 0x03, 0x06},
2264 {6144000, 24000, 0x02, 0x04},
2265 {6144000, 32000, 0x01, 0x03},
2266 {6144000, 48000, 0x00, 0x02},
2267
2268 {8192000, 8000, 0x07, 0x10},
2269 {8192000, 16000, 0x04, 0x08},
2270 {8192000, 32000, 0x02, 0x04},
2271
2272 {11289600, 11025, 0x07, 0x10},
2273 {11289600, 22050, 0x04, 0x08},
2274 {11289600, 44100, 0x02, 0x04},
2275
2276 {12000000, 8000, 0x1b, 0x17},
2277 {12000000, 11025, 0x19, 0x11},
2278 {12000000, 12000, 0x18, 0x13},
2279 {12000000, 16000, 0x17, 0x0f},
2280 {12000000, 22050, 0x16, 0x08},
2281 {12000000, 24000, 0x15, 0x0a},
2282 {12000000, 32000, 0x14, 0x05},
2283 {12000000, 44100, 0x13, 0x04},
2284 {12000000, 48000, 0x12, 0x05},
2285
2286 {12288000, 8000, 0x0a, 0x15},
2287 {12288000, 12000, 0x07, 0x10},
2288 {12288000, 16000, 0x06, 0x0c},
2289 {12288000, 24000, 0x04, 0x08},
2290 {12288000, 32000, 0x03, 0x06},
2291 {12288000, 48000, 0x02, 0x04},
2292 };
2293
es8396_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)2294 static int es8396_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
2295 {
2296 struct snd_soc_component *component = codec_dai->component;
2297 struct es8396_private *priv = snd_soc_component_get_drvdata(component);
2298 u8 id = codec_dai->id;
2299 unsigned int inv, format;
2300 u8 spc, mmcc;
2301
2302 switch (id) {
2303 case ES8396_SDP1:
2304 spc = snd_soc_component_read(component, ES8396_SDP1_IN_FMT_REG1F) & 0x3f;
2305 mmcc = snd_soc_component_read(component, ES8396_SDP_1_MS_REG12);
2306 break;
2307 case ES8396_SDP2:
2308 spc = snd_soc_component_read(component, ES8396_SDP2_IN_FMT_REG22) & 0x3f;
2309 mmcc = snd_soc_component_read(component, ES8396_SDP_2_MS_REG13);
2310 break;
2311 case ES8396_SDP3:
2312 spc = snd_soc_component_read(component, ES8396_SDP3_IN_FMT_REG24) & 0x3f;
2313 mmcc = snd_soc_component_read(component, ES8396_SDP_3_MS_REG14);
2314 break;
2315 default:
2316 return -EINVAL;
2317 }
2318
2319 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2320 case SND_SOC_DAIFMT_CBM_CFM:
2321 mmcc &= ~MS_MASTER;
2322 mmcc |= 0x24;
2323 if (id == ES8396_SDP1) {
2324 mmcc &= 0xe4; /* select bclkm1,lrckm3 */
2325 } else {
2326 mmcc &= 0xe4; /* select bclkm2,lrckm4 */
2327 mmcc |= 0x09;
2328 }
2329 break;
2330
2331 case SND_SOC_DAIFMT_CBS_CFS:
2332 mmcc &= ~MS_MASTER;
2333 break;
2334
2335 default:
2336 return -EINVAL;
2337 }
2338
2339 format = (fmt & SND_SOC_DAIFMT_FORMAT_MASK);
2340 inv = (fmt & SND_SOC_DAIFMT_INV_MASK);
2341
2342 switch (format) {
2343 case SND_SOC_DAIFMT_I2S:
2344 spc &= 0xC7;
2345 /* lrck polarity normal, TO CHECK THE L&R Inverted for i-net */
2346 spc |= 0x00;
2347 break;
2348 case SND_SOC_DAIFMT_LEFT_J:
2349 spc &= 0xC7;
2350 spc |= 0x18; /* lrck polarity normal */
2351 break;
2352 case SND_SOC_DAIFMT_RIGHT_J:
2353 if (id == ES8396_SDP1) {
2354 spc &= 0xC7;
2355 spc |= 0x28; /* lrck polarity normal */
2356 } else {
2357 pr_err("ES8396 SDP2&SDP3 don't Support Right Justified\n");
2358 return -EINVAL;
2359 }
2360 break;
2361 case SND_SOC_DAIFMT_DSP_A:
2362 case SND_SOC_DAIFMT_DSP_B:
2363 spc &= 0xC7;
2364
2365 if (format == SND_SOC_DAIFMT_DSP_A)
2366 spc |= 0x30;
2367 else
2368 spc |= 0x38;
2369 break;
2370 default:
2371 return -EINVAL;
2372 }
2373
2374 snd_soc_component_write(component, ES8396_SDP1_IN_FMT_REG1F, 00);
2375 pr_debug("es8396_set_dai_fmt-->\n");
2376
2377 priv->config[id].spc = spc;
2378 priv->config[id].mmcc = mmcc;
2379
2380 return 0;
2381 }
2382
es8396_pcm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)2383 static int es8396_pcm_hw_params(struct snd_pcm_substream *substream,
2384 struct snd_pcm_hw_params *params,
2385 struct snd_soc_dai *dai)
2386 {
2387 struct snd_soc_component *component = dai->component;
2388 struct es8396_private *priv = snd_soc_component_get_drvdata(component);
2389 int id = dai->id;
2390 int mclk_coeff = 0;
2391 int srate = params_rate(params);
2392 u8 bdiv, lrdiv;
2393
2394 pr_debug("DAI[%d]: MCLK= %u, srate= %u, lrckdiv= %x, bclkdiv= %x\n",
2395 id, priv->mclk[0], srate,
2396 es8396_mclk_coeffs[mclk_coeff].lrcdiv,
2397 es8396_mclk_coeffs[mclk_coeff].bclkdiv);
2398
2399 switch (id) {
2400 case ES8396_SDP1:
2401 bdiv = snd_soc_component_read(component, ES8396_BCLK_DIV_M2_REG0F);
2402 bdiv &= 0xe0;
2403 bdiv |= es8396_mclk_coeffs[mclk_coeff].bclkdiv;
2404 lrdiv = snd_soc_component_read(component, ES8396_LRCK_DIV_M4_REG11);
2405 lrdiv &= 0xe0;
2406 lrdiv |= 0x22; /* es8396_mclk_coeffs[mclk_coeff].lrcdiv; */
2407 snd_soc_component_write(component, ES8396_BCLK_DIV_M2_REG0F, bdiv);
2408 snd_soc_component_write(component, ES8396_LRCK_DIV_M4_REG11, lrdiv);
2409 priv->config[id].srate = srate;
2410 priv->config[id].lrcdiv = lrdiv;
2411 priv->config[id].sclkdiv = bdiv;
2412 break;
2413 case ES8396_SDP2:
2414 case ES8396_SDP3:
2415 bdiv = snd_soc_component_read(component, ES8396_BCLK_DIV_M1_REG0E);
2416 bdiv &= 0xe0;
2417 bdiv |= es8396_mclk_coeffs[mclk_coeff].bclkdiv;
2418 lrdiv = snd_soc_component_read(component, ES8396_LRCK_DIV_M3_REG10);
2419 lrdiv &= 0xe0;
2420 lrdiv |= es8396_mclk_coeffs[mclk_coeff].lrcdiv;
2421 snd_soc_component_write(component, ES8396_BCLK_DIV_M1_REG0E, bdiv);
2422 snd_soc_component_write(component, ES8396_LRCK_DIV_M3_REG10, lrdiv);
2423 priv->config[id].srate = srate;
2424 priv->config[id].lrcdiv = lrdiv;
2425 priv->config[id].sclkdiv = bdiv;
2426 break;
2427 default:
2428 return -EINVAL;
2429 }
2430
2431 return 0;
2432 }
2433
es8396_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)2434 static int es8396_set_bias_level(struct snd_soc_component *component,
2435 enum snd_soc_bias_level level)
2436 {
2437 u8 value;
2438 struct es8396_private *es8396 = snd_soc_component_get_drvdata(component);
2439
2440 switch (level) {
2441 case SND_SOC_BIAS_ON:
2442 /*
2443 * dac csm startup, dac digital still on
2444 * snd_soc_component_update_bits(component, ES8396_DAC_CSM_REG66, 0xFF, 0x00);
2445 * dac analog power on
2446 * snd_soc_component_update_bits(component, ES8396_DAC_REF_PWR_CTRL_REG6E,
2447 * 0xff, 0x00);
2448 */
2449 snd_soc_component_write(component, 0x4E, 0x80);
2450 snd_soc_component_write(component, 0x4F, 0x81);
2451 break;
2452
2453 case SND_SOC_BIAS_PREPARE:
2454 break;
2455
2456 case SND_SOC_BIAS_STANDBY:
2457 if (es8396->aif1_select == 0 && es8396->aif2_select == 0) {
2458 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
2459 snd_soc_component_write(component, ES8396_SYS_VMID_REF_REG71,
2460 0xFF);
2461 if (es8396_valid_analdo(es8396->ana_ldo_lvl)) {
2462 value = es8396->ana_ldo_lvl;
2463 value &= 0x07;
2464 snd_soc_component_write(component, 0x70, value);
2465 }
2466 }
2467 }
2468 /*
2469 * dac csm startup, dac digital still stop
2470 * snd_soc_component_update_bits(component, ES8396_DAC_CSM_REG66, 0xFF, 0x04);
2471 * adc csm startup, adc digital still stop
2472 * snd_soc_component_update_bits(component, ES8396_ADC_CSM_REG53, 0xFF, 0x00);
2473 */
2474 break;
2475
2476 case SND_SOC_BIAS_OFF:
2477 break;
2478 }
2479
2480 return 0;
2481 }
2482
es8396_set_tristate(struct snd_soc_dai * dai,int tristate)2483 static int es8396_set_tristate(struct snd_soc_dai *dai, int tristate)
2484 {
2485 struct snd_soc_component *component = dai->component;
2486 int id = dai->id;
2487
2488 pr_debug("es8396_set_tristate\n");
2489 pr_debug("ES8396 SDP NUM = %d\n", id);
2490 switch (id) {
2491 case ES8396_SDP1:
2492 return snd_soc_component_update_bits(component, ES8396_SDP1_DGAIN_TDM_REG21,
2493 0x0a, 0x0a);
2494 case ES8396_SDP2:
2495 case ES8396_SDP3:
2496 pr_err("SDP NUM = %d, Can not support tristate\n", id);
2497 return -EINVAL;
2498 default:
2499 return -EINVAL;
2500 }
2501 }
2502
es8396_pcm_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)2503 static int es8396_pcm_startup(struct snd_pcm_substream *substream,
2504 struct snd_soc_dai *dai)
2505 {
2506 bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
2507 struct snd_soc_component *component = dai->component;
2508 struct es8396_private *es8396 = snd_soc_component_get_drvdata(component);
2509 int ret;
2510 int regv;
2511 int i;
2512
2513 pr_debug(">>>>>>>>es8396_pcm_startup\n");
2514 ret = snd_soc_component_read(component, ES8396_ADC_CSM_REG53);
2515 pr_debug("ES8396_ADC_CSM_REG53===0x%x\n", ret);
2516 /*
2517 * set the clock source to MCLK pin
2518 * set divider for music playback
2519 * set DAC source from SDP1 in
2520 */
2521 if ((es8396->aif2_select & 0x01) == 0) {
2522 pr_debug(">>>>>>>>es8396_pcm_startup, only power on sdp1 for music\n");
2523 /* if don't have voice requirement */
2524 snd_soc_component_write(component, 0x1A, 0x00);
2525 snd_soc_component_write(component, 0x8, 0x10);
2526 snd_soc_component_write(component, 0xd, 0x00);
2527 snd_soc_component_write(component, 0x9, 0x04);
2528 snd_soc_component_write(component, 0x69, 0x00);
2529 snd_soc_component_write(component, 0x67, 0x00);
2530 } else {
2531 pr_debug(">>>>>>>>es8396_pcm_startup, already power on sdp2 for voice\n");
2532 snd_soc_component_write(component, 0x18, 0x00); /* set eq source */
2533 snd_soc_component_write(component, 0x19, 0x51); /* set eq source */
2534 /* if have voice requirement */
2535 snd_soc_component_write(component, 0x1A, 0x40);
2536 snd_soc_component_write(component, 0x8, 0x10);
2537 snd_soc_component_write(component, 0xd, 0x00);
2538 snd_soc_component_write(component, 0x9, 0x04);
2539 snd_soc_component_write(component, 0x67, 0x0c);
2540 snd_soc_component_write(component, 0x69, 0x04);
2541 }
2542
2543 if (playback) {
2544 pr_debug(">>>>>>>>>>>es8396_pcm_startup playback\n");
2545 es8396->aif1_select |= 0x01;
2546 snd_soc_component_write(component, 0x66, 0x01);
2547 for (i = 0; i < 120; i = i + 2) {
2548 snd_soc_component_write(component, 0x6A, i + 1);
2549 snd_soc_component_write(component, 0x6B, i + 1);
2550 usleep_range(100, 200);
2551 }
2552 if (es8396->calibrate == 0) {
2553 pr_debug("Enter into %s %d\n", __func__, __LINE__);
2554 es8396->calibrate = true;
2555 }
2556 schedule_delayed_work(&es8396->pcm_pop_work,
2557 msecs_to_jiffies(10));
2558
2559 } else {
2560 pr_debug(">>>>>>>>>>>es8396_pcm_startup capture\n");
2561 snd_soc_component_update_bits(component, ES8396_SDP1_OUT_FMT_REG20, 0x40,
2562 0x40);
2563 /* set adc alc */
2564 snd_soc_component_write(component, ES8396_ADC_ALC_CTRL_1_REG58, 0xC6);
2565 snd_soc_component_write(component, ES8396_ADC_ALC_CTRL_2_REG59, 0x12);
2566 snd_soc_component_write(component, ES8396_ADC_ALC_CTRL_4_REG5B, 0x04);
2567 snd_soc_component_write(component, ES8396_ADC_ALC_CTRL_5_REG5C, 0xC8);
2568 snd_soc_component_write(component, ES8396_ADC_ALC_CTRL_6_REG5D, 0x11);
2569 snd_soc_component_write(component, ES8396_ADC_ANALOG_CTRL_REG5E, 0x0);
2570 /* Enable MIC BOOST */
2571 snd_soc_component_write(component, ES8396_SYS_MIC_IBIAS_EN_REG75, 0x02);
2572
2573 /* axMixer Gain boost */
2574 regv = snd_soc_component_read(component, ES8396_AX_MIXER_BOOST_REG2F);
2575 regv |= 0x88;
2576 snd_soc_component_write(component, ES8396_AX_MIXER_BOOST_REG2F, regv);
2577 /* axmixer vol = +12db */
2578 snd_soc_component_write(component, ES8396_AX_MIXER_VOL_REG30, 0xaa);
2579 /* axmixer high driver capacility */
2580 snd_soc_component_write(component, ES8396_AX_MIXER_REF_LP_REG31, 0x02);
2581 snd_soc_component_write(component, 0x33, 0);
2582 /* MNMixer Gain boost */
2583 regv = snd_soc_component_read(component, ES8396_MN_MIXER_BOOST_REG37);
2584 regv |= 0x88;
2585 snd_soc_component_write(component, ES8396_MN_MIXER_BOOST_REG37, regv);
2586 /* mnmixer vol = +12db */
2587 snd_soc_component_write(component, ES8396_MN_MIXER_VOL_REG38, 0x44);
2588 /* mnmixer high driver capacility */
2589 snd_soc_component_write(component, ES8396_MN_MIXER_REF_LP_REG39, 0x02);
2590
2591 /* ADC STM and Digital Startup, ADC DS Mode */
2592 snd_soc_component_write(component, ES8396_ADC_CSM_REG53, 0x00);
2593 /* force adc stm to normal */
2594 snd_soc_component_write(component, ES8396_ADC_FORCE_REG77, 0x40);
2595 snd_soc_component_write(component, ES8396_ADC_FORCE_REG77, 0x0);
2596 /* ADC Volume =0db */
2597 snd_soc_component_write(component, ES8396_ADC_LADC_VOL_REG56, 0x0);
2598 snd_soc_component_write(component, ES8396_ADC_RADC_VOL_REG57, 0x0);
2599 snd_soc_component_write(component, ES8396_ADC_CLK_DIV_REG09, 0x04);
2600 es8396->aif1_select |= 0x02;
2601 schedule_delayed_work(&es8396->adc_depop_work,
2602 msecs_to_jiffies(150));
2603 }
2604 return 0;
2605 }
2606
es8396_pcm_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)2607 static void es8396_pcm_shutdown(struct snd_pcm_substream *substream,
2608 struct snd_soc_dai *dai)
2609 {
2610 bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
2611 struct snd_soc_component *component = dai->component;
2612 struct es8396_private *es8396 = snd_soc_component_get_drvdata(component);
2613
2614 pr_debug(">>>>>>>>es8396_pcm_shutdown\n");
2615
2616 /*
2617 * mute SDP1 in and mute SDP1 out
2618 */
2619 if (playback) {
2620 pr_debug(">>>>>>>>es8396_pcm_shutdown, playback\n");
2621 schedule_delayed_work(&es8396->pcm_shutdown_depop_work,
2622 msecs_to_jiffies(20));
2623 } else {
2624 pr_debug(">>>>>>>>es8396_pcm_shutdown, capture\n");
2625 snd_soc_component_update_bits(component, ES8396_SDP1_OUT_FMT_REG20, 0x40,
2626 0x40);
2627 es8396->aif1_select &= 0xfd;
2628 }
2629 }
2630
es8396_voice_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)2631 static int es8396_voice_startup(struct snd_pcm_substream *substream,
2632 struct snd_soc_dai *dai)
2633 {
2634 unsigned int index;
2635 bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
2636 struct snd_soc_component *component = dai->component;
2637 struct es8396_private *es8396 = snd_soc_component_get_drvdata(component);
2638 int regv;
2639 int i;
2640
2641 pr_debug("****************es8396_voice_startup\n");
2642
2643 if (playback) {
2644 pr_debug("****************es8396_voice_startup, playback\n");
2645 es8396->aif2_select |= 0x01;
2646 snd_soc_component_write(component, 0x4e, 0x84);
2647 snd_soc_component_write(component, 0x4f, 0x85);
2648
2649 for (i = 0; i < 120; i = i + 2) {
2650 snd_soc_component_write(component, 0x6A, i + 1);
2651 snd_soc_component_write(component, 0x6B, i + 1);
2652 usleep_range(100, 200);
2653 }
2654
2655 /* mute dac */
2656 snd_soc_component_write(component, 0x66, 0x01);
2657 /* DSP-B, 1st SCLK after LRCK edge, I2S2 SDPIN */
2658 snd_soc_component_update_bits(component, ES8396_SDP2_IN_FMT_REG22,
2659 0x7F, 0x13);
2660 snd_soc_component_write(component, 0x18, 0x51); /* set eq source */
2661 snd_soc_component_write(component, 0x19, 0x51); /* set eq source */
2662 snd_soc_component_write(component, 0x8, 0x10);
2663 snd_soc_component_write(component, 0xd, 0x00);
2664 snd_soc_component_write(component, 0x9, 0x04);
2665 if ((es8396->aif1_select & 0x01) == 0) {
2666 /* if only voice */
2667 snd_soc_component_write(component, 0x67, 0x0c);
2668 snd_soc_component_write(component, 0x69, 0x04);
2669 } else {
2670 snd_soc_component_write(component, 0x67, 0x0c);
2671 snd_soc_component_write(component, 0x69, 0x04);
2672 }
2673 /* clk2 used as EQ clk, OSR = 6xFs for 8k resampling to 48k */
2674 snd_soc_component_write(component, ES8396_EQ_CLK_OSR_SEL_REG1C, 0x35);
2675 snd_soc_component_write(component, ES8396_SHARED_ADDR_REG1D, 0x00);
2676
2677 for (index = 0; index < 59; index++) {
2678 snd_soc_component_write(component, ES8396_SHARED_DATA_REG1E,
2679 es8396_equalizer_lpf_bt_incall[index]);
2680 }
2681 snd_soc_component_write(component, ES8396_SHARED_ADDR_REG1D, 0xbb);
2682 snd_soc_component_write(component, ES8396_SHARED_DATA_REG1E,
2683 es8396_equalizer_lpf_bt_incall[59]);
2684
2685 schedule_delayed_work(&es8396->voice_pop_work,
2686 msecs_to_jiffies(50));
2687 } else {
2688 pr_debug("****************es8396_voice_startup, capture\n");
2689 es8396->aif2_select |= 0x02;
2690 /* set adc alc */
2691 snd_soc_component_write(component, ES8396_ADC_ALC_CTRL_1_REG58, 0xC6);
2692 snd_soc_component_write(component, ES8396_ADC_ALC_CTRL_2_REG59, 0x12);
2693 snd_soc_component_write(component, ES8396_ADC_ALC_CTRL_4_REG5B, 0x04);
2694 snd_soc_component_write(component, ES8396_ADC_ALC_CTRL_5_REG5C, 0xC8);
2695 snd_soc_component_write(component, ES8396_ADC_ALC_CTRL_6_REG5D, 0x11);
2696 snd_soc_component_write(component, ES8396_ADC_ANALOG_CTRL_REG5E, 0x0);
2697 snd_soc_component_write(component, ES8396_SYS_MIC_IBIAS_EN_REG75, 0x02);
2698
2699 /* axMixer Gain boost */
2700 regv = snd_soc_component_read(component, ES8396_AX_MIXER_BOOST_REG2F);
2701 regv |= 0x88;
2702 snd_soc_component_write(component, ES8396_AX_MIXER_BOOST_REG2F, regv);
2703 /* axmixer vol = +12db */
2704 snd_soc_component_write(component, ES8396_AX_MIXER_VOL_REG30, 0xaa);
2705 /* axmixer high driver capacility */
2706 snd_soc_component_write(component, ES8396_AX_MIXER_REF_LP_REG31, 0x02);
2707 snd_soc_component_write(component, 0x33, 0);
2708 /* MNMixer Gain boost */
2709 regv = snd_soc_component_read(component, ES8396_MN_MIXER_BOOST_REG37);
2710 regv |= 0x88;
2711 snd_soc_component_write(component, ES8396_MN_MIXER_BOOST_REG37, regv);
2712 /* mnmixer vol = +12db */
2713 snd_soc_component_write(component, ES8396_MN_MIXER_VOL_REG38, 0x44);
2714 /* mnmixer high driver capacility */
2715 snd_soc_component_write(component, ES8396_MN_MIXER_REF_LP_REG39, 0x02);
2716
2717 /* ADC STM and Digital Startup, ADC DS Mode */
2718 snd_soc_component_write(component, ES8396_ADC_CSM_REG53, 0x00);
2719 /* force adc stm to normal */
2720 snd_soc_component_write(component, ES8396_ADC_FORCE_REG77, 0x40);
2721 snd_soc_component_write(component, ES8396_ADC_FORCE_REG77, 0x0);
2722 /* ADC Volume =0db */
2723 snd_soc_component_write(component, ES8396_ADC_LADC_VOL_REG56, 0x0);
2724 snd_soc_component_write(component, ES8396_ADC_RADC_VOL_REG57, 0x0);
2725
2726 /* clk2 used as EQ clk, OSR = 6xFs for 8k resampling to 48k */
2727 snd_soc_component_update_bits(component, ES8396_SDP2_OUT_FMT_REG23,
2728 0x7F, 0x33);
2729 }
2730 return 0;
2731 }
2732
es8396_voice_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)2733 static void es8396_voice_shutdown(struct snd_pcm_substream *substream,
2734 struct snd_soc_dai *dai)
2735 {
2736 struct snd_soc_component *component = dai->component;
2737 struct es8396_private *es8396 = snd_soc_component_get_drvdata(component);
2738 bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
2739
2740 pr_debug("****************es8396_voice_shutdown\n");
2741
2742 /* DSP-B, 1st SCLK after LRCK edge, I2S2 SDPIN */
2743 if (playback) {
2744 snd_soc_component_write(component, 0x66, 0x01);
2745 pr_debug("****************es8396_voice_shutdown, playback\n");
2746 schedule_delayed_work(&es8396->voice_shutdown_depop_work,
2747 msecs_to_jiffies(10));
2748 } else {
2749 pr_debug("****************es8396_voice_shutdown, captuer\n");
2750 /* //DSP-B, 1st SCLK after LRCK edge, I2S2 SDPO */
2751 snd_soc_component_update_bits(component, ES8396_SDP2_OUT_FMT_REG23,
2752 0x7F, 0x73);
2753 es8396->aif2_select &= 0xfd;
2754 }
2755 }
2756
2757 /*
2758 * Only mute SDP IN(for dac)
2759 */
es8396_aif1_mute(struct snd_soc_dai * codec_dai,int mute,int stream)2760 static int es8396_aif1_mute(struct snd_soc_dai *codec_dai, int mute, int stream)
2761 {
2762 struct snd_soc_component *component = codec_dai->component;
2763 struct es8396_private *es8396 = snd_soc_component_get_drvdata(component);
2764
2765 pr_debug("es8396_aif1_mute id = %d, mute = %d", codec_dai->id, mute);
2766 if (mute) {
2767 if (es8396->spk_ctl_gpio && es8396->aif2_select == 0)
2768 gpiod_set_value(es8396->spk_ctl_gpio, 0);
2769 if (es8396->lineout_ctl_gpio && es8396->aif2_select == 0)
2770 gpiod_set_value(es8396->lineout_ctl_gpio, 0);
2771 msleep(100);
2772 } else {
2773 if (es8396->spk_ctl_gpio)
2774 gpiod_set_value(es8396->spk_ctl_gpio, 1);
2775 if (es8396->lineout_ctl_gpio)
2776 gpiod_set_value(es8396->lineout_ctl_gpio, 1);
2777 }
2778
2779 return 0;
2780 }
2781
es8396_aif2_mute(struct snd_soc_dai * codec_dai,int mute,int stream)2782 static int es8396_aif2_mute(struct snd_soc_dai *codec_dai, int mute, int stream)
2783 {
2784 struct snd_soc_component *component = codec_dai->component;
2785 struct es8396_private *es8396 = snd_soc_component_get_drvdata(component);
2786
2787 pr_debug("es8396_aif2_mute id = %d, mute = %d", codec_dai->id, mute);
2788
2789 if (mute) {
2790 if (es8396->spk_ctl_gpio && es8396->aif1_select == 0)
2791 gpiod_set_value(es8396->spk_ctl_gpio, 0);
2792 if (es8396->lineout_ctl_gpio && es8396->aif1_select == 0)
2793 gpiod_set_value(es8396->lineout_ctl_gpio, 0);
2794 msleep(100);
2795 } else {
2796 if (es8396->spk_ctl_gpio)
2797 gpiod_set_value(es8396->spk_ctl_gpio, 1);
2798 if (es8396->lineout_ctl_gpio)
2799 gpiod_set_value(es8396->lineout_ctl_gpio, 1);
2800 }
2801 return 0;
2802 }
2803
2804 /* SNDRV_PCM_RATE_KNOT -> 12000, 24000 Hz, limit with constraint list */
2805 #define ES8396_RATES (SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_KNOT)
2806 #define ES8396_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2807 SNDRV_PCM_FMTBIT_S24_LE)
2808
2809 static const struct snd_soc_dai_ops es8396_aif1_dai_ops = {
2810 .startup = es8396_pcm_startup,
2811 .shutdown = es8396_pcm_shutdown,
2812 .set_sysclk = es8396_set_dai_sysclk,
2813 .set_fmt = es8396_set_dai_fmt,
2814 .hw_params = es8396_pcm_hw_params,
2815 .mute_stream = es8396_aif1_mute,
2816 .set_pll = es8396_set_pll,
2817 .set_tristate = es8396_set_tristate,
2818 .no_capture_mute = 1,
2819 };
2820
2821 static const struct snd_soc_dai_ops es8396_aif2_dai_ops = {
2822 .startup = es8396_voice_startup,
2823 .shutdown = es8396_voice_shutdown,
2824 .set_sysclk = es8396_set_dai_sysclk,
2825 .set_fmt = es8396_set_dai_fmt,
2826 .hw_params = es8396_pcm_hw_params,
2827 .mute_stream = es8396_aif2_mute,
2828 .set_pll = es8396_set_pll,
2829 .no_capture_mute = 1,
2830 };
2831
2832 static struct snd_soc_dai_driver es8396_dai[] = {
2833 {
2834 .name = "es8396-aif1",
2835 .playback = {
2836 .stream_name = "SDP1 Playback",
2837 .channels_min = 1,
2838 .channels_max = 2,
2839 .rates = ES8396_RATES,
2840 .formats = ES8396_FORMATS,
2841 },
2842 .capture = {
2843 .stream_name = "SDP1 Capture",
2844 .channels_min = 1,
2845 .channels_max = 2,
2846 .rates = ES8396_RATES,
2847 .formats = ES8396_FORMATS,
2848 },
2849 .ops = &es8396_aif1_dai_ops,
2850 },
2851 };
2852
es8396_suspend(struct device * dev)2853 static int es8396_suspend(struct device *dev)
2854 {
2855 struct es8396_private *es8396 = dev_get_drvdata(dev);
2856 struct snd_soc_component *component = es8396->component;
2857
2858 snd_soc_component_write(component, 0x4e, 0x84);
2859 snd_soc_component_write(component, 0x4f, 0x85);
2860 snd_soc_component_write(component, 0x66, 0x01);
2861 snd_soc_component_write(component, 0x6e, 0x00);
2862
2863 return 0;
2864 }
2865
es8396_resume(struct device * dev)2866 static int es8396_resume(struct device *dev)
2867 {
2868 struct es8396_private *es8396 = dev_get_drvdata(dev);
2869 struct snd_soc_component *component = es8396->component;
2870
2871 usleep_range(20000, 21000);
2872
2873 snd_soc_component_write(component, 0x6e, 0x00);
2874 snd_soc_component_write(component, 0x66, 0x00);
2875 snd_soc_component_write(component, 0x4e, 0x80);
2876 snd_soc_component_write(component, 0x4f, 0x81);
2877 return 0;
2878 }
2879
es8396_probe(struct snd_soc_component * component)2880 static int es8396_probe(struct snd_soc_component *component)
2881 {
2882 struct es8396_private *es8396 = snd_soc_component_get_drvdata(component);
2883 int ret = 0, regv;
2884 u8 value;
2885
2886 es8396->component = component;
2887 es8396->mclk_clock = devm_clk_get(component->dev, "mclk");
2888 if (PTR_ERR(es8396->mclk_clock) == -EPROBE_DEFER)
2889 return -EPROBE_DEFER;
2890
2891 ret = clk_prepare_enable(es8396->mclk_clock);
2892 if (ret)
2893 return ret;
2894 regv = snd_soc_component_read(component, ES8396_PLL_K2_REG05);
2895
2896 if (regv == 0x00) {
2897 /*
2898 * setup system analog control
2899 */
2900 snd_soc_component_write(component, ES8396_DLL_CTRL_REG0D, 0x20);
2901 snd_soc_component_write(component, ES8396_CLK_SRC_SEL_REG01, 0x04);
2902 snd_soc_component_write(component, ES8396_PLL_CTRL_1_REG02, 0xc1);
2903 snd_soc_component_write(component, ES8396_PLL_CTRL_2_REG03, 0x00);
2904 snd_soc_component_write(component, ES8396_PLL_N_REG04, 0x08);
2905 snd_soc_component_write(component, ES8396_PLL_K2_REG05, 0X1d);
2906 snd_soc_component_write(component, ES8396_PLL_K1_REG06, 0Xc3);
2907 snd_soc_component_write(component, ES8396_PLL_K0_REG07, 0Xb8);
2908 snd_soc_component_write(component, ES8396_PLL_CTRL_1_REG02, 0x41);
2909
2910 /* adc,dac,cphp,class d clk enable,from clk2 */
2911 snd_soc_component_write(component, ES8396_CLK_CTRL_REG08, 0x00);
2912 /* adc clk ratio=1 */
2913 snd_soc_component_write(component, ES8396_ADC_CLK_DIV_REG09, 0x04);
2914 /* dac clk ratio=1 */
2915 snd_soc_component_write(component, ES8396_DAC_CLK_DIV_REG0A, 0x01);
2916 snd_soc_component_write(component, ES8396_BCLK_DIV_M2_REG0F, 0x24);
2917 snd_soc_component_write(component, ES8396_LRCK_DIV_M4_REG11, 0x22);
2918
2919 msleep(50);
2920 snd_soc_component_write(component, ES8396_SYS_VMID_REF_REG71, 0xFC);
2921 snd_soc_component_write(component, 0x72, 0xFF);
2922 snd_soc_component_write(component, 0x73, 0xFF);
2923 if (es8396_valid_analdo(es8396->ana_ldo_lvl) == false) {
2924 pr_err("Analog LDO Level error.\n");
2925 return -EINVAL;
2926 }
2927 value = es8396->ana_ldo_lvl;
2928 value &= 0x07;
2929 snd_soc_component_write(component, ES8396_SYS_CHIP_ANA_CTL_REG70, value);
2930 /* mic enable, mic d2se enable */
2931 snd_soc_component_write(component, ES8396_SYS_MIC_IBIAS_EN_REG75, 0x01);
2932 msleep(50);
2933 snd_soc_component_write(component, ES8396_TEST_MODE_REG76, 0xA0);
2934 snd_soc_component_write(component, ES8396_NGTH_REG7A, 0x20);
2935 msleep(50);
2936
2937 /* power up adc and dac analog */
2938 snd_soc_component_write(component, ES8396_ADC_ANALOG_CTRL_REG5E, 0x00);
2939 snd_soc_component_write(component, ES8396_DAC_REF_PWR_CTRL_REG6E, 0x00);
2940 /* set L,R DAC volume */
2941 snd_soc_component_write(component, ES8396_DAC_LDAC_VOL_REG6A, 0x01);
2942 snd_soc_component_write(component, ES8396_DAC_RDAC_VOL_REG6B, 0x01);
2943 /* setup charge current for calibrate */
2944 snd_soc_component_write(component, ES8396_ADC_LADC_VOL_REG56, 0x84);
2945 snd_soc_component_write(component, ES8396_ADC_RADC_VOL_REG57, 0xdc);
2946 snd_soc_component_write(component, ES8396_DAC_OFFSET_CALI_REG6F, 0x06);
2947 snd_soc_component_write(component, ES8396_DAC_RAMP_RATE_REG67, 0x00);
2948 /* enable adc and dac stm for calibrate */
2949 snd_soc_component_write(component, ES8396_DAC_CSM_REG66, 0x00);
2950 snd_soc_component_write(component, ES8396_ADC_CSM_REG53, 0x00);
2951 snd_soc_component_write(component, ES8396_ADC_FORCE_REG77, 0x40);
2952 snd_soc_component_write(component, ES8396_ADC_FORCE_REG77, 0x00);
2953 snd_soc_component_write(component, ES8396_DLL_CTRL_REG0D, 0x00);
2954 msleep(100);
2955 snd_soc_component_write(component, ES8396_DAC_CSM_REG66, 0x00);
2956 snd_soc_component_write(component, ES8396_ADC_ANALOG_CTRL_REG5E, 0x00);
2957 snd_soc_component_write(component, 0x5f, 0xf2);
2958 snd_soc_component_write(component, 0x1f, 0x00);
2959 snd_soc_component_write(component, 0x20, 0x40);
2960 /* FM */
2961 msleep(100);
2962 snd_soc_component_write(component, 0x65, 0x88);
2963 snd_soc_component_write(component, 0x2E, 0x88);
2964 snd_soc_component_write(component, 0x2F, 0x00);
2965 snd_soc_component_write(component, 0x30, 0xBB);
2966
2967 if (es8396_valid_micbias(es8396->mic_bias_lvl) == false) {
2968 pr_err("MIC BIAS Level error.\n");
2969 return -EINVAL;
2970 }
2971 value = es8396->mic_bias_lvl;
2972 value &= 0x07;
2973 value = (value << 4) | 0x08;
2974 /* enable micbias1 */
2975 snd_soc_component_write(component, ES8396_SYS_MICBIAS_CTRL_REG74, value);
2976
2977 snd_soc_component_write(component, ES8396_ADC_CSM_REG53, 0x20);
2978 snd_soc_component_write(component, ES8396_ADC_PGA_GAIN_REG61, 0x33);
2979 snd_soc_component_write(component, ES8396_ADC_MICBOOST_REG60, 0x22);
2980 if (es8396->dmic_amic == MIC_AMIC)
2981 /*use analog mic */
2982 snd_soc_component_write(component, ES8396_ADC_DMIC_RAMPRATE_REG54,
2983 0x00);
2984 else
2985 /*use digital mic */
2986 snd_soc_component_write(component, ES8396_ADC_DMIC_RAMPRATE_REG54,
2987 0xf0);
2988
2989 /*Enable HPF, LDATA= LADC, RDATA = LADC */
2990 snd_soc_component_write(component, ES8396_ADC_HPF_COMP_DASEL_REG55, 0x31);
2991
2992 /*
2993 * setup hp detection
2994 */
2995
2996 /* gpio 2 for irq, AINL as irq src, gpio1 for dmic clk */
2997 snd_soc_component_write(component, ES8396_ALRCK_GPIO_SEL_REG15, 0xfa);
2998 snd_soc_component_write(component, ES8396_DAC_JACK_DET_COMP_REG69, 0x00);
2999 if (es8396->jackdet_enable == 1) {
3000 /* jack detection from AINL pin, AINL=0, HP Insert */
3001 snd_soc_component_write(component, ES8396_DAC_JACK_DET_COMP_REG69,
3002 0x04);
3003 if (es8396->gpio_int_pol == 0)
3004 /* if HP insert, GPIO2=Low */
3005 snd_soc_component_write(component, ES8396_GPIO_IRQ_REG16,
3006 0x80);
3007 else
3008 /* if HP insert, GPIO2=High */
3009 snd_soc_component_write(component, ES8396_GPIO_IRQ_REG16,
3010 0xc0);
3011 } else {
3012 snd_soc_component_write(component, ES8396_GPIO_IRQ_REG16, 0x00);
3013 }
3014
3015 /*
3016 * setup mono in in differential mode or stereo mode
3017 */
3018
3019 /* monoin in differential mode */
3020 if (es8396->monoin_differential == 1)
3021 snd_soc_component_update_bits(component, ES8396_MN_MIXER_REF_LP_REG39,
3022 0x08, 0x08);
3023 else
3024 snd_soc_component_update_bits(component, ES8396_MN_MIXER_REF_LP_REG39,
3025 0x08, 0x00);
3026
3027 snd_soc_component_write(component, ES8396_DAC_JACK_DET_COMP_REG69, 0x00);
3028 snd_soc_component_write(component, ES8396_BCLK_DIV_M1_REG0E, 0x24);
3029 snd_soc_component_write(component, ES8396_LRCK_DIV_M3_REG10, 0x22);
3030 snd_soc_component_write(component, ES8396_SDP_2_MS_REG13, 0x00);
3031 //codec->dapm.bias_level = SND_SOC_BIAS_STANDBY;
3032 }
3033
3034 INIT_DELAYED_WORK(&es8396->adc_depop_work, adc_depop_work_events);
3035 mutex_init(&es8396->adc_depop_mlock);
3036 INIT_DELAYED_WORK(&es8396->pcm_pop_work, pcm_pop_work_events);
3037 mutex_init(&es8396->pcm_depop_mlock);
3038
3039 INIT_DELAYED_WORK(&es8396->voice_pop_work, voice_pop_work_events);
3040 mutex_init(&es8396->voice_depop_mlock);
3041
3042 INIT_DELAYED_WORK(&es8396->init_cali_work, init_cali_work_events);
3043 mutex_init(&es8396->init_cali_mlock);
3044
3045 INIT_DELAYED_WORK(&es8396->pcm_shutdown_depop_work,
3046 pcm_shutdown_depop_events);
3047 mutex_init(&es8396->pcm_shutdown_depop_mlock);
3048
3049 INIT_DELAYED_WORK(&es8396->voice_shutdown_depop_work,
3050 voice_shutdown_depop_events);
3051 mutex_init(&es8396->voice_shutdown_depop_mlock);
3052
3053 snd_soc_component_write(component, 0x6f, 0x83);
3054 snd_soc_component_write(component, ES8396_SYS_VMID_REF_REG71, 0xFC);
3055 msleep(100);
3056 snd_soc_component_write(component, 0x4E, 0x84);
3057 snd_soc_component_write(component, 0x4F, 0x85);
3058 snd_soc_component_write(component, 0x4A, 0x60);
3059 snd_soc_component_write(component, 0x4B, 0x60);
3060 /*
3061 * TODO: pop noise occur when HS calibration during probe
3062 * increase the delay of a period of time if necessary
3063 * msleep(50);
3064 */
3065 return ret;
3066 }
3067
es8396_remove(struct snd_soc_component * component)3068 static void es8396_remove(struct snd_soc_component *component)
3069 {
3070 snd_soc_component_write(component, 0X4E, 0x84);
3071 snd_soc_component_write(component, 0X4F, 0x85);
3072 snd_soc_component_write(component, 0X4A, 0x80);
3073 snd_soc_component_write(component, 0X4B, 0x80);
3074 snd_soc_component_write(component, 0x70, 0xd4);
3075 }
3076
3077 const struct regmap_config es8396_regmap_config = {
3078 .reg_bits = 8,
3079 .val_bits = 8,
3080 .max_register = ES8396_MAX_REGISTER,
3081 .cache_type = REGCACHE_RBTREE,
3082 .reg_defaults = es8396_reg_defaults,
3083 .num_reg_defaults = ARRAY_SIZE(es8396_reg_defaults),
3084 };
3085
3086 static const struct snd_soc_component_driver soc_codec_dev_es8396 = {
3087 .probe = es8396_probe,
3088 .remove = es8396_remove,
3089 .set_bias_level = es8396_set_bias_level,
3090
3091 .dapm_widgets = es8396_dapm_widgets,
3092 .num_dapm_widgets = ARRAY_SIZE(es8396_dapm_widgets),
3093 .dapm_routes = es8396_dapm_routes,
3094 .num_dapm_routes = ARRAY_SIZE(es8396_dapm_routes),
3095
3096 .controls = es8396_snd_controls,
3097 .num_controls = ARRAY_SIZE(es8396_snd_controls),
3098 };
3099
init_es8396_prv(struct es8396_private * es8396)3100 static int init_es8396_prv(struct es8396_private *es8396)
3101 {
3102 if (!es8396)
3103 return -EINVAL;
3104
3105 es8396->dvdd_pwr_vol = 0x18;
3106 es8396->spkmono = false;
3107 es8396->earpiece = true;
3108 es8396->monoin_differential = true;
3109 es8396->lno_differential = 0;
3110 es8396->ana_ldo_lvl = ANA_LDO_2_1V;
3111 es8396->spk_ldo_lvl = SPK_LDO_3V;
3112 es8396->mic_bias_lvl = MICBIAS_3V;
3113 es8396->jackdet_enable = true;
3114 es8396->gpio_int_pol = 0;
3115 es8396->dmic_amic = MIC_AMIC;
3116 es8396->calibrate = false;
3117 es8396->pcm_pop_work_retry = 1;
3118 es8396->output_device_selected = 0;
3119 es8396->aif1_select = 0;
3120 es8396->aif2_select = 0;
3121 return 0;
3122 }
3123
es8396_i2c_probe(struct i2c_client * i2c_client,const struct i2c_device_id * id)3124 static int es8396_i2c_probe(struct i2c_client *i2c_client,
3125 const struct i2c_device_id *id)
3126 {
3127 struct es8396_private *es8396;
3128 int ret;
3129
3130 es8396 = devm_kzalloc(&i2c_client->dev, sizeof(struct es8396_private),
3131 GFP_KERNEL);
3132 if (!es8396)
3133 return -ENOMEM;
3134
3135 ret = init_es8396_prv(es8396);
3136 if (ret < 0)
3137 return -EINVAL;
3138
3139 es8396->regmap = devm_regmap_init_i2c(i2c_client, &es8396_regmap_config);
3140 if (IS_ERR(es8396->regmap))
3141 return PTR_ERR(es8396->regmap);
3142
3143 /* initialize codec */
3144 i2c_set_clientdata(i2c_client, es8396);
3145
3146 /* external speaker amp controller */
3147 es8396->spk_ctl_gpio = devm_gpiod_get_optional(&i2c_client->dev,
3148 "spk-con-gpio",
3149 GPIOD_OUT_LOW);
3150 if (IS_ERR(es8396->spk_ctl_gpio))
3151 return PTR_ERR(es8396->spk_ctl_gpio);
3152
3153 /* lineout output controller*/
3154 es8396->lineout_ctl_gpio = devm_gpiod_get_optional(&i2c_client->dev,
3155 "lineout-con-gpio",
3156 GPIOD_OUT_LOW);
3157 if (IS_ERR(es8396->lineout_ctl_gpio))
3158 return PTR_ERR(es8396->lineout_ctl_gpio);
3159
3160 return devm_snd_soc_register_component(&i2c_client->dev,
3161 &soc_codec_dev_es8396, es8396_dai,
3162 ARRAY_SIZE(es8396_dai));
3163 }
3164
es8396_i2c_shutdown(struct i2c_client * client)3165 static void es8396_i2c_shutdown(struct i2c_client *client)
3166 {
3167 struct es8396_private *es8396 = i2c_get_clientdata(client);
3168 struct snd_soc_component *component = es8396->component;
3169
3170 if (es8396->spk_ctl_gpio)
3171 gpiod_set_value(es8396->spk_ctl_gpio, 0);
3172
3173 usleep_range(20000, 21000);
3174 snd_soc_component_write(component, 0X4E, 0x84);
3175 snd_soc_component_write(component, 0X4F, 0x85);
3176 snd_soc_component_write(component, 0X4a, 0x80);
3177 snd_soc_component_write(component, 0X4b, 0x80);
3178 snd_soc_component_write(component, 0x70, 0xd4);
3179 msleep(300);
3180 }
3181
3182 static const struct i2c_device_id es8396_id[] = {
3183 {"es8396", 0},
3184 {}
3185 };
3186
3187 MODULE_DEVICE_TABLE(i2c, es8396_id);
3188 static const struct dev_pm_ops es8396_pm_ops = {
3189 .suspend = es8396_suspend,
3190 .resume = es8396_resume,
3191 };
3192
3193 static struct i2c_driver es8396_i2c_driver = {
3194 .driver = {
3195 .name = "es8396",
3196 .pm = &es8396_pm_ops,
3197 },
3198 .id_table = es8396_id,
3199 .probe = es8396_i2c_probe,
3200 .shutdown = es8396_i2c_shutdown,
3201 };
3202
3203 module_i2c_driver(es8396_i2c_driver);
3204
3205 MODULE_DESCRIPTION("ASoC ES8396 driver");
3206 MODULE_AUTHOR("DavidYang, Everest Semiconductor Co., Ltd, <yangxiaohua@everest-semi.com>");
3207 MODULE_LICENSE("GPL");
3208