1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * es8328.c -- ES8328 ALSA SoC Audio driver
4 *
5 * Copyright 2014 Sutajio Ko-Usagi PTE LTD
6 *
7 * Author: Sean Cross <xobs@kosagi.com>
8 */
9
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/of_device.h>
13 #include <linux/module.h>
14 #include <linux/pm.h>
15 #include <linux/regmap.h>
16 #include <linux/slab.h>
17 #include <linux/regulator/consumer.h>
18 #include <sound/core.h>
19 #include <sound/initval.h>
20 #include <sound/pcm.h>
21 #include <sound/pcm_params.h>
22 #include <sound/soc.h>
23 #include <sound/tlv.h>
24 #include "es8328.h"
25
26 static const unsigned int rates_12288[] = {
27 8000, 12000, 16000, 24000, 32000, 48000, 96000,
28 };
29
30 static const int ratios_12288[] = {
31 10, 7, 6, 4, 3, 2, 0,
32 };
33
34 static const struct snd_pcm_hw_constraint_list constraints_12288 = {
35 .count = ARRAY_SIZE(rates_12288),
36 .list = rates_12288,
37 };
38
39 static unsigned int ratios_12000[] = {
40 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000,
41 48000, 88235, 96000,
42 };
43
44 static struct snd_pcm_hw_constraint_list constraints_12000 = {
45 .count = ARRAY_SIZE(ratios_12000),
46 .list = ratios_12000,
47 };
48
49 static const unsigned int rates_11289[] = {
50 8018, 11025, 22050, 44100, 88200,
51 };
52
53 static const int ratios_11289[] = {
54 9, 7, 4, 2, 0,
55 };
56
57 static const struct snd_pcm_hw_constraint_list constraints_11289 = {
58 .count = ARRAY_SIZE(rates_11289),
59 .list = rates_11289,
60 };
61
62 /* regulator supplies for sgtl5000, VDDD is an optional external supply */
63 enum sgtl5000_regulator_supplies {
64 DVDD,
65 AVDD,
66 PVDD,
67 HPVDD,
68 ES8328_SUPPLY_NUM
69 };
70
71 /* vddd is optional supply */
72 static const char * const supply_names[ES8328_SUPPLY_NUM] = {
73 "DVDD",
74 "AVDD",
75 "PVDD",
76 "HPVDD",
77 };
78
79 #define ES8328_RATES (SNDRV_PCM_RATE_192000 | \
80 SNDRV_PCM_RATE_96000 | \
81 SNDRV_PCM_RATE_88200 | \
82 SNDRV_PCM_RATE_8000_48000)
83 #define ES8328_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
84 SNDRV_PCM_FMTBIT_S18_3LE | \
85 SNDRV_PCM_FMTBIT_S20_3LE | \
86 SNDRV_PCM_FMTBIT_S24_LE | \
87 SNDRV_PCM_FMTBIT_S32_LE)
88
89 struct es8328_priv {
90 struct regmap *regmap;
91 struct clk *clk;
92 int playback_fs;
93 bool deemph;
94 int mclkdiv2;
95 const struct snd_pcm_hw_constraint_list *sysclk_constraints;
96 const int *mclk_ratios;
97 bool master;
98 struct regulator_bulk_data supplies[ES8328_SUPPLY_NUM];
99 };
100
101 /*
102 * ES8328 Controls
103 */
104
105 static const char * const adcpol_txt[] = {"Normal", "L Invert", "R Invert",
106 "L + R Invert"};
107 static SOC_ENUM_SINGLE_DECL(adcpol,
108 ES8328_ADCCONTROL6, 6, adcpol_txt);
109
110 static const DECLARE_TLV_DB_SCALE(play_tlv, -3000, 100, 0);
111 static const DECLARE_TLV_DB_SCALE(dac_adc_tlv, -9600, 50, 0);
112 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
113 static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 300, 0);
114
115 static const struct {
116 int rate;
117 unsigned int val;
118 } deemph_settings[] = {
119 { 0, ES8328_DACCONTROL6_DEEMPH_OFF },
120 { 32000, ES8328_DACCONTROL6_DEEMPH_32k },
121 { 44100, ES8328_DACCONTROL6_DEEMPH_44_1k },
122 { 48000, ES8328_DACCONTROL6_DEEMPH_48k },
123 };
124
es8328_set_deemph(struct snd_soc_component * component)125 static int es8328_set_deemph(struct snd_soc_component *component)
126 {
127 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
128 int val, i, best;
129
130 /*
131 * If we're using deemphasis select the nearest available sample
132 * rate.
133 */
134 if (es8328->deemph) {
135 best = 0;
136 for (i = 1; i < ARRAY_SIZE(deemph_settings); i++) {
137 if (abs(deemph_settings[i].rate - es8328->playback_fs) <
138 abs(deemph_settings[best].rate - es8328->playback_fs))
139 best = i;
140 }
141
142 val = deemph_settings[best].val;
143 } else {
144 val = ES8328_DACCONTROL6_DEEMPH_OFF;
145 }
146
147 dev_dbg(component->dev, "Set deemphasis %d\n", val);
148
149 return snd_soc_component_update_bits(component, ES8328_DACCONTROL6,
150 ES8328_DACCONTROL6_DEEMPH_MASK, val);
151 }
152
es8328_get_deemph(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)153 static int es8328_get_deemph(struct snd_kcontrol *kcontrol,
154 struct snd_ctl_elem_value *ucontrol)
155 {
156 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
157 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
158
159 ucontrol->value.integer.value[0] = es8328->deemph;
160 return 0;
161 }
162
es8328_put_deemph(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)163 static int es8328_put_deemph(struct snd_kcontrol *kcontrol,
164 struct snd_ctl_elem_value *ucontrol)
165 {
166 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
167 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
168 unsigned int deemph = ucontrol->value.integer.value[0];
169 int ret;
170
171 if (deemph > 1)
172 return -EINVAL;
173
174 if (es8328->deemph == deemph)
175 return 0;
176
177 ret = es8328_set_deemph(component);
178 if (ret < 0)
179 return ret;
180
181 es8328->deemph = deemph;
182
183 return 1;
184 }
185
186
187
188 static const struct snd_kcontrol_new es8328_snd_controls[] = {
189 SOC_DOUBLE_R_TLV("Capture Digital Volume",
190 ES8328_ADCCONTROL8, ES8328_ADCCONTROL9,
191 0, 0xc0, 1, dac_adc_tlv),
192 SOC_SINGLE("Capture ZC Switch", ES8328_ADCCONTROL7, 6, 1, 0),
193
194 SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
195 es8328_get_deemph, es8328_put_deemph),
196
197 SOC_ENUM("Capture Polarity", adcpol),
198
199 SOC_SINGLE_TLV("Left Mixer Left Bypass Volume",
200 ES8328_DACCONTROL17, 3, 7, 1, bypass_tlv),
201 SOC_SINGLE_TLV("Left Mixer Right Bypass Volume",
202 ES8328_DACCONTROL19, 3, 7, 1, bypass_tlv),
203 SOC_SINGLE_TLV("Right Mixer Left Bypass Volume",
204 ES8328_DACCONTROL18, 3, 7, 1, bypass_tlv),
205 SOC_SINGLE_TLV("Right Mixer Right Bypass Volume",
206 ES8328_DACCONTROL20, 3, 7, 1, bypass_tlv),
207
208 SOC_DOUBLE_R_TLV("PCM Volume",
209 ES8328_LDACVOL, ES8328_RDACVOL,
210 0, ES8328_DACVOL_MAX, 1, dac_adc_tlv),
211
212 SOC_DOUBLE_R_TLV("Output 1 Playback Volume",
213 ES8328_LOUT1VOL, ES8328_ROUT1VOL,
214 0, ES8328_OUT1VOL_MAX, 0, play_tlv),
215
216 SOC_DOUBLE_R_TLV("Output 2 Playback Volume",
217 ES8328_LOUT2VOL, ES8328_ROUT2VOL,
218 0, ES8328_OUT2VOL_MAX, 0, play_tlv),
219
220 SOC_DOUBLE_TLV("Mic PGA Volume", ES8328_ADCCONTROL1,
221 4, 0, 8, 0, mic_tlv),
222 };
223
224 /*
225 * DAPM Controls
226 */
227
228 static const char * const es8328_line_texts[] = {
229 "Line 1", "Line 2", "PGA", "Differential"};
230
231 static const struct soc_enum es8328_lline_enum =
232 SOC_ENUM_SINGLE(ES8328_DACCONTROL16, 3,
233 ARRAY_SIZE(es8328_line_texts),
234 es8328_line_texts);
235 static const struct snd_kcontrol_new es8328_left_line_controls =
236 SOC_DAPM_ENUM("Route", es8328_lline_enum);
237
238 static const struct soc_enum es8328_rline_enum =
239 SOC_ENUM_SINGLE(ES8328_DACCONTROL16, 0,
240 ARRAY_SIZE(es8328_line_texts),
241 es8328_line_texts);
242 static const struct snd_kcontrol_new es8328_right_line_controls =
243 SOC_DAPM_ENUM("Route", es8328_rline_enum);
244
245 /* Left Mixer */
246 static const struct snd_kcontrol_new es8328_left_mixer_controls[] = {
247 SOC_DAPM_SINGLE("Playback Switch", ES8328_DACCONTROL17, 7, 1, 0),
248 SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL17, 6, 1, 0),
249 SOC_DAPM_SINGLE("Right Playback Switch", ES8328_DACCONTROL18, 7, 1, 0),
250 SOC_DAPM_SINGLE("Right Bypass Switch", ES8328_DACCONTROL18, 6, 1, 0),
251 };
252
253 /* Right Mixer */
254 static const struct snd_kcontrol_new es8328_right_mixer_controls[] = {
255 SOC_DAPM_SINGLE("Left Playback Switch", ES8328_DACCONTROL19, 7, 1, 0),
256 SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL19, 6, 1, 0),
257 SOC_DAPM_SINGLE("Playback Switch", ES8328_DACCONTROL20, 7, 1, 0),
258 SOC_DAPM_SINGLE("Right Bypass Switch", ES8328_DACCONTROL20, 6, 1, 0),
259 };
260
261 static const char * const es8328_pga_sel[] = {
262 "Line 1", "Line 2", "Line 3", "Differential"};
263
264 /* Left PGA Mux */
265 static const struct soc_enum es8328_lpga_enum =
266 SOC_ENUM_SINGLE(ES8328_ADCCONTROL2, 6,
267 ARRAY_SIZE(es8328_pga_sel),
268 es8328_pga_sel);
269 static const struct snd_kcontrol_new es8328_left_pga_controls =
270 SOC_DAPM_ENUM("Route", es8328_lpga_enum);
271
272 /* Right PGA Mux */
273 static const struct soc_enum es8328_rpga_enum =
274 SOC_ENUM_SINGLE(ES8328_ADCCONTROL2, 4,
275 ARRAY_SIZE(es8328_pga_sel),
276 es8328_pga_sel);
277 static const struct snd_kcontrol_new es8328_right_pga_controls =
278 SOC_DAPM_ENUM("Route", es8328_rpga_enum);
279
280 /* Differential Mux */
281 static const char * const es8328_diff_sel[] = {"Line 1", "Line 2"};
282 static SOC_ENUM_SINGLE_DECL(diffmux,
283 ES8328_ADCCONTROL3, 7, es8328_diff_sel);
284 static const struct snd_kcontrol_new es8328_diffmux_controls =
285 SOC_DAPM_ENUM("Route", diffmux);
286
287 /* Mono ADC Mux */
288 static const char * const es8328_mono_mux[] = {"Stereo", "Mono (Left)",
289 "Mono (Right)", "Digital Mono"};
290 static SOC_ENUM_SINGLE_DECL(monomux,
291 ES8328_ADCCONTROL3, 3, es8328_mono_mux);
292 static const struct snd_kcontrol_new es8328_monomux_controls =
293 SOC_DAPM_ENUM("Route", monomux);
294
295 static const struct snd_soc_dapm_widget es8328_dapm_widgets[] = {
296 SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
297 &es8328_diffmux_controls),
298 SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
299 &es8328_monomux_controls),
300 SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
301 &es8328_monomux_controls),
302
303 SND_SOC_DAPM_MUX("Left PGA Mux", ES8328_ADCPOWER,
304 ES8328_ADCPOWER_AINL_OFF, 1,
305 &es8328_left_pga_controls),
306 SND_SOC_DAPM_MUX("Right PGA Mux", ES8328_ADCPOWER,
307 ES8328_ADCPOWER_AINR_OFF, 1,
308 &es8328_right_pga_controls),
309
310 SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
311 &es8328_left_line_controls),
312 SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
313 &es8328_right_line_controls),
314
315 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", ES8328_ADCPOWER,
316 ES8328_ADCPOWER_ADCR_OFF, 1),
317 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", ES8328_ADCPOWER,
318 ES8328_ADCPOWER_ADCL_OFF, 1),
319
320 SND_SOC_DAPM_SUPPLY("Mic Bias", ES8328_ADCPOWER,
321 ES8328_ADCPOWER_MIC_BIAS_OFF, 1, NULL, 0),
322 SND_SOC_DAPM_SUPPLY("Mic Bias Gen", ES8328_ADCPOWER,
323 ES8328_ADCPOWER_ADC_BIAS_GEN_OFF, 1, NULL, 0),
324
325 SND_SOC_DAPM_SUPPLY("DAC STM", ES8328_CHIPPOWER,
326 ES8328_CHIPPOWER_DACSTM_RESET, 1, NULL, 0),
327 SND_SOC_DAPM_SUPPLY("ADC STM", ES8328_CHIPPOWER,
328 ES8328_CHIPPOWER_ADCSTM_RESET, 1, NULL, 0),
329
330 SND_SOC_DAPM_SUPPLY("DAC DIG", ES8328_CHIPPOWER,
331 ES8328_CHIPPOWER_DACDIG_OFF, 1, NULL, 0),
332 SND_SOC_DAPM_SUPPLY("ADC DIG", ES8328_CHIPPOWER,
333 ES8328_CHIPPOWER_ADCDIG_OFF, 1, NULL, 0),
334
335 SND_SOC_DAPM_SUPPLY("DAC DLL", ES8328_CHIPPOWER,
336 ES8328_CHIPPOWER_DACDLL_OFF, 1, NULL, 0),
337 SND_SOC_DAPM_SUPPLY("ADC DLL", ES8328_CHIPPOWER,
338 ES8328_CHIPPOWER_ADCDLL_OFF, 1, NULL, 0),
339
340 SND_SOC_DAPM_SUPPLY("ADC Vref", ES8328_CHIPPOWER,
341 ES8328_CHIPPOWER_ADCVREF_OFF, 1, NULL, 0),
342 SND_SOC_DAPM_SUPPLY("DAC Vref", ES8328_CHIPPOWER,
343 ES8328_CHIPPOWER_DACVREF_OFF, 1, NULL, 0),
344
345 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", ES8328_DACPOWER,
346 ES8328_DACPOWER_RDAC_OFF, 1),
347 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", ES8328_DACPOWER,
348 ES8328_DACPOWER_LDAC_OFF, 1),
349
350 SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
351 &es8328_left_mixer_controls[0],
352 ARRAY_SIZE(es8328_left_mixer_controls)),
353 SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
354 &es8328_right_mixer_controls[0],
355 ARRAY_SIZE(es8328_right_mixer_controls)),
356
357 SND_SOC_DAPM_PGA("Right Out 2", ES8328_DACPOWER,
358 ES8328_DACPOWER_ROUT2_ON, 0, NULL, 0),
359 SND_SOC_DAPM_PGA("Left Out 2", ES8328_DACPOWER,
360 ES8328_DACPOWER_LOUT2_ON, 0, NULL, 0),
361 SND_SOC_DAPM_PGA("Right Out 1", ES8328_DACPOWER,
362 ES8328_DACPOWER_ROUT1_ON, 0, NULL, 0),
363 SND_SOC_DAPM_PGA("Left Out 1", ES8328_DACPOWER,
364 ES8328_DACPOWER_LOUT1_ON, 0, NULL, 0),
365
366 SND_SOC_DAPM_OUTPUT("LOUT1"),
367 SND_SOC_DAPM_OUTPUT("ROUT1"),
368 SND_SOC_DAPM_OUTPUT("LOUT2"),
369 SND_SOC_DAPM_OUTPUT("ROUT2"),
370
371 SND_SOC_DAPM_INPUT("LINPUT1"),
372 SND_SOC_DAPM_INPUT("LINPUT2"),
373 SND_SOC_DAPM_INPUT("RINPUT1"),
374 SND_SOC_DAPM_INPUT("RINPUT2"),
375 };
376
377 static const struct snd_soc_dapm_route es8328_dapm_routes[] = {
378
379 { "Left Line Mux", "Line 1", "LINPUT1" },
380 { "Left Line Mux", "Line 2", "LINPUT2" },
381 { "Left Line Mux", "PGA", "Left PGA Mux" },
382 { "Left Line Mux", "Differential", "Differential Mux" },
383
384 { "Right Line Mux", "Line 1", "RINPUT1" },
385 { "Right Line Mux", "Line 2", "RINPUT2" },
386 { "Right Line Mux", "PGA", "Right PGA Mux" },
387 { "Right Line Mux", "Differential", "Differential Mux" },
388
389 { "Left PGA Mux", "Line 1", "LINPUT1" },
390 { "Left PGA Mux", "Line 2", "LINPUT2" },
391 { "Left PGA Mux", "Differential", "Differential Mux" },
392
393 { "Right PGA Mux", "Line 1", "RINPUT1" },
394 { "Right PGA Mux", "Line 2", "RINPUT2" },
395 { "Right PGA Mux", "Differential", "Differential Mux" },
396
397 { "Differential Mux", "Line 1", "LINPUT1" },
398 { "Differential Mux", "Line 1", "RINPUT1" },
399 { "Differential Mux", "Line 2", "LINPUT2" },
400 { "Differential Mux", "Line 2", "RINPUT2" },
401
402 { "Left ADC Mux", "Stereo", "Left PGA Mux" },
403 { "Left ADC Mux", "Mono (Left)", "Left PGA Mux" },
404 { "Left ADC Mux", "Digital Mono", "Left PGA Mux" },
405
406 { "Right ADC Mux", "Stereo", "Right PGA Mux" },
407 { "Right ADC Mux", "Mono (Right)", "Right PGA Mux" },
408 { "Right ADC Mux", "Digital Mono", "Right PGA Mux" },
409
410 { "Left ADC", NULL, "Left ADC Mux" },
411 { "Right ADC", NULL, "Right ADC Mux" },
412
413 { "ADC DIG", NULL, "ADC STM" },
414 { "ADC DIG", NULL, "ADC Vref" },
415 { "ADC DIG", NULL, "ADC DLL" },
416
417 { "Left ADC", NULL, "ADC DIG" },
418 { "Right ADC", NULL, "ADC DIG" },
419
420 { "Mic Bias", NULL, "Mic Bias Gen" },
421
422 { "Left Line Mux", "Line 1", "LINPUT1" },
423 { "Left Line Mux", "Line 2", "LINPUT2" },
424 { "Left Line Mux", "PGA", "Left PGA Mux" },
425 { "Left Line Mux", "Differential", "Differential Mux" },
426
427 { "Right Line Mux", "Line 1", "RINPUT1" },
428 { "Right Line Mux", "Line 2", "RINPUT2" },
429 { "Right Line Mux", "PGA", "Right PGA Mux" },
430 { "Right Line Mux", "Differential", "Differential Mux" },
431
432 { "Left Out 1", NULL, "Left DAC" },
433 { "Right Out 1", NULL, "Right DAC" },
434 { "Left Out 2", NULL, "Left DAC" },
435 { "Right Out 2", NULL, "Right DAC" },
436
437 { "Left Mixer", "Playback Switch", "Left DAC" },
438 { "Left Mixer", "Left Bypass Switch", "Left Line Mux" },
439 { "Left Mixer", "Right Playback Switch", "Right DAC" },
440 { "Left Mixer", "Right Bypass Switch", "Right Line Mux" },
441
442 { "Right Mixer", "Left Playback Switch", "Left DAC" },
443 { "Right Mixer", "Left Bypass Switch", "Left Line Mux" },
444 { "Right Mixer", "Playback Switch", "Right DAC" },
445 { "Right Mixer", "Right Bypass Switch", "Right Line Mux" },
446
447 { "DAC DIG", NULL, "DAC STM" },
448 { "DAC DIG", NULL, "DAC Vref" },
449 { "DAC DIG", NULL, "DAC DLL" },
450
451 { "Left DAC", NULL, "DAC DIG" },
452 { "Right DAC", NULL, "DAC DIG" },
453
454 { "Left Out 1", NULL, "Left Mixer" },
455 { "LOUT1", NULL, "Left Out 1" },
456 { "Right Out 1", NULL, "Right Mixer" },
457 { "ROUT1", NULL, "Right Out 1" },
458
459 { "Left Out 2", NULL, "Left Mixer" },
460 { "LOUT2", NULL, "Left Out 2" },
461 { "Right Out 2", NULL, "Right Mixer" },
462 { "ROUT2", NULL, "Right Out 2" },
463 };
464
es8328_mute(struct snd_soc_dai * dai,int mute,int direction)465 static int es8328_mute(struct snd_soc_dai *dai, int mute, int direction)
466 {
467 return snd_soc_component_update_bits(dai->component, ES8328_DACCONTROL3,
468 ES8328_DACCONTROL3_DACMUTE,
469 mute ? ES8328_DACCONTROL3_DACMUTE : 0);
470 }
471
es8328_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)472 static int es8328_startup(struct snd_pcm_substream *substream,
473 struct snd_soc_dai *dai)
474 {
475 struct snd_soc_component *component = dai->component;
476 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
477
478 if (es8328->master && es8328->sysclk_constraints)
479 snd_pcm_hw_constraint_list(substream->runtime, 0,
480 SNDRV_PCM_HW_PARAM_RATE,
481 es8328->sysclk_constraints);
482
483 return 0;
484 }
485
es8328_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)486 static int es8328_hw_params(struct snd_pcm_substream *substream,
487 struct snd_pcm_hw_params *params,
488 struct snd_soc_dai *dai)
489 {
490 struct snd_soc_component *component = dai->component;
491 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
492 int i;
493 int reg;
494 int wl;
495 int ratio;
496
497 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
498 reg = ES8328_DACCONTROL2;
499 else
500 reg = ES8328_ADCCONTROL5;
501
502 if (es8328->master) {
503 if (!es8328->sysclk_constraints) {
504 dev_err(component->dev, "No MCLK configured\n");
505 return -EINVAL;
506 }
507
508 for (i = 0; i < es8328->sysclk_constraints->count; i++)
509 if (es8328->sysclk_constraints->list[i] ==
510 params_rate(params))
511 break;
512
513 if (i == es8328->sysclk_constraints->count) {
514 dev_err(component->dev,
515 "LRCLK %d unsupported with current clock\n",
516 params_rate(params));
517 return -EINVAL;
518 }
519 ratio = es8328->mclk_ratios[i];
520 } else {
521 ratio = 0;
522 es8328->mclkdiv2 = 0;
523 }
524
525 snd_soc_component_update_bits(component, ES8328_MASTERMODE,
526 ES8328_MASTERMODE_MCLKDIV2,
527 es8328->mclkdiv2 ? ES8328_MASTERMODE_MCLKDIV2 : 0);
528
529 switch (params_width(params)) {
530 case 16:
531 wl = 3;
532 break;
533 case 18:
534 wl = 2;
535 break;
536 case 20:
537 wl = 1;
538 break;
539 case 24:
540 wl = 0;
541 break;
542 case 32:
543 wl = 4;
544 break;
545 default:
546 return -EINVAL;
547 }
548
549 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
550 snd_soc_component_update_bits(component, ES8328_DACCONTROL1,
551 ES8328_DACCONTROL1_DACWL_MASK,
552 wl << ES8328_DACCONTROL1_DACWL_SHIFT);
553
554 es8328->playback_fs = params_rate(params);
555 es8328_set_deemph(component);
556 } else
557 snd_soc_component_update_bits(component, ES8328_ADCCONTROL4,
558 ES8328_ADCCONTROL4_ADCWL_MASK,
559 wl << ES8328_ADCCONTROL4_ADCWL_SHIFT);
560
561 return snd_soc_component_update_bits(component, reg, ES8328_RATEMASK, ratio);
562 }
563
es8328_set_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)564 static int es8328_set_sysclk(struct snd_soc_dai *codec_dai,
565 int clk_id, unsigned int freq, int dir)
566 {
567 struct snd_soc_component *component = codec_dai->component;
568 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
569 int mclkdiv2 = 0;
570
571 switch (freq) {
572 case 0:
573 es8328->sysclk_constraints = NULL;
574 es8328->mclk_ratios = NULL;
575 break;
576 case 22579200:
577 mclkdiv2 = 1;
578 fallthrough;
579 case 11289600:
580 es8328->sysclk_constraints = &constraints_11289;
581 es8328->mclk_ratios = ratios_11289;
582 break;
583 case 24576000:
584 mclkdiv2 = 1;
585 fallthrough;
586 case 12288000:
587 es8328->sysclk_constraints = &constraints_12288;
588 es8328->mclk_ratios = ratios_12288;
589 break;
590
591 case 24000000:
592 mclkdiv2 = 1;
593 fallthrough;
594 case 12000000:
595 es8328->sysclk_constraints = &constraints_12000;
596 es8328->mclk_ratios = ratios_12000;
597 break;
598 default:
599 return -EINVAL;
600 }
601
602 es8328->mclkdiv2 = mclkdiv2;
603 return 0;
604 }
605
es8328_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)606 static int es8328_set_dai_fmt(struct snd_soc_dai *codec_dai,
607 unsigned int fmt)
608 {
609 struct snd_soc_component *component = codec_dai->component;
610 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
611 u8 dac_mode = 0;
612 u8 adc_mode = 0;
613
614 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
615 case SND_SOC_DAIFMT_CBM_CFM:
616 /* Master serial port mode, with BCLK generated automatically */
617 snd_soc_component_update_bits(component, ES8328_MASTERMODE,
618 ES8328_MASTERMODE_MSC,
619 ES8328_MASTERMODE_MSC);
620 es8328->master = true;
621 break;
622 case SND_SOC_DAIFMT_CBS_CFS:
623 /* Slave serial port mode */
624 snd_soc_component_update_bits(component, ES8328_MASTERMODE,
625 ES8328_MASTERMODE_MSC, 0);
626 es8328->master = false;
627 break;
628 default:
629 return -EINVAL;
630 }
631
632 /* interface format */
633 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
634 case SND_SOC_DAIFMT_I2S:
635 dac_mode |= ES8328_DACCONTROL1_DACFORMAT_I2S;
636 adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_I2S;
637 break;
638 case SND_SOC_DAIFMT_RIGHT_J:
639 dac_mode |= ES8328_DACCONTROL1_DACFORMAT_RJUST;
640 adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_RJUST;
641 break;
642 case SND_SOC_DAIFMT_LEFT_J:
643 dac_mode |= ES8328_DACCONTROL1_DACFORMAT_LJUST;
644 adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_LJUST;
645 break;
646 default:
647 return -EINVAL;
648 }
649
650 /* clock inversion */
651 if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF)
652 return -EINVAL;
653
654 snd_soc_component_update_bits(component, ES8328_DACCONTROL1,
655 ES8328_DACCONTROL1_DACFORMAT_MASK, dac_mode);
656 snd_soc_component_update_bits(component, ES8328_ADCCONTROL4,
657 ES8328_ADCCONTROL4_ADCFORMAT_MASK, adc_mode);
658
659 return 0;
660 }
661
es8328_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)662 static int es8328_set_bias_level(struct snd_soc_component *component,
663 enum snd_soc_bias_level level)
664 {
665 switch (level) {
666 case SND_SOC_BIAS_ON:
667 break;
668
669 case SND_SOC_BIAS_PREPARE:
670 /* VREF, VMID=2x50k, digital enabled */
671 snd_soc_component_write(component, ES8328_CHIPPOWER, 0);
672 snd_soc_component_update_bits(component, ES8328_CONTROL1,
673 ES8328_CONTROL1_VMIDSEL_MASK |
674 ES8328_CONTROL1_ENREF,
675 ES8328_CONTROL1_VMIDSEL_50k |
676 ES8328_CONTROL1_ENREF);
677 break;
678
679 case SND_SOC_BIAS_STANDBY:
680 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
681 snd_soc_component_update_bits(component, ES8328_CONTROL1,
682 ES8328_CONTROL1_VMIDSEL_MASK |
683 ES8328_CONTROL1_ENREF,
684 ES8328_CONTROL1_VMIDSEL_5k |
685 ES8328_CONTROL1_ENREF);
686
687 /* Charge caps */
688 msleep(100);
689 }
690
691 snd_soc_component_write(component, ES8328_CONTROL2,
692 ES8328_CONTROL2_OVERCURRENT_ON |
693 ES8328_CONTROL2_THERMAL_SHUTDOWN_ON);
694
695 /* VREF, VMID=2*500k, digital stopped */
696 snd_soc_component_update_bits(component, ES8328_CONTROL1,
697 ES8328_CONTROL1_VMIDSEL_MASK |
698 ES8328_CONTROL1_ENREF,
699 ES8328_CONTROL1_VMIDSEL_500k |
700 ES8328_CONTROL1_ENREF);
701 break;
702
703 case SND_SOC_BIAS_OFF:
704 snd_soc_component_update_bits(component, ES8328_CONTROL1,
705 ES8328_CONTROL1_VMIDSEL_MASK |
706 ES8328_CONTROL1_ENREF,
707 0);
708 break;
709 }
710 return 0;
711 }
712
713 static const struct snd_soc_dai_ops es8328_dai_ops = {
714 .startup = es8328_startup,
715 .hw_params = es8328_hw_params,
716 .mute_stream = es8328_mute,
717 .set_sysclk = es8328_set_sysclk,
718 .set_fmt = es8328_set_dai_fmt,
719 .no_capture_mute = 1,
720 };
721
722 static struct snd_soc_dai_driver es8328_dai = {
723 .name = "es8328-hifi-analog",
724 .playback = {
725 .stream_name = "Playback",
726 .channels_min = 2,
727 .channels_max = 2,
728 .rates = ES8328_RATES,
729 .formats = ES8328_FORMATS,
730 },
731 .capture = {
732 .stream_name = "Capture",
733 .channels_min = 2,
734 .channels_max = 2,
735 .rates = ES8328_RATES,
736 .formats = ES8328_FORMATS,
737 },
738 .ops = &es8328_dai_ops,
739 .symmetric_rates = 1,
740 };
741
es8328_suspend(struct snd_soc_component * component)742 static int es8328_suspend(struct snd_soc_component *component)
743 {
744 struct es8328_priv *es8328;
745 int ret;
746
747 es8328 = snd_soc_component_get_drvdata(component);
748
749 clk_disable_unprepare(es8328->clk);
750
751 ret = regulator_bulk_disable(ARRAY_SIZE(es8328->supplies),
752 es8328->supplies);
753 if (ret) {
754 dev_err(component->dev, "unable to disable regulators\n");
755 return ret;
756 }
757 return 0;
758 }
759
es8328_resume(struct snd_soc_component * component)760 static int es8328_resume(struct snd_soc_component *component)
761 {
762 struct regmap *regmap = dev_get_regmap(component->dev, NULL);
763 struct es8328_priv *es8328;
764 int ret;
765
766 es8328 = snd_soc_component_get_drvdata(component);
767
768 ret = clk_prepare_enable(es8328->clk);
769 if (ret) {
770 dev_err(component->dev, "unable to enable clock\n");
771 return ret;
772 }
773
774 ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies),
775 es8328->supplies);
776 if (ret) {
777 dev_err(component->dev, "unable to enable regulators\n");
778 return ret;
779 }
780
781 regcache_mark_dirty(regmap);
782 ret = regcache_sync(regmap);
783 if (ret) {
784 dev_err(component->dev, "unable to sync regcache\n");
785 return ret;
786 }
787
788 return 0;
789 }
790
es8328_component_probe(struct snd_soc_component * component)791 static int es8328_component_probe(struct snd_soc_component *component)
792 {
793 struct es8328_priv *es8328;
794 int ret;
795
796 es8328 = snd_soc_component_get_drvdata(component);
797
798 ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies),
799 es8328->supplies);
800 if (ret) {
801 dev_err(component->dev, "unable to enable regulators\n");
802 return ret;
803 }
804
805 /* Setup clocks */
806 es8328->clk = devm_clk_get(component->dev, NULL);
807 if (IS_ERR(es8328->clk)) {
808 dev_err(component->dev, "codec clock missing or invalid\n");
809 ret = PTR_ERR(es8328->clk);
810 goto clk_fail;
811 }
812
813 ret = clk_prepare_enable(es8328->clk);
814 if (ret) {
815 dev_err(component->dev, "unable to prepare codec clk\n");
816 goto clk_fail;
817 }
818
819 return 0;
820
821 clk_fail:
822 regulator_bulk_disable(ARRAY_SIZE(es8328->supplies),
823 es8328->supplies);
824 return ret;
825 }
826
es8328_remove(struct snd_soc_component * component)827 static void es8328_remove(struct snd_soc_component *component)
828 {
829 struct es8328_priv *es8328;
830
831 es8328 = snd_soc_component_get_drvdata(component);
832
833 if (es8328->clk)
834 clk_disable_unprepare(es8328->clk);
835
836 regulator_bulk_disable(ARRAY_SIZE(es8328->supplies),
837 es8328->supplies);
838 }
839
840 const struct regmap_config es8328_regmap_config = {
841 .reg_bits = 8,
842 .val_bits = 8,
843 .max_register = ES8328_REG_MAX,
844 .cache_type = REGCACHE_RBTREE,
845 .use_single_read = true,
846 .use_single_write = true,
847 };
848 EXPORT_SYMBOL_GPL(es8328_regmap_config);
849
850 static const struct snd_soc_component_driver es8328_component_driver = {
851 .probe = es8328_component_probe,
852 .remove = es8328_remove,
853 .suspend = es8328_suspend,
854 .resume = es8328_resume,
855 .set_bias_level = es8328_set_bias_level,
856 .controls = es8328_snd_controls,
857 .num_controls = ARRAY_SIZE(es8328_snd_controls),
858 .dapm_widgets = es8328_dapm_widgets,
859 .num_dapm_widgets = ARRAY_SIZE(es8328_dapm_widgets),
860 .dapm_routes = es8328_dapm_routes,
861 .num_dapm_routes = ARRAY_SIZE(es8328_dapm_routes),
862 .suspend_bias_off = 1,
863 .idle_bias_on = 1,
864 .use_pmdown_time = 1,
865 .endianness = 1,
866 .non_legacy_dai_naming = 1,
867 };
868
es8328_probe(struct device * dev,struct regmap * regmap)869 int es8328_probe(struct device *dev, struct regmap *regmap)
870 {
871 struct es8328_priv *es8328;
872 int ret;
873 int i;
874
875 if (IS_ERR(regmap))
876 return PTR_ERR(regmap);
877
878 es8328 = devm_kzalloc(dev, sizeof(*es8328), GFP_KERNEL);
879 if (es8328 == NULL)
880 return -ENOMEM;
881
882 es8328->regmap = regmap;
883
884 for (i = 0; i < ARRAY_SIZE(es8328->supplies); i++)
885 es8328->supplies[i].supply = supply_names[i];
886
887 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(es8328->supplies),
888 es8328->supplies);
889 if (ret) {
890 dev_err(dev, "unable to get regulators\n");
891 return ret;
892 }
893
894 dev_set_drvdata(dev, es8328);
895
896 return devm_snd_soc_register_component(dev,
897 &es8328_component_driver, &es8328_dai, 1);
898 }
899 EXPORT_SYMBOL_GPL(es8328_probe);
900
901 MODULE_DESCRIPTION("ASoC ES8328 driver");
902 MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
903 MODULE_LICENSE("GPL");
904