xref: /OK3568_Linux_fs/kernel/sound/soc/codecs/es8326.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * es8326.c -- es8326 ALSA SoC audio driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (c) 2021 Everest Semiconductor Co Ltd.
6*4882a593Smuzhiyun  * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * Author: David <zhuning@everset-semi.com>
9*4882a593Smuzhiyun  * Author: Xing Zheng <zhengxing@rock-chips.com>
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or modify
12*4882a593Smuzhiyun  * it under the terms of the GNU General Public License version 2 as
13*4882a593Smuzhiyun  * published by the Free Software Foundation.
14*4882a593Smuzhiyun  */
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #include <linux/module.h>
17*4882a593Smuzhiyun #include <linux/moduleparam.h>
18*4882a593Smuzhiyun #include <linux/init.h>
19*4882a593Smuzhiyun #include <linux/clk.h>
20*4882a593Smuzhiyun #include <linux/delay.h>
21*4882a593Smuzhiyun #include <linux/pm.h>
22*4882a593Smuzhiyun #include <linux/i2c.h>
23*4882a593Smuzhiyun #include <linux/platform_device.h>
24*4882a593Smuzhiyun #include <linux/slab.h>
25*4882a593Smuzhiyun #include <linux/of_gpio.h>
26*4882a593Smuzhiyun #include <sound/core.h>
27*4882a593Smuzhiyun #include <sound/pcm.h>
28*4882a593Smuzhiyun #include <sound/pcm_params.h>
29*4882a593Smuzhiyun #include <sound/tlv.h>
30*4882a593Smuzhiyun #include <sound/soc.h>
31*4882a593Smuzhiyun #include <sound/soc-dapm.h>
32*4882a593Smuzhiyun #include <sound/initval.h>
33*4882a593Smuzhiyun #include <linux/proc_fs.h>
34*4882a593Smuzhiyun #include <linux/gpio.h>
35*4882a593Smuzhiyun #include <linux/interrupt.h>
36*4882a593Smuzhiyun #include <linux/irq.h>
37*4882a593Smuzhiyun #include <sound/jack.h>
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun #include "es8326.h"
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun #define ES8326_CODEC_SET_SPK	1
42*4882a593Smuzhiyun #define ES8326_CODEC_SET_HP	2
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun #define ES8326_LRCK		48000
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun /* codec private data */
47*4882a593Smuzhiyun struct es8326_priv {
48*4882a593Smuzhiyun 	struct clk *mclk;
49*4882a593Smuzhiyun 	struct snd_pcm_hw_constraint_list *sysclk_constraints;
50*4882a593Smuzhiyun 	struct i2c_client *i2c;
51*4882a593Smuzhiyun 	struct regmap *regmap;
52*4882a593Smuzhiyun 	struct snd_soc_component *component;
53*4882a593Smuzhiyun 	struct gpio_desc *hp_ctl_gpio;
54*4882a593Smuzhiyun 	struct gpio_desc *spk_ctl_gpio;
55*4882a593Smuzhiyun 	struct snd_soc_jack *jack;
56*4882a593Smuzhiyun 	struct delayed_work hpdet_work;
57*4882a593Smuzhiyun 	struct mutex lock;
58*4882a593Smuzhiyun 	int irq;
59*4882a593Smuzhiyun 	u8 mic1_src;
60*4882a593Smuzhiyun 	u8 mic2_src;
61*4882a593Smuzhiyun 	u8 jack_pol;
62*4882a593Smuzhiyun 	u32 mclk_rate;
63*4882a593Smuzhiyun 	bool mastermode;
64*4882a593Smuzhiyun 	bool hp_inserted;
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun /*
68*4882a593Smuzhiyun  * es8326 register cache
69*4882a593Smuzhiyun  * We can't read the es8326 register space when we
70*4882a593Smuzhiyun  * are using 2 wire for device control, so we cache them instead.
71*4882a593Smuzhiyun  */
72*4882a593Smuzhiyun static const struct reg_default es8326_reg_defaults[] = {
73*4882a593Smuzhiyun 	{0x00, 0x03}, {0x01, 0x03}, {0x02, 0x00}, {0x03, 0x20},
74*4882a593Smuzhiyun 	{0x04, 0x11}, {0x05, 0x00}, {0x06, 0x11}, {0x07, 0x00},
75*4882a593Smuzhiyun 	{0x08, 0x00}, {0x09, 0x01}, {0x0a, 0x00}, {0x0b, 0x00},
76*4882a593Smuzhiyun 	{0x0c, 0xf8}, {0x0d, 0x3f}, {0x0e, 0x00}, {0x0f, 0x00},
77*4882a593Smuzhiyun 	{0x10, 0x01}, {0x11, 0xfc}, {0x12, 0x28}, {0x13, 0x00},
78*4882a593Smuzhiyun 	{0x14, 0x00}, {0x15, 0x33}, {0x16, 0x00}, {0x17, 0x00},
79*4882a593Smuzhiyun 	{0x18, 0x88}, {0x19, 0x06}, {0x1a, 0x22}, {0x1b, 0x03},
80*4882a593Smuzhiyun 	{0x1c, 0x0f}, {0x1d, 0x00}, {0x1e, 0x80}, {0x1f, 0x80},
81*4882a593Smuzhiyun 	{0x20, 0x00}, {0x21, 0x00}, {0x22, 0xc0}, {0x23, 0x00},
82*4882a593Smuzhiyun 	{0x24, 0x01}, {0x25, 0x08}, {0x26, 0x10}, {0x27, 0xc0},
83*4882a593Smuzhiyun 	{0x28, 0x00}, {0x29, 0x1c}, {0x2a, 0x00}, {0x2b, 0xb0},
84*4882a593Smuzhiyun 	{0x2c, 0x32}, {0x2d, 0x03}, {0x2e, 0x00}, {0x2f, 0x11},
85*4882a593Smuzhiyun 	{0x30, 0x10}, {0x31, 0x00}, {0x32, 0x00}, {0x33, 0xc0},
86*4882a593Smuzhiyun 	{0x34, 0xc0}, {0x35, 0x1f}, {0x36, 0xf7}, {0x37, 0xfd},
87*4882a593Smuzhiyun 	{0x38, 0xff}, {0x39, 0x1f}, {0x3a, 0xf7}, {0x3b, 0xfd},
88*4882a593Smuzhiyun 	{0x3c, 0xff}, {0x3d, 0x1f}, {0x3e, 0xf7}, {0x3f, 0xfd},
89*4882a593Smuzhiyun 	{0x40, 0xff}, {0x41, 0x1f}, {0x42, 0xf7}, {0x43, 0xfd},
90*4882a593Smuzhiyun 	{0x44, 0xff}, {0x45, 0x1f}, {0x46, 0xf7}, {0x47, 0xfd},
91*4882a593Smuzhiyun 	{0x48, 0xff}, {0x49, 0x1f}, {0x4a, 0xf7}, {0x4b, 0xfd},
92*4882a593Smuzhiyun 	{0x4c, 0xff}, {0x4d, 0x00}, {0x4e, 0x00}, {0x4f, 0xff},
93*4882a593Smuzhiyun 	{0x50, 0x00}, {0x51, 0x00}, {0x52, 0x00}, {0x53, 0x00},
94*4882a593Smuzhiyun 	{0x54, 0x00}, {0x55, 0x00}, {0x56, 0x00}, {0x57, 0x1f},
95*4882a593Smuzhiyun 	{0x58, 0x00}, {0x59, 0x00}, {0x5a, 0x00}, {0x5b, 0x00},
96*4882a593Smuzhiyun 	{0x5c, 0x00}, {0xf9, 0x00}, {0xfa, 0x00}, {0xfb, 0x00},
97*4882a593Smuzhiyun 	{0xfc, 0x00}, {0xfd, 0x00}, {0xfe, 0x00}, {0xff, 0x00},
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun 
es8326_set_gpio(struct es8326_priv * es8326,int gpio,bool level)100*4882a593Smuzhiyun static int es8326_set_gpio(struct es8326_priv *es8326, int gpio, bool level)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun 	if (!es8326)
103*4882a593Smuzhiyun 		return 0;
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	if ((gpio & ES8326_CODEC_SET_SPK) && es8326->spk_ctl_gpio)
106*4882a593Smuzhiyun 		gpiod_set_value(es8326->spk_ctl_gpio, level);
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 	if ((gpio & ES8326_CODEC_SET_HP) && es8326->hp_ctl_gpio)
109*4882a593Smuzhiyun 		gpiod_set_value(es8326->hp_ctl_gpio, level);
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun 	return 0;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun 
es8326_hpdetect_work(struct work_struct * work)114*4882a593Smuzhiyun static void es8326_hpdetect_work(struct work_struct *work)
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun 	struct es8326_priv *es8326 =
117*4882a593Smuzhiyun 	    container_of(work, struct es8326_priv, hpdet_work.work);
118*4882a593Smuzhiyun 	struct device *dev = es8326->component->dev;
119*4882a593Smuzhiyun 	unsigned int iface;
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 	mutex_lock(&es8326->lock);
122*4882a593Smuzhiyun 	if (!es8326->jack)
123*4882a593Smuzhiyun 		goto out;
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	snd_soc_component_write(es8326->component, 0x1b, 0x7c);
126*4882a593Smuzhiyun 	msleep(200);
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	iface = snd_soc_component_read(es8326->component, 0xfb);
129*4882a593Smuzhiyun 	dev_dbg(dev, "%s fb=%#04x\n", __func__, iface);
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun 	if ((iface & 0x02) == 0) {
132*4882a593Smuzhiyun 		dev_dbg(dev, "No headset detected");
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 		snd_soc_jack_report(es8326->jack, 0, SND_JACK_HEADSET);
135*4882a593Smuzhiyun 		snd_soc_component_write(es8326->component, ES8326_ADC1_SRC_2A,
136*4882a593Smuzhiyun 					es8326->mic2_src);
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun 		es8326_set_gpio(es8326, ES8326_CODEC_SET_SPK, 1);
139*4882a593Smuzhiyun 		es8326_set_gpio(es8326, ES8326_CODEC_SET_HP, 1);
140*4882a593Smuzhiyun 		es8326->hp_inserted = 0;
141*4882a593Smuzhiyun 	} else if ((iface & 0x02) == 0x02) {
142*4882a593Smuzhiyun 		if ((iface & 0x01) == 0x00) {
143*4882a593Smuzhiyun 			/* iface == 0x02 is 4-Pole */
144*4882a593Smuzhiyun 			dev_dbg(dev, "Headset detected");
145*4882a593Smuzhiyun 			snd_soc_jack_report(es8326->jack, SND_JACK_HEADSET,
146*4882a593Smuzhiyun 					    SND_JACK_HEADSET);
147*4882a593Smuzhiyun 			snd_soc_component_write(es8326->component,
148*4882a593Smuzhiyun 						ES8326_ADC1_SRC_2A,
149*4882a593Smuzhiyun 						es8326->mic1_src);
150*4882a593Smuzhiyun 		} else {
151*4882a593Smuzhiyun 			/* iface == 0x03 is 3-Pole */
152*4882a593Smuzhiyun 			dev_dbg(dev, "Headphone detected");
153*4882a593Smuzhiyun 			snd_soc_jack_report(es8326->jack, SND_JACK_HEADPHONE,
154*4882a593Smuzhiyun 					    SND_JACK_HEADSET);
155*4882a593Smuzhiyun 		}
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 		es8326_set_gpio(es8326, ES8326_CODEC_SET_SPK, 0);
158*4882a593Smuzhiyun 		es8326_set_gpio(es8326, ES8326_CODEC_SET_HP, 0);
159*4882a593Smuzhiyun 		es8326->hp_inserted = 1;
160*4882a593Smuzhiyun 	}
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun out:
163*4882a593Smuzhiyun 	mutex_unlock(&es8326->lock);
164*4882a593Smuzhiyun 	snd_soc_component_write(es8326->component, 0x1b, 0x70);
165*4882a593Smuzhiyun }
166*4882a593Smuzhiyun 
es8326_irq(int irq,void * dev_id)167*4882a593Smuzhiyun static irqreturn_t es8326_irq(int irq, void *dev_id)
168*4882a593Smuzhiyun {
169*4882a593Smuzhiyun 	struct es8326_priv *es8326 = dev_id;
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun 	/*
172*4882a593Smuzhiyun 	 * For the high level irq trigger, disable irq and avoid a lot of
173*4882a593Smuzhiyun 	 * repeated irq handlers entry.
174*4882a593Smuzhiyun 	 */
175*4882a593Smuzhiyun 	queue_delayed_work(system_power_efficient_wq,
176*4882a593Smuzhiyun 			   &es8326->hpdet_work, msecs_to_jiffies(10));
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	return IRQ_HANDLED;
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(dac_vol_tlv, -9550, 50, 0);
182*4882a593Smuzhiyun static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(adc_vol_tlv, -9550, 50, 0);
183*4882a593Smuzhiyun static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(adc_pga_tlv, 0, 600, 0);
184*4882a593Smuzhiyun static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(softramp_rate, 0, 100, 0);
185*4882a593Smuzhiyun static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(drc_target_tlv, -3200, 200, 0);
186*4882a593Smuzhiyun static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(drc_recovery_tlv, -125, 250, 0);
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun static const char *const winsize[] = {
189*4882a593Smuzhiyun 	"0.25db/2  LRCK",
190*4882a593Smuzhiyun 	"0.25db/4  LRCK",
191*4882a593Smuzhiyun 	"0.25db/8  LRCK",
192*4882a593Smuzhiyun 	"0.25db/16  LRCK",
193*4882a593Smuzhiyun 	"0.25db/32  LRCK",
194*4882a593Smuzhiyun 	"0.25db/64  LRCK",
195*4882a593Smuzhiyun 	"0.25db/128  LRCK",
196*4882a593Smuzhiyun 	"0.25db/256  LRCK",
197*4882a593Smuzhiyun 	"0.25db/512  LRCK",
198*4882a593Smuzhiyun 	"0.25db/1024  LRCK",
199*4882a593Smuzhiyun 	"0.25db/2048  LRCK",
200*4882a593Smuzhiyun 	"0.25db/4096  LRCK",
201*4882a593Smuzhiyun 	"0.25db/8192  LRCK",
202*4882a593Smuzhiyun 	"0.25db/16384  LRCK",
203*4882a593Smuzhiyun 	"0.25db/32768  LRCK",
204*4882a593Smuzhiyun 	"0.25db/65536  LRCK",
205*4882a593Smuzhiyun };
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun static const char *const dacpol_txt[] = { "Normal", "R Invert", "L Invert", "L + R Invert" };
208*4882a593Smuzhiyun static const struct soc_enum dacpol = SOC_ENUM_SINGLE(0x4d, 4, 4, dacpol_txt);
209*4882a593Smuzhiyun static const struct soc_enum alc_winsize = SOC_ENUM_SINGLE(0x2e, 4, 16, winsize);
210*4882a593Smuzhiyun static const struct soc_enum drc_winsize = SOC_ENUM_SINGLE(0x54, 4, 16, winsize);
211*4882a593Smuzhiyun static const struct snd_kcontrol_new es8326_snd_controls[] = {
212*4882a593Smuzhiyun 	SOC_SINGLE_TLV("DAC Playback Volume", 0x50, 0, 0xff, 0,
213*4882a593Smuzhiyun 		       dac_vol_tlv),
214*4882a593Smuzhiyun 	SOC_ENUM("Playback Polarity", dacpol),
215*4882a593Smuzhiyun 	SOC_SINGLE_TLV("DAC Ramp Rate", 0x4e, 0, 0x0f, 0,
216*4882a593Smuzhiyun 		       softramp_rate),
217*4882a593Smuzhiyun 	SOC_SINGLE("DRC Switch", 0x53, 3, 1, 0),
218*4882a593Smuzhiyun 	SOC_SINGLE_TLV("DRC Recovery Level", 0x53, 0, 4, 0, drc_recovery_tlv),
219*4882a593Smuzhiyun 	SOC_ENUM("DRC Winsize", drc_winsize),
220*4882a593Smuzhiyun 	SOC_SINGLE_TLV("DRC Target Level", 0x54, 0, 0x0f, 0,
221*4882a593Smuzhiyun 		       drc_target_tlv),
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun 	SOC_DOUBLE_R_TLV("ADC Capture Volume", 0x2C, 0x2D, 0, 0xff, 0,
224*4882a593Smuzhiyun 			 adc_vol_tlv),
225*4882a593Smuzhiyun 	SOC_DOUBLE_TLV("ADC PGA Gain", 0x29, 4, 0, 5, 0, adc_pga_tlv),
226*4882a593Smuzhiyun 	SOC_SINGLE_TLV("ADC Ramp Rate", 0x2e, 0, 0x0f, 0,
227*4882a593Smuzhiyun 		       softramp_rate),
228*4882a593Smuzhiyun 	SOC_SINGLE("ALC Switch", 0x32, 3, 1, 0),
229*4882a593Smuzhiyun 	SOC_SINGLE_TLV("ALC Recovery Level", 0x33, 0, 4, 0, drc_recovery_tlv),
230*4882a593Smuzhiyun 	SOC_ENUM("ALC Winsize", alc_winsize),
231*4882a593Smuzhiyun 	SOC_SINGLE_TLV("ALC Target Level", 0x33, 0, 0x0f, 0,
232*4882a593Smuzhiyun 		       drc_target_tlv),
233*4882a593Smuzhiyun };
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun static const struct snd_soc_dapm_widget es8326_dapm_widgets[] = {
236*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("MIC1"),
237*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("MIC2"),
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun 	SND_SOC_DAPM_ADC("Right ADC", NULL, SND_SOC_NOPM, 0, 0),
240*4882a593Smuzhiyun 	SND_SOC_DAPM_ADC("Left ADC", NULL, SND_SOC_NOPM, 0, 0),
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun 	/* Digital Interface */
243*4882a593Smuzhiyun 	SND_SOC_DAPM_AIF_OUT("I2S OUT", "Capture", 0,
244*4882a593Smuzhiyun 			     SND_SOC_NOPM, 0, 0),
245*4882a593Smuzhiyun 	SND_SOC_DAPM_AIF_IN("I2S IN", "Playback", 0,
246*4882a593Smuzhiyun 			    SND_SOC_NOPM, 0, 0),
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 	SND_SOC_DAPM_DAC("Right DAC", NULL, ES8326_ANA_PDN_16, 0, 1),
249*4882a593Smuzhiyun 	SND_SOC_DAPM_DAC("Left DAC", NULL, ES8326_ANA_PDN_16, 1, 1),
250*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA("LHPMIX", 0x25, 7, 0, NULL, 0),
251*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA("RHPMIX", 0x25, 3, 0, NULL, 0),
252*4882a593Smuzhiyun 	SND_SOC_DAPM_SUPPLY("HPOR Cal", 0x27, 7, 1, NULL, 0),
253*4882a593Smuzhiyun 	SND_SOC_DAPM_SUPPLY("HPOL Cal", 0x27, 3, 1, NULL, 0),
254*4882a593Smuzhiyun 	SND_SOC_DAPM_REG(snd_soc_dapm_supply, "HPOR Supply", 0x27,
255*4882a593Smuzhiyun 			 4, (7 << 4), (7 << 4), 0),
256*4882a593Smuzhiyun 	SND_SOC_DAPM_REG(snd_soc_dapm_supply, "HPOL Supply", 0x27,
257*4882a593Smuzhiyun 			 0, 7, 7, 0),
258*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("HPOL"),
259*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("HPOR"),
260*4882a593Smuzhiyun };
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun static const struct snd_soc_dapm_route es8326_dapm_routes[] = {
263*4882a593Smuzhiyun 	{"Left ADC", NULL, "MIC1"},
264*4882a593Smuzhiyun 	{"Right ADC", NULL, "MIC2"},
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 	{"I2S OUT", NULL, "Left ADC"},
267*4882a593Smuzhiyun 	{"I2S OUT", NULL, "Right ADC"},
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun 	{"Right DAC", NULL, "I2S IN"},
270*4882a593Smuzhiyun 	{"Left DAC", NULL, "I2S IN"},
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun 	{"LHPMIX", NULL, "Left DAC"},
273*4882a593Smuzhiyun 	{"RHPMIX", NULL, "Right DAC"},
274*4882a593Smuzhiyun 
275*4882a593Smuzhiyun 	{"HPOR", NULL, "HPOR Cal"},
276*4882a593Smuzhiyun 	{"HPOL", NULL, "HPOL Cal"},
277*4882a593Smuzhiyun 	{"HPOR", NULL, "HPOR Supply"},
278*4882a593Smuzhiyun 	{"HPOL", NULL, "HPOL Supply"},
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun 	{"HPOL", NULL, "LHPMIX"},
281*4882a593Smuzhiyun 	{"HPOR", NULL, "RHPMIX"},
282*4882a593Smuzhiyun };
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun static const struct regmap_range es8326_volatile_ranges[] = {
285*4882a593Smuzhiyun 	regmap_reg_range(0xfb, 0xfb),
286*4882a593Smuzhiyun };
287*4882a593Smuzhiyun 
288*4882a593Smuzhiyun static const struct regmap_access_table es8326_volatile_table = {
289*4882a593Smuzhiyun 	.yes_ranges = es8326_volatile_ranges,
290*4882a593Smuzhiyun 	.n_yes_ranges = ARRAY_SIZE(es8326_volatile_ranges),
291*4882a593Smuzhiyun };
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun const struct regmap_config es8326_regmap_config = {
294*4882a593Smuzhiyun 	.reg_bits = 8,
295*4882a593Smuzhiyun 	.val_bits = 8,
296*4882a593Smuzhiyun 	.max_register = 0xff,
297*4882a593Smuzhiyun 	.volatile_table = &es8326_volatile_table,
298*4882a593Smuzhiyun 	.cache_type = REGCACHE_RBTREE,
299*4882a593Smuzhiyun };
300*4882a593Smuzhiyun 
301*4882a593Smuzhiyun struct _coeff_div {
302*4882a593Smuzhiyun 	u16 fs;
303*4882a593Smuzhiyun 	u32 rate;
304*4882a593Smuzhiyun 	u32 mclk;
305*4882a593Smuzhiyun 	u8 reg4;
306*4882a593Smuzhiyun 	u8 reg5;
307*4882a593Smuzhiyun 	u8 reg6;
308*4882a593Smuzhiyun 	u8 reg7;
309*4882a593Smuzhiyun 	u8 reg8;
310*4882a593Smuzhiyun 	u8 reg9;
311*4882a593Smuzhiyun 	u8 rega;
312*4882a593Smuzhiyun 	u8 regb;
313*4882a593Smuzhiyun };
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun /* codec hifi mclk clock divider coefficients */
316*4882a593Smuzhiyun static const struct _coeff_div coeff_div[] = {
317*4882a593Smuzhiyun 	/* ratio,LRCK,MCLK,REG04,REG05,REG06,REG07,REG08,REG09,REG10,REG11 */
318*4882a593Smuzhiyun 	{32, 8000, 256000, 0x60, 0x00, 0x0F, 0x75, 0x0A, 0x1B, 0x1F, 0x7F},
319*4882a593Smuzhiyun 	{32, 16000, 512000, 0x20, 0x00, 0x0D, 0x75, 0x0A, 0x1B, 0x1F, 0x3F},
320*4882a593Smuzhiyun 	{32, 44100, 1411200, 0x00, 0x00, 0x13, 0x2D, 0x0A, 0x0A, 0x1F, 0x1F},
321*4882a593Smuzhiyun 	{32, 48000, 1536000, 0x00, 0x00, 0x13, 0x2D, 0x0A, 0x0A, 0x1F, 0x1F},
322*4882a593Smuzhiyun 	{36, 8000, 288000, 0x20, 0x00, 0x0D, 0x75, 0x0A, 0x1B, 0x23, 0x47},
323*4882a593Smuzhiyun 	{36, 16000, 576000, 0x20, 0x00, 0x0D, 0x75, 0x0A, 0x1B, 0x23, 0x47},
324*4882a593Smuzhiyun 	{48, 8000, 384000, 0x60, 0x02, 0x1F, 0x75, 0x0A, 0x1B, 0x1F, 0x7F},
325*4882a593Smuzhiyun 	{48, 16000, 768000, 0x20, 0x02, 0x0F, 0x75, 0x0A, 0x1B, 0x1F, 0x3F},
326*4882a593Smuzhiyun 	{48, 48000, 2304000, 0x00, 0x02, 0x0D, 0x2D, 0x0A, 0x0A, 0x1F, 0x1F},
327*4882a593Smuzhiyun 	{64, 8000, 512000, 0x60, 0x00, 0x0D, 0x75, 0x0A, 0x1B, 0x1F, 0x7F},
328*4882a593Smuzhiyun 	{64, 16000, 1024000, 0x20, 0x00, 0x05, 0x75, 0x0A, 0x1B, 0x1F, 0x3F},
329*4882a593Smuzhiyun 
330*4882a593Smuzhiyun 	{64, 44100, 2822400, 0x00, 0x00, 0x11, 0x2D, 0x0A, 0x0A, 0x1F, 0x1F},
331*4882a593Smuzhiyun 	{64, 48000, 3072000, 0x00, 0x00, 0x11, 0x2D, 0x0A, 0x0A, 0x1F, 0x1F},
332*4882a593Smuzhiyun 	{72, 8000, 576000, 0x20, 0x00, 0x13, 0x35, 0x0A, 0x1B, 0x23, 0x47},
333*4882a593Smuzhiyun 	{72, 16000, 1152000, 0x20, 0x00, 0x05, 0x75, 0x0A, 0x1B, 0x23, 0x47},
334*4882a593Smuzhiyun 	{96, 8000, 768000, 0x60, 0x02, 0x1D, 0x75, 0x0A, 0x1B, 0x1F, 0x7F},
335*4882a593Smuzhiyun 	{96, 16000, 1536000, 0x20, 0x02, 0x0D, 0x75, 0x0A, 0x1B, 0x1F, 0x3F},
336*4882a593Smuzhiyun 	{100, 48000, 4800000, 0x04, 0x04, 0x1F, 0x2D, 0x0A, 0x0A, 0x1F, 0x1F},
337*4882a593Smuzhiyun 	{125, 48000, 6000000, 0x04, 0x04, 0x1F, 0x2D, 0x0A, 0x0A, 0x27, 0x27},
338*4882a593Smuzhiyun 	{128, 8000, 1024000, 0x60, 0x00, 0x13, 0x35, 0x0A, 0x1B, 0x1F, 0x7F},
339*4882a593Smuzhiyun 	{128, 16000, 2048000, 0x20, 0x00, 0x11, 0x35, 0x0A, 0x1B, 0x1F, 0x3F},
340*4882a593Smuzhiyun 
341*4882a593Smuzhiyun 	{128, 44100, 5644800, 0x00, 0x00, 0x01, 0x2D, 0x0A, 0x0A, 0x1F, 0x1F},
342*4882a593Smuzhiyun 	{128, 48000, 6144000, 0x00, 0x00, 0x01, 0x2D, 0x0A, 0x0A, 0x1F, 0x1F},
343*4882a593Smuzhiyun 	{144, 8000, 1152000, 0x20, 0x00, 0x03, 0x35, 0x0A, 0x1B, 0x23, 0x47},
344*4882a593Smuzhiyun 	{144, 16000, 2304000, 0x20, 0x00, 0x11, 0x35, 0x0A, 0x1B, 0x23, 0x47},
345*4882a593Smuzhiyun 	{192, 8000, 1536000, 0x60, 0x02, 0x0D, 0x75, 0x0A, 0x1B, 0x1F, 0x7F},
346*4882a593Smuzhiyun 	{192, 16000, 3072000, 0x20, 0x02, 0x05, 0x75, 0x0A, 0x1B, 0x1F, 0x3F},
347*4882a593Smuzhiyun 	{200, 48000, 9600000, 0x04, 0x04, 0x0F, 0x2D, 0x0A, 0x0A, 0x1F, 0x1F},
348*4882a593Smuzhiyun 	{250, 48000, 12000000, 0x04, 0x04, 0x0F, 0x2D, 0x0A, 0x0A, 0x27, 0x27},
349*4882a593Smuzhiyun 	{256, 8000, 2048000, 0x60, 0x00, 0x11, 0x35, 0x0A, 0x1B, 0x1F, 0x7F},
350*4882a593Smuzhiyun 	{256, 16000, 4096000, 0x20, 0x00, 0x01, 0x35, 0x0A, 0x1B, 0x1F, 0x3F},
351*4882a593Smuzhiyun 	{256, 44100, 11289600, 0x20, 0x00, 0x30, 0x2B, 0x1A, 0xFF, 0x4F, 0x1F},
352*4882a593Smuzhiyun 	{256, 48000, 12288000, 0x00, 0x00, 0x30, 0x2B, 0x1A, 0x0A, 0x4F, 0x1F},
353*4882a593Smuzhiyun 
354*4882a593Smuzhiyun 	{288, 8000, 2304000, 0x20, 0x00, 0x01, 0x35, 0x0A, 0x1B, 0x23, 0x47},
355*4882a593Smuzhiyun 	{384, 8000, 3072000, 0x60, 0x02, 0x05, 0x75, 0x0A, 0x1B, 0x1F, 0x7F},
356*4882a593Smuzhiyun 	{384, 16000, 6144000, 0x20, 0x02, 0x03, 0x35, 0x0A, 0x1B, 0x1F, 0x3F},
357*4882a593Smuzhiyun 	{384, 48000, 18432000, 0x00, 0x02, 0x01, 0x2D, 0x0A, 0x0A, 0x1F, 0x1F},
358*4882a593Smuzhiyun 	{400, 48000, 19200000, 0x09, 0x04, 0x0f, 0x6d, 0x3a, 0x0A, 0x4F, 0x1F},
359*4882a593Smuzhiyun 	{500, 48000, 24000000, 0x18, 0x04, 0x1F, 0x2D, 0x0A, 0x0A, 0x1F, 0x1F},
360*4882a593Smuzhiyun 	{512, 8000, 4096000, 0x60, 0x00, 0x01, 0x35, 0x0A, 0x1B, 0x1F, 0x7F},
361*4882a593Smuzhiyun 	{512, 16000, 8192000, 0x20, 0x00, 0x10, 0x35, 0x0A, 0x1B, 0x1F, 0x3F},
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun 	{512, 44100, 22579200, 0x00, 0x00, 0x00, 0x2D, 0x0A, 0x0A, 0x1F, 0x1F},
364*4882a593Smuzhiyun 	{512, 48000, 24576000, 0x00, 0x00, 0x00, 0x2D, 0x0A, 0x0A, 0x1F, 0x1F},
365*4882a593Smuzhiyun 	{768, 8000, 6144000, 0x60, 0x02, 0x11, 0x35, 0x0A, 0x1B, 0x1F, 0x7F},
366*4882a593Smuzhiyun 	{768, 16000, 12288000, 0x20, 0x02, 0x01, 0x35, 0x0A, 0x1B, 0x1F, 0x3F},
367*4882a593Smuzhiyun 	{800, 48000, 38400000, 0x00, 0x18, 0x13, 0x2D, 0x0A, 0x0A, 0x1F, 0x1F},
368*4882a593Smuzhiyun 	{1024, 8000, 8192000, 0x60, 0x00, 0x10, 0x35, 0x0A, 0x1B, 0x1F, 0x7F},
369*4882a593Smuzhiyun 	{1024, 16000, 16384000, 0x20, 0x00, 0x00, 0x35, 0x0A, 0x1B, 0x1F, 0x3F},
370*4882a593Smuzhiyun 	{1152, 16000, 18432000, 0x20, 0x08, 0x11, 0x35, 0x0A, 0x1B, 0x1F, 0x3F},
371*4882a593Smuzhiyun 	{1536, 8000, 12288000, 0x60, 0x02, 0x01, 0x35, 0x0A, 0x1B, 0x1F, 0x7F},
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun 	{1536, 16000, 24576000, 0x20, 0x02, 0x10, 0x35, 0x0A, 0x1B, 0x1F, 0x3F},
374*4882a593Smuzhiyun 	{1625, 8000, 13000000, 0x0C, 0x18, 0x1F, 0x2D, 0x0A, 0x0A, 0x27, 0x27},
375*4882a593Smuzhiyun 	{1625, 16000, 26000000, 0x0C, 0x18, 0x1F, 0x2D, 0x0A, 0x0A, 0x27, 0x27},
376*4882a593Smuzhiyun 	{2048, 8000, 16384000, 0x60, 0x00, 0x00, 0x35, 0x0A, 0x1B, 0x1F, 0x7F},
377*4882a593Smuzhiyun 	{2304, 8000, 18432000, 0x40, 0x02, 0x10, 0x35, 0x0A, 0x1B, 0x1F, 0x5F},
378*4882a593Smuzhiyun 	{3072, 8000, 24576000, 0x60, 0x02, 0x10, 0x35, 0x0A, 0x1B, 0x1F, 0x7F},
379*4882a593Smuzhiyun 	{3250, 8000, 26000000, 0x0C, 0x18, 0x0F, 0x2D, 0x0A, 0x0A, 0x27, 0x27},
380*4882a593Smuzhiyun };
381*4882a593Smuzhiyun 
get_coeff(int mclk,int rate)382*4882a593Smuzhiyun static inline int get_coeff(int mclk, int rate)
383*4882a593Smuzhiyun {
384*4882a593Smuzhiyun 	int i;
385*4882a593Smuzhiyun 
386*4882a593Smuzhiyun 	rate = ES8326_LRCK;
387*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
388*4882a593Smuzhiyun 		if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
389*4882a593Smuzhiyun 			return i;
390*4882a593Smuzhiyun 	}
391*4882a593Smuzhiyun 
392*4882a593Smuzhiyun 	return -EINVAL;
393*4882a593Smuzhiyun }
394*4882a593Smuzhiyun 
395*4882a593Smuzhiyun /* The set of rates we can generate from the above for each SYSCLK */
396*4882a593Smuzhiyun static unsigned int rates_12288[] = {
397*4882a593Smuzhiyun 	8000, 12000, 16000, 24000, 24000, 32000, 48000, 96000,
398*4882a593Smuzhiyun };
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun static struct snd_pcm_hw_constraint_list constraints_12288 = {
401*4882a593Smuzhiyun 	.count = ARRAY_SIZE(rates_12288),
402*4882a593Smuzhiyun 	.list = rates_12288,
403*4882a593Smuzhiyun };
404*4882a593Smuzhiyun 
405*4882a593Smuzhiyun static unsigned int rates_112896[] = {
406*4882a593Smuzhiyun 	8000, 11025, 22050, 44100,
407*4882a593Smuzhiyun };
408*4882a593Smuzhiyun 
409*4882a593Smuzhiyun static struct snd_pcm_hw_constraint_list constraints_112896 = {
410*4882a593Smuzhiyun 	.count = ARRAY_SIZE(rates_112896),
411*4882a593Smuzhiyun 	.list = rates_112896,
412*4882a593Smuzhiyun };
413*4882a593Smuzhiyun 
414*4882a593Smuzhiyun static unsigned int rates_12[] = {
415*4882a593Smuzhiyun 	8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000,
416*4882a593Smuzhiyun 	48000, 88235, 96000,
417*4882a593Smuzhiyun };
418*4882a593Smuzhiyun 
419*4882a593Smuzhiyun static struct snd_pcm_hw_constraint_list constraints_12 = {
420*4882a593Smuzhiyun 	.count = ARRAY_SIZE(rates_12),
421*4882a593Smuzhiyun 	.list = rates_12,
422*4882a593Smuzhiyun };
423*4882a593Smuzhiyun 
424*4882a593Smuzhiyun /*
425*4882a593Smuzhiyun  * Note that this should be called from init rather than from hw_params.
426*4882a593Smuzhiyun  */
es8326_set_dai_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)427*4882a593Smuzhiyun static int es8326_set_dai_sysclk(struct snd_soc_dai *codec_dai,
428*4882a593Smuzhiyun 				 int clk_id, unsigned int freq, int dir)
429*4882a593Smuzhiyun {
430*4882a593Smuzhiyun 	struct snd_soc_component *component = codec_dai->component;
431*4882a593Smuzhiyun 	struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
432*4882a593Smuzhiyun 	unsigned int freq2 = es8326->mclk_rate;
433*4882a593Smuzhiyun 
434*4882a593Smuzhiyun 	if (freq == 0) {
435*4882a593Smuzhiyun 		es8326->sysclk_constraints->list = NULL;
436*4882a593Smuzhiyun 		es8326->sysclk_constraints->count = 0;
437*4882a593Smuzhiyun 		return 0;
438*4882a593Smuzhiyun 	}
439*4882a593Smuzhiyun 
440*4882a593Smuzhiyun 	switch (freq2) {
441*4882a593Smuzhiyun 	case 11289600:
442*4882a593Smuzhiyun 	case 18432000:
443*4882a593Smuzhiyun 	case 22579200:
444*4882a593Smuzhiyun 	case 36864000:
445*4882a593Smuzhiyun 		es8326->sysclk_constraints = &constraints_112896;
446*4882a593Smuzhiyun 		return 0;
447*4882a593Smuzhiyun 
448*4882a593Smuzhiyun 	case 12288000:
449*4882a593Smuzhiyun 	case 16934400:
450*4882a593Smuzhiyun 	case 24576000:
451*4882a593Smuzhiyun 	case 33868800:
452*4882a593Smuzhiyun 		es8326->sysclk_constraints = &constraints_12288;
453*4882a593Smuzhiyun 		return 0;
454*4882a593Smuzhiyun 
455*4882a593Smuzhiyun 	case 12000000:
456*4882a593Smuzhiyun 	case 19200000:
457*4882a593Smuzhiyun 	case 24000000:
458*4882a593Smuzhiyun 		es8326->sysclk_constraints = &constraints_12;
459*4882a593Smuzhiyun 		return 0;
460*4882a593Smuzhiyun 	}
461*4882a593Smuzhiyun 
462*4882a593Smuzhiyun 	return -EINVAL;
463*4882a593Smuzhiyun }
464*4882a593Smuzhiyun 
es8326_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)465*4882a593Smuzhiyun static int es8326_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
466*4882a593Smuzhiyun {
467*4882a593Smuzhiyun 
468*4882a593Smuzhiyun 	struct snd_soc_component *component = codec_dai->component;
469*4882a593Smuzhiyun 	u8 iface = snd_soc_component_read(component, ES8326_FMT_13);
470*4882a593Smuzhiyun 
471*4882a593Smuzhiyun 	/* interface format */
472*4882a593Smuzhiyun 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
473*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_I2S:
474*4882a593Smuzhiyun 		iface &= 0xFC;
475*4882a593Smuzhiyun 		break;
476*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_RIGHT_J:
477*4882a593Smuzhiyun 		break;
478*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_LEFT_J:
479*4882a593Smuzhiyun 		break;
480*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_DSP_A:
481*4882a593Smuzhiyun 		break;
482*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_DSP_B:
483*4882a593Smuzhiyun 		break;
484*4882a593Smuzhiyun 	default:
485*4882a593Smuzhiyun 		return -EINVAL;
486*4882a593Smuzhiyun 	}
487*4882a593Smuzhiyun 
488*4882a593Smuzhiyun 	snd_soc_component_write(component, ES8326_FMT_13, iface);
489*4882a593Smuzhiyun 
490*4882a593Smuzhiyun 	return 0;
491*4882a593Smuzhiyun }
492*4882a593Smuzhiyun 
es8326_pcm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)493*4882a593Smuzhiyun static int es8326_pcm_hw_params(struct snd_pcm_substream *substream,
494*4882a593Smuzhiyun 				struct snd_pcm_hw_params *params,
495*4882a593Smuzhiyun 				struct snd_soc_dai *dai)
496*4882a593Smuzhiyun {
497*4882a593Smuzhiyun 	struct snd_soc_component *component = dai->component;
498*4882a593Smuzhiyun 	struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
499*4882a593Smuzhiyun 	u8 srate = snd_soc_component_read(component, ES8326_FMT_13) & 0xe3;
500*4882a593Smuzhiyun 	int coeff = get_coeff(es8326->mclk_rate, params_rate(params));
501*4882a593Smuzhiyun 
502*4882a593Smuzhiyun 	/* bit size */
503*4882a593Smuzhiyun 	switch (params_format(params)) {
504*4882a593Smuzhiyun 	case SNDRV_PCM_FORMAT_S16_LE:
505*4882a593Smuzhiyun 		srate |= 0x0C;
506*4882a593Smuzhiyun 		break;
507*4882a593Smuzhiyun 	case SNDRV_PCM_FORMAT_S20_3LE:
508*4882a593Smuzhiyun 		srate |= 0x04;
509*4882a593Smuzhiyun 		break;
510*4882a593Smuzhiyun 	case SNDRV_PCM_FORMAT_S18_3LE:
511*4882a593Smuzhiyun 		srate |= 0x08;
512*4882a593Smuzhiyun 	case SNDRV_PCM_FORMAT_S24_LE:
513*4882a593Smuzhiyun 		break;
514*4882a593Smuzhiyun 	case SNDRV_PCM_FORMAT_S32_LE:
515*4882a593Smuzhiyun 		srate |= 0x10;
516*4882a593Smuzhiyun 		break;
517*4882a593Smuzhiyun 	}
518*4882a593Smuzhiyun 
519*4882a593Smuzhiyun 	/* set iface & srate */
520*4882a593Smuzhiyun 	snd_soc_component_write(component, ES8326_FMT_13, srate);
521*4882a593Smuzhiyun 
522*4882a593Smuzhiyun 	if (coeff >= 0) {
523*4882a593Smuzhiyun 		snd_soc_component_write(component, ES8326_CLK_DIV1_04,
524*4882a593Smuzhiyun 					coeff_div[coeff].reg4);
525*4882a593Smuzhiyun 		snd_soc_component_write(component, ES8326_CLK_DIV2_05,
526*4882a593Smuzhiyun 					coeff_div[coeff].reg5);
527*4882a593Smuzhiyun 		snd_soc_component_write(component, ES8326_CLK_DLL_06,
528*4882a593Smuzhiyun 					coeff_div[coeff].reg6);
529*4882a593Smuzhiyun 		snd_soc_component_write(component, ES8326_CLK_MUX_07,
530*4882a593Smuzhiyun 					coeff_div[coeff].reg7);
531*4882a593Smuzhiyun 		snd_soc_component_write(component, ES8326_CLK_ADC_SEL_08,
532*4882a593Smuzhiyun 					coeff_div[coeff].reg8);
533*4882a593Smuzhiyun 		snd_soc_component_write(component, ES8326_CLK_DAC_SEL_09,
534*4882a593Smuzhiyun 					coeff_div[coeff].reg9);
535*4882a593Smuzhiyun 		snd_soc_component_write(component, ES8326_CLK_ADC_OSR_0A,
536*4882a593Smuzhiyun 					coeff_div[coeff].rega);
537*4882a593Smuzhiyun 		snd_soc_component_write(component, ES8326_CLK_DAC_OSR_0B,
538*4882a593Smuzhiyun 					coeff_div[coeff].regb);
539*4882a593Smuzhiyun 	}
540*4882a593Smuzhiyun 
541*4882a593Smuzhiyun 	return 0;
542*4882a593Smuzhiyun }
543*4882a593Smuzhiyun 
es8326_mute(struct snd_soc_dai * dai,int mute,int stream)544*4882a593Smuzhiyun static int es8326_mute(struct snd_soc_dai *dai, int mute, int stream)
545*4882a593Smuzhiyun {
546*4882a593Smuzhiyun 	struct snd_soc_component *component = dai->component;
547*4882a593Smuzhiyun 	struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
548*4882a593Smuzhiyun 
549*4882a593Smuzhiyun 	if (stream == SNDRV_PCM_STREAM_CAPTURE)
550*4882a593Smuzhiyun 		return 0;
551*4882a593Smuzhiyun 
552*4882a593Smuzhiyun 	if (es8326->hp_inserted)
553*4882a593Smuzhiyun 		return 0;
554*4882a593Smuzhiyun 
555*4882a593Smuzhiyun 	if (mute) {
556*4882a593Smuzhiyun 		es8326_set_gpio(es8326, ES8326_CODEC_SET_SPK, 0);
557*4882a593Smuzhiyun 		es8326_set_gpio(es8326, ES8326_CODEC_SET_HP, 0);
558*4882a593Smuzhiyun 	} else {
559*4882a593Smuzhiyun 		es8326_set_gpio(es8326, ES8326_CODEC_SET_SPK, 1);
560*4882a593Smuzhiyun 		es8326_set_gpio(es8326, ES8326_CODEC_SET_HP, 1);
561*4882a593Smuzhiyun 	}
562*4882a593Smuzhiyun 	return 0;
563*4882a593Smuzhiyun }
564*4882a593Smuzhiyun 
es8326_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)565*4882a593Smuzhiyun static int es8326_set_bias_level(struct snd_soc_component *component,
566*4882a593Smuzhiyun 				 enum snd_soc_bias_level level)
567*4882a593Smuzhiyun {
568*4882a593Smuzhiyun 	struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
569*4882a593Smuzhiyun 	int ret;
570*4882a593Smuzhiyun 
571*4882a593Smuzhiyun 	switch (level) {
572*4882a593Smuzhiyun 	case SND_SOC_BIAS_ON:
573*4882a593Smuzhiyun 		dev_dbg(component->dev, "%s SND_SOC_BIAS_ON\n", __func__);
574*4882a593Smuzhiyun 		break;
575*4882a593Smuzhiyun 	case SND_SOC_BIAS_PREPARE:
576*4882a593Smuzhiyun 		dev_dbg(component->dev, "%s SND_SOC_BIAS_PREPARE\n", __func__);
577*4882a593Smuzhiyun 		if (!IS_ERR(es8326->mclk)) {
578*4882a593Smuzhiyun 			if (snd_soc_component_get_bias_level(component) ==
579*4882a593Smuzhiyun 			    SND_SOC_BIAS_ON) {
580*4882a593Smuzhiyun 				clk_disable_unprepare(es8326->mclk);
581*4882a593Smuzhiyun 			} else {
582*4882a593Smuzhiyun 				ret = clk_prepare_enable(es8326->mclk);
583*4882a593Smuzhiyun 				if (ret)
584*4882a593Smuzhiyun 					return ret;
585*4882a593Smuzhiyun 			}
586*4882a593Smuzhiyun 		}
587*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x01, 0x7F);
588*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x00, 0x00);
589*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x59, 0x45);
590*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x5A, 0x90);
591*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x5B, 0x00);
592*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x03, 0x05);
593*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x24, 0x00);
594*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x18, 0x02);
595*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x16, 0x00);
596*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x17, 0x40);
597*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x25, 0xAA);
598*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x15, 0x00);
599*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x00, 0x80);
600*4882a593Smuzhiyun 		break;
601*4882a593Smuzhiyun 	case SND_SOC_BIAS_STANDBY:
602*4882a593Smuzhiyun 		dev_dbg(component->dev, "%s SND_SOC_BIAS_STANDBY\n", __func__);
603*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x15, 0x1F);
604*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x25, 0x11);
605*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x00, 0x20);
606*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x17, 0xF8);
607*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x16, 0xFB);
608*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x18, 0x00);
609*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x24, 0x0F);
610*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x58, 0x08);
611*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x5A, 0x00);
612*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x5B, 0x00);
613*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x00, 0x2F);
614*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x01, 0x00);
615*4882a593Smuzhiyun 		break;
616*4882a593Smuzhiyun 	case SND_SOC_BIAS_OFF:
617*4882a593Smuzhiyun 		dev_dbg(component->dev, "%s SND_SOC_BIAS_OFF\n", __func__);
618*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x15, 0x1F);
619*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x25, 0x11);
620*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x00, 0x20);
621*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x17, 0xF8);
622*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x16, 0xFB);
623*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x18, 0x00);
624*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x24, 0x0F);
625*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x58, 0x08);
626*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x5A, 0x00);
627*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x5B, 0x00);
628*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x00, 0x2F);
629*4882a593Smuzhiyun 		snd_soc_component_write(component, 0x01, 0x00);
630*4882a593Smuzhiyun 		break;
631*4882a593Smuzhiyun 	}
632*4882a593Smuzhiyun 	return 0;
633*4882a593Smuzhiyun }
634*4882a593Smuzhiyun 
635*4882a593Smuzhiyun #define es8326_RATES SNDRV_PCM_RATE_8000_96000
636*4882a593Smuzhiyun 
637*4882a593Smuzhiyun #define es8326_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
638*4882a593Smuzhiyun 			SNDRV_PCM_FMTBIT_S18_3LE |\
639*4882a593Smuzhiyun 			SNDRV_PCM_FMTBIT_S20_3LE |\
640*4882a593Smuzhiyun 			SNDRV_PCM_FMTBIT_S24_LE |\
641*4882a593Smuzhiyun 			SNDRV_PCM_FMTBIT_S32_LE)
642*4882a593Smuzhiyun 
643*4882a593Smuzhiyun static const struct snd_soc_dai_ops es8326_ops = {
644*4882a593Smuzhiyun 	.hw_params = es8326_pcm_hw_params,
645*4882a593Smuzhiyun 	.set_fmt = es8326_set_dai_fmt,
646*4882a593Smuzhiyun 	.set_sysclk = es8326_set_dai_sysclk,
647*4882a593Smuzhiyun 	.mute_stream = es8326_mute,
648*4882a593Smuzhiyun };
649*4882a593Smuzhiyun 
650*4882a593Smuzhiyun static struct snd_soc_dai_driver es8326_dai = {
651*4882a593Smuzhiyun 	.name = "ES8326 HiFi",
652*4882a593Smuzhiyun 	.playback = {
653*4882a593Smuzhiyun 		     .stream_name = "Playback",
654*4882a593Smuzhiyun 		     .channels_min = 1,
655*4882a593Smuzhiyun 		     .channels_max = 2,
656*4882a593Smuzhiyun 		     .rates = es8326_RATES,
657*4882a593Smuzhiyun 		     .formats = es8326_FORMATS,
658*4882a593Smuzhiyun 		     },
659*4882a593Smuzhiyun 	.capture = {
660*4882a593Smuzhiyun 		    .stream_name = "Capture",
661*4882a593Smuzhiyun 		    .channels_min = 1,
662*4882a593Smuzhiyun 		    .channels_max = 2,
663*4882a593Smuzhiyun 		    .rates = es8326_RATES,
664*4882a593Smuzhiyun 		    .formats = es8326_FORMATS,
665*4882a593Smuzhiyun 		    },
666*4882a593Smuzhiyun 	.ops = &es8326_ops,
667*4882a593Smuzhiyun };
668*4882a593Smuzhiyun 
es8326_suspend(struct snd_soc_component * component)669*4882a593Smuzhiyun static int es8326_suspend(struct snd_soc_component *component)
670*4882a593Smuzhiyun {
671*4882a593Smuzhiyun 	/* TBD */
672*4882a593Smuzhiyun 	/* snd_soc_component_write(component, 0x19, 0x06); */
673*4882a593Smuzhiyun 	return 0;
674*4882a593Smuzhiyun }
675*4882a593Smuzhiyun 
es8326_resume(struct snd_soc_component * component)676*4882a593Smuzhiyun static int es8326_resume(struct snd_soc_component *component)
677*4882a593Smuzhiyun {
678*4882a593Smuzhiyun 	/* TBD */
679*4882a593Smuzhiyun 	/* snd_soc_component_write(component, 0x2b, 0x80); */
680*4882a593Smuzhiyun 	return 0;
681*4882a593Smuzhiyun }
682*4882a593Smuzhiyun 
es8326_probe(struct snd_soc_component * component)683*4882a593Smuzhiyun static int es8326_probe(struct snd_soc_component *component)
684*4882a593Smuzhiyun {
685*4882a593Smuzhiyun 	struct es8326_priv *es8326;
686*4882a593Smuzhiyun 	int ret = 0;
687*4882a593Smuzhiyun 
688*4882a593Smuzhiyun 	if (component == NULL)
689*4882a593Smuzhiyun 		return -ENODEV;
690*4882a593Smuzhiyun 
691*4882a593Smuzhiyun 	es8326 = snd_soc_component_get_drvdata(component);
692*4882a593Smuzhiyun 	es8326->component = component;
693*4882a593Smuzhiyun 
694*4882a593Smuzhiyun 	es8326->mclk = devm_clk_get_optional(component->dev, "mclk");
695*4882a593Smuzhiyun 	if (IS_ERR(es8326->mclk)) {
696*4882a593Smuzhiyun 		dev_err(component->dev, "%s,unable to get mclk\n", __func__);
697*4882a593Smuzhiyun 		return PTR_ERR(es8326->mclk);
698*4882a593Smuzhiyun 	}
699*4882a593Smuzhiyun 	if (!es8326->mclk)
700*4882a593Smuzhiyun 		dev_err(component->dev, "%s, assuming static mclk\n", __func__);
701*4882a593Smuzhiyun 
702*4882a593Smuzhiyun 	ret = clk_prepare_enable(es8326->mclk);
703*4882a593Smuzhiyun 	if (ret) {
704*4882a593Smuzhiyun 		dev_err(component->dev, "%s, unable to enable mclk\n", __func__);
705*4882a593Smuzhiyun 		return ret;
706*4882a593Smuzhiyun 	}
707*4882a593Smuzhiyun 
708*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x04, 0x3C);
709*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x01, 0x7F);
710*4882a593Smuzhiyun 	snd_soc_component_write(component, 0xF9, 0x02);
711*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x02, 0x00);
712*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x03, 0x05);
713*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x04, 0x01);
714*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x05, 0x00);
715*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x06, 0x30);
716*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x07, 0x2D);
717*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x08, 0x26);
718*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x09, 0x26);
719*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x0A, 0x1F);
720*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x0B, 0x1F);
721*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x0C, 0x1F);
722*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x10, 0xC8);
723*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x11, 0x88);
724*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x12, 0x20);
725*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x13, 0x00);
726*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x14, 0x00);
727*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x19, 0xF0);
728*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x1D, 0x08);
729*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x23, 0x10);
730*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x25, 0x22);
731*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x29, 0x00);
732*4882a593Smuzhiyun 	/* snd_soc_component_write(component,0x2A,0x00); */
733*4882a593Smuzhiyun 	/* snd_soc_component_write(component,0x2B,0x44); */
734*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x2A, es8326->mic2_src);
735*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x2B, es8326->mic2_src);
736*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x2C, 0xFF);
737*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x2D, 0xFF);
738*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x2E, 0x00);
739*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x4A, 0x00);
740*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x4D, 0x08);
741*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x4E, 0x20);
742*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x4F, 0x15);
743*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x50, 0xBF);
744*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x56, 0x88);
745*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x57, 0x10 | es8326->jack_pol);
746*4882a593Smuzhiyun 	/* snd_soc_component_write(component,0x57,0x1f); */
747*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x58, 0x08);
748*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x59, 0x45);
749*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x5A, 0x90);
750*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x5B, 0x00);
751*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x15, 0x00);
752*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x00, 0x80);
753*4882a593Smuzhiyun 	snd_soc_component_write(component, 0x27, 0x77);
754*4882a593Smuzhiyun 
755*4882a593Smuzhiyun 	es8326_set_bias_level(component, SND_SOC_BIAS_STANDBY);
756*4882a593Smuzhiyun 	return 0;
757*4882a593Smuzhiyun }
758*4882a593Smuzhiyun 
es8326_remove(struct snd_soc_component * component)759*4882a593Smuzhiyun static void es8326_remove(struct snd_soc_component *component)
760*4882a593Smuzhiyun {
761*4882a593Smuzhiyun 	es8326_set_bias_level(component, SND_SOC_BIAS_OFF);
762*4882a593Smuzhiyun }
763*4882a593Smuzhiyun 
es8326_enable_jack_detect(struct snd_soc_component * component,struct snd_soc_jack * jack)764*4882a593Smuzhiyun static void es8326_enable_jack_detect(struct snd_soc_component *component,
765*4882a593Smuzhiyun 				      struct snd_soc_jack *jack)
766*4882a593Smuzhiyun {
767*4882a593Smuzhiyun 	struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
768*4882a593Smuzhiyun 
769*4882a593Smuzhiyun 	mutex_lock(&es8326->lock);
770*4882a593Smuzhiyun 	es8326->jack = jack;
771*4882a593Smuzhiyun 	mutex_unlock(&es8326->lock);
772*4882a593Smuzhiyun 
773*4882a593Smuzhiyun 	/* Enable irq and sync initial jack state */
774*4882a593Smuzhiyun 	enable_irq(es8326->irq);
775*4882a593Smuzhiyun 	queue_delayed_work(system_power_efficient_wq,
776*4882a593Smuzhiyun 			   &es8326->hpdet_work, msecs_to_jiffies(10));
777*4882a593Smuzhiyun }
778*4882a593Smuzhiyun 
es8326_disable_jack_detect(struct snd_soc_component * component)779*4882a593Smuzhiyun static void es8326_disable_jack_detect(struct snd_soc_component *component)
780*4882a593Smuzhiyun {
781*4882a593Smuzhiyun 	struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
782*4882a593Smuzhiyun 
783*4882a593Smuzhiyun 	if (!es8326->jack)
784*4882a593Smuzhiyun 		return;
785*4882a593Smuzhiyun 
786*4882a593Smuzhiyun 	disable_irq(es8326->irq);
787*4882a593Smuzhiyun 
788*4882a593Smuzhiyun 	mutex_lock(&es8326->lock);
789*4882a593Smuzhiyun 	if (es8326->jack->status & SND_JACK_MICROPHONE)
790*4882a593Smuzhiyun 		snd_soc_jack_report(es8326->jack, 0, SND_JACK_BTN_0);
791*4882a593Smuzhiyun 	es8326->jack = NULL;
792*4882a593Smuzhiyun 	mutex_unlock(&es8326->lock);
793*4882a593Smuzhiyun }
794*4882a593Smuzhiyun 
es8326_set_jack(struct snd_soc_component * component,struct snd_soc_jack * jack,void * data)795*4882a593Smuzhiyun static int es8326_set_jack(struct snd_soc_component *component,
796*4882a593Smuzhiyun 			   struct snd_soc_jack *jack, void *data)
797*4882a593Smuzhiyun {
798*4882a593Smuzhiyun 	dev_info(component->dev, "Enter into %s jack:%p\n", __func__, jack);
799*4882a593Smuzhiyun 	if (jack)
800*4882a593Smuzhiyun 		es8326_enable_jack_detect(component, jack);
801*4882a593Smuzhiyun 	else
802*4882a593Smuzhiyun 		es8326_disable_jack_detect(component);
803*4882a593Smuzhiyun 	return 0;
804*4882a593Smuzhiyun }
805*4882a593Smuzhiyun 
806*4882a593Smuzhiyun static const struct snd_soc_component_driver soc_codec_dev_es8326 = {
807*4882a593Smuzhiyun 	.probe = es8326_probe,
808*4882a593Smuzhiyun 	.remove = es8326_remove,
809*4882a593Smuzhiyun 	.suspend = es8326_suspend,
810*4882a593Smuzhiyun 	.resume = es8326_resume,
811*4882a593Smuzhiyun 	.set_bias_level = es8326_set_bias_level,
812*4882a593Smuzhiyun 	.set_jack = es8326_set_jack,
813*4882a593Smuzhiyun 
814*4882a593Smuzhiyun 	.dapm_widgets = es8326_dapm_widgets,
815*4882a593Smuzhiyun 	.num_dapm_widgets = ARRAY_SIZE(es8326_dapm_widgets),
816*4882a593Smuzhiyun 	.dapm_routes = es8326_dapm_routes,
817*4882a593Smuzhiyun 	.num_dapm_routes = ARRAY_SIZE(es8326_dapm_routes),
818*4882a593Smuzhiyun 	.controls = es8326_snd_controls,
819*4882a593Smuzhiyun 	.num_controls = ARRAY_SIZE(es8326_snd_controls),
820*4882a593Smuzhiyun };
821*4882a593Smuzhiyun 
es8326_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)822*4882a593Smuzhiyun static int es8326_i2c_probe(struct i2c_client *i2c,
823*4882a593Smuzhiyun 			    const struct i2c_device_id *id)
824*4882a593Smuzhiyun {
825*4882a593Smuzhiyun 	struct i2c_adapter *adapter = to_i2c_adapter(i2c->dev.parent);
826*4882a593Smuzhiyun 	struct es8326_priv *es8326;
827*4882a593Smuzhiyun 	u8 reg = 0x00;
828*4882a593Smuzhiyun 	int ret = -1;
829*4882a593Smuzhiyun 
830*4882a593Smuzhiyun 	if (!i2c_check_functionality(adapter, I2C_FUNC_I2C)) {
831*4882a593Smuzhiyun 		dev_warn(&adapter->dev,
832*4882a593Smuzhiyun 			 "I2C-Adapter doesn't support I2C_FUNC_I2C\n");
833*4882a593Smuzhiyun 		return -EIO;
834*4882a593Smuzhiyun 	}
835*4882a593Smuzhiyun 
836*4882a593Smuzhiyun 	es8326 = devm_kzalloc(&i2c->dev, sizeof(struct es8326_priv), GFP_KERNEL);
837*4882a593Smuzhiyun 	if (es8326 == NULL)
838*4882a593Smuzhiyun 		return -ENOMEM;
839*4882a593Smuzhiyun 
840*4882a593Smuzhiyun 	i2c_set_clientdata(i2c, es8326);
841*4882a593Smuzhiyun 	es8326->i2c = i2c;
842*4882a593Smuzhiyun 	es8326->hp_inserted = 0;
843*4882a593Smuzhiyun 
844*4882a593Smuzhiyun 	mutex_init(&es8326->lock);
845*4882a593Smuzhiyun 	es8326->regmap = devm_regmap_init_i2c(i2c, &es8326_regmap_config);
846*4882a593Smuzhiyun 	if (IS_ERR(es8326->regmap)) {
847*4882a593Smuzhiyun 		ret = PTR_ERR(es8326->regmap);
848*4882a593Smuzhiyun 		dev_err(&i2c->dev, "Failed to init regmap: %d\n", ret);
849*4882a593Smuzhiyun 		return ret;
850*4882a593Smuzhiyun 	}
851*4882a593Smuzhiyun 
852*4882a593Smuzhiyun 	es8326->spk_ctl_gpio = devm_gpiod_get_optional(&i2c->dev,
853*4882a593Smuzhiyun 						       "spk-con",
854*4882a593Smuzhiyun 						       GPIOD_OUT_LOW);
855*4882a593Smuzhiyun 	if (IS_ERR(es8326->spk_ctl_gpio))
856*4882a593Smuzhiyun 		return PTR_ERR(es8326->spk_ctl_gpio);
857*4882a593Smuzhiyun 
858*4882a593Smuzhiyun 	es8326->hp_ctl_gpio = devm_gpiod_get_optional(&i2c->dev,
859*4882a593Smuzhiyun 						      "hp-con", GPIOD_OUT_LOW);
860*4882a593Smuzhiyun 	if (IS_ERR(es8326->hp_ctl_gpio))
861*4882a593Smuzhiyun 		return PTR_ERR(es8326->hp_ctl_gpio);
862*4882a593Smuzhiyun 
863*4882a593Smuzhiyun 	ret = i2c_master_recv(i2c, &reg, 1);
864*4882a593Smuzhiyun 	if (ret < 0) {
865*4882a593Smuzhiyun 		dev_err(&i2c->dev, "i2c recv Failed\n");
866*4882a593Smuzhiyun 		return ret;
867*4882a593Smuzhiyun 	}
868*4882a593Smuzhiyun 
869*4882a593Smuzhiyun 	/* TODO */
870*4882a593Smuzhiyun 	es8326->mastermode = device_property_read_bool(&i2c->dev, "mastermode");
871*4882a593Smuzhiyun 	dev_dbg(&i2c->dev, "master mode %d", es8326->mastermode);
872*4882a593Smuzhiyun 
873*4882a593Smuzhiyun 	ret = of_property_read_u8(i2c->dev.of_node, "mic1-src",
874*4882a593Smuzhiyun 				  &es8326->mic1_src);
875*4882a593Smuzhiyun 	if (ret != 0) {
876*4882a593Smuzhiyun 		dev_dbg(&i2c->dev, "mic1-src return %d", ret);
877*4882a593Smuzhiyun 		es8326->mic1_src = 0x22;
878*4882a593Smuzhiyun 	}
879*4882a593Smuzhiyun 	dev_dbg(&i2c->dev, "mic1-src %x", es8326->mic1_src);
880*4882a593Smuzhiyun 
881*4882a593Smuzhiyun 	ret = of_property_read_u8(i2c->dev.of_node, "mic2-src",
882*4882a593Smuzhiyun 				  &es8326->mic2_src);
883*4882a593Smuzhiyun 	if (ret != 0) {
884*4882a593Smuzhiyun 		dev_dbg(&i2c->dev, "mic2-src return %d", ret);
885*4882a593Smuzhiyun 		es8326->mic2_src = 0x44;
886*4882a593Smuzhiyun 	}
887*4882a593Smuzhiyun 	dev_dbg(&i2c->dev, "mic2-src %x", es8326->mic2_src);
888*4882a593Smuzhiyun 
889*4882a593Smuzhiyun 	ret = of_property_read_u8(i2c->dev.of_node, "jack-pol",
890*4882a593Smuzhiyun 				  &es8326->jack_pol);
891*4882a593Smuzhiyun 	if (ret != 0) {
892*4882a593Smuzhiyun 		dev_dbg(&i2c->dev, "jack-pol return %d", ret);
893*4882a593Smuzhiyun 		es8326->jack_pol = 0x0f;
894*4882a593Smuzhiyun 	}
895*4882a593Smuzhiyun 	dev_dbg(&i2c->dev, "jack-pol %x", es8326->jack_pol);
896*4882a593Smuzhiyun 
897*4882a593Smuzhiyun 	ret = of_property_read_u32(i2c->dev.of_node, "mclk-rate",
898*4882a593Smuzhiyun 				   &es8326->mclk_rate);
899*4882a593Smuzhiyun 	if (ret != 0) {
900*4882a593Smuzhiyun 		dev_dbg(&i2c->dev, "mclk-rate return %d", ret);
901*4882a593Smuzhiyun 		es8326->mclk_rate = 12288000;
902*4882a593Smuzhiyun 	}
903*4882a593Smuzhiyun 	dev_dbg(&i2c->dev, "mclk-rate %u", es8326->mclk_rate);
904*4882a593Smuzhiyun 
905*4882a593Smuzhiyun 	INIT_DELAYED_WORK(&es8326->hpdet_work, es8326_hpdetect_work);
906*4882a593Smuzhiyun 
907*4882a593Smuzhiyun 	es8326->irq = i2c->irq;
908*4882a593Smuzhiyun 	ret = devm_request_threaded_irq(&i2c->dev, es8326->irq, NULL, es8326_irq,
909*4882a593Smuzhiyun 					IRQF_TRIGGER_RISING |
910*4882a593Smuzhiyun 					IRQF_TRIGGER_FALLING |
911*4882a593Smuzhiyun 					IRQF_ONESHOT,
912*4882a593Smuzhiyun 					"es8326", es8326);
913*4882a593Smuzhiyun 	if (ret < 0) {
914*4882a593Smuzhiyun 		dev_err(&i2c->dev, "Getting irq failed.");
915*4882a593Smuzhiyun 		return -EINVAL;
916*4882a593Smuzhiyun 	}
917*4882a593Smuzhiyun 
918*4882a593Smuzhiyun 	disable_irq(es8326->irq);
919*4882a593Smuzhiyun 	dev_info(&i2c->dev, "Getting irq success.");
920*4882a593Smuzhiyun 
921*4882a593Smuzhiyun 	return snd_soc_register_component(&i2c->dev, &soc_codec_dev_es8326,
922*4882a593Smuzhiyun 					  &es8326_dai, 1);
923*4882a593Smuzhiyun }
924*4882a593Smuzhiyun 
925*4882a593Smuzhiyun #ifdef CONFIG_OF
926*4882a593Smuzhiyun static const struct i2c_device_id es8326_i2c_id[] = {
927*4882a593Smuzhiyun 	{"es8326", 0},
928*4882a593Smuzhiyun 	{}
929*4882a593Smuzhiyun };
930*4882a593Smuzhiyun 
931*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, es8326_i2c_id);
932*4882a593Smuzhiyun #endif
933*4882a593Smuzhiyun 
934*4882a593Smuzhiyun #ifdef CONFIG_ACPI
935*4882a593Smuzhiyun static const struct acpi_device_id es8326_acpi_match[] = {
936*4882a593Smuzhiyun 	{"ESSX8326", 0},
937*4882a593Smuzhiyun 	{},
938*4882a593Smuzhiyun };
939*4882a593Smuzhiyun 
940*4882a593Smuzhiyun MODULE_DEVICE_TABLE(acpi, es8326_acpi_match);
941*4882a593Smuzhiyun #endif
942*4882a593Smuzhiyun 
943*4882a593Smuzhiyun static const struct of_device_id es8326_of_match[] = {
944*4882a593Smuzhiyun 	{.compatible = "everest,es8326",},
945*4882a593Smuzhiyun 	{}
946*4882a593Smuzhiyun };
947*4882a593Smuzhiyun 
948*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, es8326_of_match);
949*4882a593Smuzhiyun 
950*4882a593Smuzhiyun static struct i2c_driver es8326_i2c_driver = {
951*4882a593Smuzhiyun 	.driver = {
952*4882a593Smuzhiyun 		   .name = "ES8326",
953*4882a593Smuzhiyun #ifdef CONFIG_ACPI
954*4882a593Smuzhiyun 		   .acpi_match_table = ACPI_PTR(es8326_acpi_match),
955*4882a593Smuzhiyun #endif
956*4882a593Smuzhiyun 		   .of_match_table = of_match_ptr(es8326_of_match),
957*4882a593Smuzhiyun 		   },
958*4882a593Smuzhiyun 	.probe = es8326_i2c_probe,
959*4882a593Smuzhiyun 	.id_table = es8326_i2c_id,
960*4882a593Smuzhiyun };
961*4882a593Smuzhiyun module_i2c_driver(es8326_i2c_driver);
962*4882a593Smuzhiyun 
963*4882a593Smuzhiyun MODULE_DESCRIPTION("Everest Semi ES8326 ALSA SoC Codec Driver");
964*4882a593Smuzhiyun MODULE_AUTHOR("David <zhuning@everset-semi.com>");
965*4882a593Smuzhiyun MODULE_LICENSE("GPL");
966